Key phases of this project are:
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* Assessment of the missing RISC-V instructions (RISC-V RV64GC is only 96 instructions whereas POWER ISA SFFS is 214) which are present in Power ISA 3.0
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* Implementation of the missing RISC-V instructions and instruction forms that makes is comparable with POWER ISA in the Scalar ISA space.
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* Assessment of application of Simple-V Vector Prefixing to SVP64, building on the work already done under NLnet Grant 2019-10-012 <https://libre-soc.org/nlnet_2018/>
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* Implementation of Simple-V in the Libre-SOC Simulator, ISACaller.
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* Assembler and disassembler of RISC-V instructions and also SVP64 in the Libre-SOC infrastructure.
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* Upgrading (with the newly created instructions and forms) sv-spike assembler development which was prototyped previously for Simple-V Specification:
<https://git.libre-soc.org/?p=riscv-isa-sim.git;a=shortlog;h=refs/heads/sv>
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* Adding a comprehensive unit test base for the new instructions which can then be tested against sv-spike as well as ISACaller. Conversion of previously created instructions to the new format used in Libre-SOC, and adding the newly defined and created instructions.
<https://git.libre-soc.org/?p=riscv-tests.git;a=shortlog;h=refs/heads/sv>
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* Documentation, demonstrations and Conference Papers. This will include porting results of other completed projects (cryptoprimitives, video) from POWER ISA to the RISC-V/Simple-V/SVP64 environment
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* Research and assessment of ARM7 and i486 (both on opencores.org)as to their feasibility for applying Simple-V Prefixing in future development projects
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# Does the project have other funding sources, both past and present?
NGI Search, NGI POINTER, and NLnet Grants have been the sole source of funding
projects / libreriscv.git / commitdiff