(no commit message)

diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index ff992e4f90877665164a3f68d7d6667a2d7bfd57..9223fcfa22fa97fa50227cf6ef90aea1aa1ed316 100644 (file)
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -256,7 +256,7 @@ This is part of `scalar identity behaviour` described above.
 
 The Scalar Power ISA Condition Register is a 64 bit register where the top
 32 MSBs (numbered 0:31 in MSB0 numbering) are not used.  This convention is
-*preserved* (not modified, respected, and thus coipied)
+*preserved*
 in SVP64 and an additional 15 Condition Registers provided in
 order to store the new CR Fields, CR8-CR15, CR16-CR23 etc. sequentially.
 The top 32 MSBs in each new SVP64 Condition Register are *also* not used:
@@ -289,7 +289,9 @@ Register).  Further discussion is out of scope for this version of SVP64.
 Additionally, a future variant of SVP64 will be applied to the Scalar
 (Quad-precision and 128-bit) VSX instructions. Element-width overrides
 are an opportunity to expand the Power ISA to 256-bit, 512-bit and
-1024-bit operations.
+1024-bit operations, as well as doubling or quadrupling the number
+of CSX registers to 128 or 256. Again further discussion is out of
+scope for this version of SVP64
 
 --------