replace halfs with hwords in svp64.mdwn

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index fe4b8a3fd71cc63ae14cf74796117eca2001f604..38e19355927a3216dc85410387a74ea59140f9b9 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -180,7 +180,8 @@ The Canonical specification for how element-sequential numbering and
 element-width overrides is defined is expressed in the following c
 structure, assuming a Little-Endian system, and naturally using LSB0
 numbering everywhere because the ANSI c specification is inherently LSB0.
-Note the deliberate similarity to how VSX register elements are defined:
+Note the deliberate similarity to how VSX register elements are defined,
+from Figure 97, Book I, Section 6.3, Page 258:
 
 ```
     #pragma pack
@@ -223,9 +224,9 @@ Example Vector-looped add operation implementation when elwidths are 64-bit:
 However if elwidth overrides are set to 16 for both source and destination:
 
 ```
-    # vector-add RT, RA, RB using the "uint64_t" union member "halfs"
+    # vector-add RT, RA, RB using the "uint64_t" union member "hwords"
     for i in range(VL):
-        int_regfile[RT].halfs[i] = int_regfile[RA].halfs[i] + int_regfile[RB].halfs[i]
+        int_regfile[RT].hwords[i] = int_regfile[RA].hwords[i] + int_regfile[RB].hwords[i]
 ```
 
 The most fundamental aspect here to understand is that the wrapping into
@@ -400,12 +401,12 @@ that VSR register elements are static bounded:
 And finally use these functions:
 
 ```
-    # VSX-add RT, RA, RB using the "uint64_t" union member "halfs"
+    # VSX-add RT, RA, RB using the "uint64_t" union member "hwords"
     for i in range(VL):
          el_reg_t result, ra, rb;
         _get_VSR_element(&ra, RA, i, 16);
         _get_VSR_element(&rb, RB, i, 16);
-         result.halfs[0] = ra.halfs[0] + rb.halfs[0]; // use array 0 elements
+         result.hwords[0] = ra.hwords[0] + rb.hwords[0]; // use array 0 elements
         _set_VSR_element(&result, RT, i, 16);
 
 ```