(no commit message)

diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index 3ed1b98762af5f5f2cd66ffff329154c37783254..41b01a26648e0a58a0db42afd5af1764c4bd2ad2 100644 (file)
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -1152,6 +1152,7 @@ which creates scenarios unique to Vector applications, that a Scalar
 (and even a SIMD) ISA simply never encounters.  SVP64 endeavours to add
 the modes typically found in *all* Scalable Vector ISAs, without changing
 the behaviour of the underlying Base (Scalar) v3.0B operations in any way.
+(The sole apparent exception is Post-Increment Mode on LD/ST-update instructions)
 
 ## Modes overview