Fisrt attempt at floorplaning test_issuer.

diff --git a/experiments9/GUIDELINES.rst b/experiments9/GUIDELINES.rst
new file mode 100644 (file)
index 0000000..e00670f
--- /dev/null
+++ b/experiments9/GUIDELINES.rst
@@ -0,0 +1,114 @@
+
+
+================================
+Quick Guidelines on Floorplaning
+================================
+
+
+Some hints about how to avoid common pitfall making the floorplan.
+
+Terminology:
+
+* ``Cell`` : Even if in Hurricane it contain both the netlist and
+  the layout, in this context we will consider it as a pure netlist.
+
+* ``Block`` : The Python class wrapper around a ``Cell`` to change it
+  into a placed and routed layout used as black box by the above
+  hierarchical levels. It is both the program that perform the P&R
+  and a cache for upper levels.
+    If it contains no sub-blocks, it is placed flat (virtual flatten).
+
+
+Disclaimer
+==========
+
+At this moment, the Block tools can hardly be called floorplaner.
+They provides very basic facility for manual floorplanning.
+
+
+Layout Caching
+==============
+
+To create a block from a ``Cell``:
+
+.. code-block:: python
+
+   add = af.getCell( 'add', CRL.Catalog.State.Views )
+   blockAdd = Block.create \
+       ( add
+       , ioPins=[ (IoPin.SOUTH|IoPin.A_BEGIN, 'a({})', l( 10.0), l(20.0), 16)
+                , (IoPin.SOUTH|IoPin.A_BEGIN, 'b({})', l( 20.0), l(20.0), 16)
+                , (IoPin.NORTH|IoPin.A_BEGIN, 'o({})', l(100.0), l(10.0), 16)
+                ]
+       )
+   blockAdd.state.cfg.etesian.spaceMargin = 0.10
+   blockAdd.state.fixedHeight = l(400)
+   blockAdd.state.useSpares   = False
+   blockAdd.state.editor      = editor
+   rvalue = blockAdd.build()
+
+
+If you load the ``Cell`` with the flag ``CRL.Catalog.State.Views``, the
+parser will attemps to load both the netlist (mandatory) and the layout.
+If the layout is present, then the block **will not be P&R again**,
+the current layout is reused.
+
+If you want to selectivelely rebuild one block, you can either remove
+the relevant ``ap`` file or change the loading flag to:
+
+.. code-block:: python
+
+   add = af.getCell( 'add', CRL.Catalog.State.Logical )
+
+
+Pin Placement
+=============
+
+Pin placement is critical both for the P&R of the block and the one
+of the above level. So here is some hints.
+
+* Do not pack pin as closely as possible. Try to leave at least one
+  free pitch between them. Otherwise it may create huge contention
+  point both inside the block and outside to access the block.
+
+* If there is a *sliced* structure, that is one same treatment is
+  done for each bit of the I/O busses, interleave the relevant
+  busses pins. For examle, instead of having: ::
+
+    a(0) a(1) a(2) a(3) b(0) b(1) b(2) b(3)
+
+  Try: ::
+
+    a(0) b(0) a(1) b(1) a(2) b(2) a(3) b(3)
+
+
+Aspect Ratio (aka Form Factor)
+==============================
+
+It is important to consider that the routing capacity in one direction
+is directly proportional to the length of the side of the abutment box
+in the perpandicular direction. So, if you make a very *flat* box,
+the number of horizontal tracks became limited, and may become not
+routable.
+
+This effect is related to the kind of graph of the netlist. If it
+has a strong pipeline structure, a very elongated shape may be still
+be possible.
+
+
+The Halo Parameter
+==================
+
+By default, the global router will search to connect all pins of a Net
+in the square area defined by the pins, inflated by the halo (the halo
+is given in number of GCells, that is the height of a standard cell).
+A problem arise if you have a net of only two pins (usually 60% of the
+nets are like that), each across of a huge block. To avoid being stuck,
+the halo must be increased by at least half the size of the biggest
+block dimension. Note that, by drastically increasing the search area
+it may slow down much the global router.
+
+.. code-block:: python
+
+   blockIssuer.state.cfg.katana.searchHalo = 10000
+ 

diff --git a/experiments9/Makefile b/experiments9/Makefile
index 8a00f933920c13352c0a13dfe6a2866fcfa5ee1b..8d413ba4b478afa50dfe5339cadf46c988f1a6dd 100755 (executable)
--- a/experiments9/Makefile
+++ b/experiments9/Makefile
@@ -3,7 +3,7 @@
        PHYSICAL_SYNTHESIS = Coriolis
                DESIGN_KIT = sxlib
 
-            YOSYS_SET_TOP = No
+            YOSYS_SET_TOP = Yes
             USE_CLOCKTREE = No
                 USE_DEBUG = No
                  USE_KITE = No

diff --git a/experiments9/cells.lst b/experiments9/cells.lst
index 463027f3b8cf589ceb798771a63b417f00d484c5..499bb7bce9798a355829660fe6131325b100c1d6 100644 (file)
--- a/experiments9/cells.lst
+++ b/experiments9/cells.lst
@@ -90,6 +90,7 @@ output_55
 output
 pdecode2
 pick
+pimem
 pipe_20
 pipe_34
 pipe_50

diff --git a/experiments9/coriolis2/katana.py b/experiments9/coriolis2/katana.py
new file mode 100644 (file)
index 0000000..0fddfda
--- /dev/null
+++ b/experiments9/coriolis2/katana.py
@@ -0,0 +1,3 @@
+from Hurricane import DebugSession
+
+#DebugSession.addToTrace( katana.getCell().getNet( 'cu_issue_i' ) )

diff --git a/experiments9/doDesign.py b/experiments9/doDesign.py
new file mode 100644 (file)
index 0000000..2aca99e
--- /dev/null
+++ b/experiments9/doDesign.py
@@ -0,0 +1,556 @@
+
+from   __future__ import print_function
+import sys
+import traceback
+import CRL
+import helpers
+from   helpers.io import ErrorMessage
+from   helpers.io import WarningMessage
+from   helpers    import trace, l
+import plugins
+from   Hurricane  import DbU
+from   Hurricane  import Pin
+from   Hurricane  import Transformation
+from   plugins.alpha.block.block         import Block
+from   plugins.alpha.block.configuration import IoPin
+
+
+af = CRL.AllianceFramework.get()
+
+
+def scriptMain ( **kw ):
+    """The mandatory function that Coriolis CGT/Unicorn will look for."""
+    global af
+
+    rvalue = True
+    try:
+        helpers.setTraceLevel( 550 )
+        cell, editor = plugins.kwParseMain( **kw )
+
+        alu0 = af.getCell( 'alu0', CRL.Catalog.State.Views )
+        blockAlu0 = Block.create \
+            ( alu0
+            , ioPins=[ (IoPin.WEST |IoPin.A_BEGIN, 'clk'                             , 0 )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_issue_i'                      , 0 )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_imm_data_imm_ok' , 0 )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_invert_a'        , 0 )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_invert_out'      , 0 )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_is_32bit'        , 0 )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_is_signed'       , 0 )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_oe_oe'           , 0 )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_oe_oe_ok'        , 0 )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_output_carry'    , 0 )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_rc_rc'           , 0 )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_rc_rc_ok'        , 0 )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_write_cr0'       , 0 )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_zero_a'          , 0 )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'rst'                             , 0 )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'src3_i'                          , 0 )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_input_carry({})' , 0, l( 10.0),  2)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'src4_i({})'                      , 0, l( 10.0),  2)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_data_len({})'    , 0, l( 10.0),  4)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rd_go_i({})'                  , 0, l( 10.0),  4)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rdmaskn_i({})'                , 0, l( 10.0),  4)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_wr_go_i({})'                  , 0, l( 10.0),  5)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_insn_type({})'   , 0, l( 10.0),  7)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_fn_unit({})'     , 0, l( 10.0), 11)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_insn({})'        , 0, l( 10.0), 32)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_imm_data_imm({})', 0, l( 15.0), 64)
+                     , (IoPin.SOUTH              , 'src1_i({})'                      , l(10), l( 15.0), 64)
+                     , (IoPin.SOUTH              , 'src2_i({})'                      , l(15), l( 15.0), 64)
+                     , (IoPin.NORTH              , 'dest1_o({})'                     , l(20), l( 15.0), 64)
+                     , (IoPin.EAST |IoPin.A_END  , 'cu_busy_o'                       , 0 )
+                     , (IoPin.EAST |IoPin.A_END  , 'cr_a_ok'                         , 0 )
+                     , (IoPin.EAST |IoPin.A_END  , 'dest5_o'                         , 0 )
+                     , (IoPin.EAST |IoPin.A_END  , 'o_ok'                            , 0 )
+                     , (IoPin.EAST |IoPin.A_END  , 'xer_ca_ok'                       , 0 )
+                     , (IoPin.EAST |IoPin.A_END  , 'xer_ov_ok'                       , 0 )
+                     , (IoPin.EAST |IoPin.A_END  , 'xer_so_ok'                       , 0 )
+                     , (IoPin.EAST |IoPin.A_END  , 'dest3_o({})'                     , 0, l( 20.0),  2)
+                     , (IoPin.EAST |IoPin.A_END  , 'dest4_o({})'                     , 0, l( 20.0),  2)
+                     , (IoPin.EAST |IoPin.A_END  , 'dest2_o({})'                     , 0, l( 20.0),  4)
+                     , (IoPin.EAST |IoPin.A_END  , 'cu_rd_rel_o({})'                 , 0, l( 20.0),  4)
+                     , (IoPin.EAST |IoPin.A_END  , 'cu_wr_rel_o({})'                 , 0, l( 20.0),  5)
+                     ]
+            )
+        blockAlu0.state.cfg.etesian.spaceMargin = 0.05
+        blockAlu0.state.fixedHeight = l(5000)
+        blockAlu0.state.useSpares   = False
+       #rvalue = blockAlu0.build()
+
+        mul0 = af.getCell( 'mul0', CRL.Catalog.State.Views )
+        blockMul0 = Block.create \
+            ( mul0
+            , ioPins=[ (IoPin.NORTH              , 'clk'                             , l(4500.0) )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_issue_i'                      , 0, l(20) )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_imm_data_imm_ok' , 0, l(20) )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_invert_a'        , 0, l(20) )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_invert_out'      , 0, l(20) )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_is_32bit'        , 0, l(20) )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_is_signed'       , 0, l(20) )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_oe_oe'           , 0, l(20) )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_oe_oe_ok'        , 0, l(20) )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_rc_rc'           , 0, l(20) )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_rc_rc_ok'        , 0, l(20) )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_write_cr0'       , 0, l(20) )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_zero_a'          , 0, l(20) )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'rst'                             , 0, l(20) )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'src3_i'                          , 0, l(20) )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rd_go_i({})'                  , 0, l(10.0),  3)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rdmaskn_i({})'                , 0, l(10.0),  3)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_wr_go_i({})'                  , 0, l(10.0),  4)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_insn_type({})'   , 0, l(10.0),  7)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_fn_unit({})'     , 0, l(10.0), 11)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_insn({})'        , 0, l(10.0), 32)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_imm_data_imm({})', 0, l(15.0), 64)
+                     , (IoPin.SOUTH|IoPin.A_BEGIN, 'src1_i({})'                      , l(10.0), l(50.0), 64)
+                     , (IoPin.SOUTH|IoPin.A_BEGIN, 'src2_i({})'                      , l(20.0), l(50.0), 64)
+                     , (IoPin.EAST |IoPin.A_END  , 'cu_busy_o'                       , 0 )
+                     , (IoPin.EAST |IoPin.A_END  , 'cr_a_ok'                         , 0 )
+                     , (IoPin.EAST |IoPin.A_END  , 'dest4_o'                         , 0 )
+                     , (IoPin.EAST |IoPin.A_END  , 'o_ok'                            , 0 )
+                     , (IoPin.EAST |IoPin.A_END  , 'xer_ov_ok'                       , 0 )
+                     , (IoPin.EAST |IoPin.A_END  , 'xer_so_ok'                       , 0 )
+                     , (IoPin.EAST |IoPin.A_END  , 'dest3_o({})'                     , 0, l( 20.0),  2)
+                     , (IoPin.EAST |IoPin.A_END  , 'dest2_o({})'                     , 0, l( 20.0),  4)
+                     , (IoPin.EAST |IoPin.A_END  , 'cu_rd_rel_o({})'                 , 0, l( 20.0),  3)
+                     , (IoPin.EAST |IoPin.A_END  , 'cu_wr_rel_o({})'                 , 0, l( 20.0),  4)
+                     , (IoPin.NORTH|IoPin.A_END  , 'dest1_o({})'                     , 0, l( 30.0), 64)
+                     ]
+            )
+        blockMul0.state.cfg.etesian.uniformDensity = True
+        blockMul0.state.cfg.etesian.spaceMargin    = 0.10
+        blockMul0.state.cfg.katana.searchHalo      = 1
+        blockMul0.state.fixedHeight = l(5000)
+        blockMul0.state.useSpares   = False
+       #rvalue = blockMul0.build()
+
+        branch0 = af.getCell( 'branch0', CRL.Catalog.State.Views )
+        blockBranch0 = Block.create \
+            ( branch0
+            , ioPins=[ (IoPin.NORTH, 'clk'                                , l( 805.0) )
+                     , (IoPin.WEST , 'cu_issue_i'                         , l(  30.0) )
+                     , (IoPin.WEST , 'oper_i_alu_branch0_imm_data_imm_ok' , l(  40.0) )
+                     , (IoPin.WEST , 'oper_i_alu_branch0_is_32bit'        , l(  70.0) )
+                     , (IoPin.WEST , 'oper_i_alu_branch0_lk'              , l( 150.0) )
+                     , (IoPin.WEST , 'rst'                                , l( 160.0) )
+                     , (IoPin.WEST , 'src3_i({})'                         , l( 180.0), l( 10.0),  4)
+                     , (IoPin.WEST , 'cu_rd_go_i({})'                     , l( 270.0), l( 10.0),  3)
+                     , (IoPin.WEST , 'cu_rdmaskn_i({})'                   , l( 310.0), l( 10.0),  3)
+                     , (IoPin.WEST , 'cu_wr_go_i({})'                     , l( 350.0), l( 10.0),  3)
+                     , (IoPin.WEST , 'oper_i_alu_branch0_insn_type({})'   , l( 400.0), l( 10.0),  7)
+                     , (IoPin.WEST , 'oper_i_alu_branch0_fn_unit({})'     , l( 470.0), l( 10.0), 11)
+                     , (IoPin.WEST , 'oper_i_alu_branch0_insn({})'        , l( 580.0), l( 10.0), 32)
+                     , (IoPin.WEST , 'oper_i_alu_branch0_imm_data_imm({})', l( 900.0), l( 10.0), 64)
+                     , (IoPin.WEST , 'oper_i_alu_branch0_cia({})'         , l(1540.0), l( 10.0), 64)
+                     , (IoPin.SOUTH, 'src1_i({})'                         , l(  10.0), l( 20.0), 64)
+                     , (IoPin.SOUTH, 'src2_i({})'                         , l(  15.0), l( 20.0), 64)
+                     , (IoPin.EAST , 'cu_busy_o'                          , l(3500.0) )
+                     , (IoPin.EAST , 'fast1_ok'                           , l(3520.0) )
+                     , (IoPin.EAST , 'fast2_ok'                           , l(3540.0) )
+                     , (IoPin.EAST , 'nia_ok'                             , l(3560.0) )
+                     , (IoPin.EAST , 'dest2_o({})'                        , l(3580.0), l( 10.0), 64)
+                     , (IoPin.EAST , 'dest3_o({})'                        , l(4220.0), l( 10.0), 64)
+                     , (IoPin.EAST , 'cu_rd_rel_o({})'                    , l(4860.0), l( 20.0),  3)
+                     , (IoPin.EAST , 'cu_wr_rel_o({})'                    , l(4920.0), l( 20.0),  3)
+                     , (IoPin.NORTH, 'dest1_o({})'                        , l( 500.0), l( 10.0), 64)
+                     ]
+            )
+        blockBranch0.state.cfg.etesian.spaceMargin = 0.07
+        blockBranch0.state.fixedHeight = l(5000)
+        blockBranch0.state.useSpares   = False
+       #rvalue = blockBranch0.build()
+
+        cr0 = af.getCell( 'cr0', CRL.Catalog.State.Views )
+        blockCr0 = Block.create \
+            ( cr0
+            , ioPins=[ (IoPin.NORTH, 'clk'                                , l( 805.0) )
+                     , (IoPin.WEST , 'cu_issue_i'                         , l(  30.0) )
+                     , (IoPin.WEST , 'oper_i_alu_cr0_read_cr_whole'       , l(  40.0) )
+                     , (IoPin.WEST , 'oper_i_alu_cr0_write_cr_whole'      , l(  70.0) )
+                     , (IoPin.WEST , 'rst'                                , l( 160.0) )
+                     , (IoPin.WEST , 'src4_i({})'                         , l( 180.0), l( 10.0),  4)
+                     , (IoPin.WEST , 'src5_i({})'                         , l( 220.0), l( 10.0),  4)
+                     , (IoPin.WEST , 'src6_i({})'                         , l( 260.0), l( 10.0),  4)
+                     , (IoPin.WEST , 'cu_rd_go_i({})'                     , l( 300.0), l( 10.0),  6)
+                     , (IoPin.WEST , 'cu_rdmaskn_i({})'                   , l( 360.0), l( 10.0),  6)
+                     , (IoPin.WEST , 'cu_wr_go_i({})'                     , l( 420.0), l( 10.0),  3)
+                     , (IoPin.WEST , 'oper_i_alu_cr0_insn_type({})'       , l( 450.0), l( 10.0),  7)
+                     , (IoPin.WEST , 'oper_i_alu_cr0_fn_unit({})'         , l( 520.0), l( 10.0), 11)
+                     , (IoPin.WEST , 'oper_i_alu_cr0_insn({})'            , l( 630.0), l( 10.0), 32)
+                     , (IoPin.SOUTH, 'src1_i({})'                         , l(  10.0), l( 10.0), 64)
+                     , (IoPin.SOUTH, 'src2_i({})'                         , l(  15.0), l( 10.0), 64)
+                     , (IoPin.EAST , 'src3_i({})'                         , l(  10.0), l( 20.0), 32)
+                     , (IoPin.EAST , 'cu_busy_o'                          , l(4320.0) )
+                     , (IoPin.EAST , 'cr_a_ok'                            , l(4340.0) )
+                     , (IoPin.EAST , 'full_cr_ok'                         , l(4360.0) )
+                     , (IoPin.EAST , 'o_ok'                               , l(4380.0) )
+                     , (IoPin.EAST , 'dest2_o({})'                        , l(4400.0), l( 10.0), 32)
+                     , (IoPin.EAST , 'dest3_o({})'                        , l(4720.0), l( 10.0),  4)
+                     , (IoPin.EAST , 'cu_rd_rel_o({})'                    , l(4800.0), l( 20.0),  6)
+                     , (IoPin.EAST , 'cu_wr_rel_o({})'                    , l(4920.0), l( 20.0),  3)
+                     , (IoPin.NORTH, 'dest1_o({})'                        , l( 100.0), l( 10.0), 64)
+                     ]
+            )
+        blockCr0.state.cfg.etesian.spaceMargin = 0.10
+        blockCr0.state.fixedHeight = l(5000)
+        blockCr0.state.useSpares   = False
+       #rvalue = blockCr0.build()
+
+        ldst0 = af.getCell( 'ldst0', CRL.Catalog.State.Views )
+        blockLdst0 = Block.create \
+            ( ldst0
+            , ioPins=[ (IoPin.NORTH              , 'clk'                                , l(805.0) )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_ad_go_i'                         , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_issue_i'                         , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'ldst_port0_addr_exc_o'              , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'ldst_port0_addr_ok_o'               , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'ldst_port0_ld_data_o_ok'            , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_byte_reverse'     , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_imm_data_imm_ok'  , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_is_32bit'         , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_is_signed'        , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_oe_oe'            , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_oe_oe_ok'         , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_rc_rc'            , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_rc_rc_ok'         , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_sign_extend'      , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_zero_a'           , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'rst'                                , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_st_go_i'                         , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_ldst_mode({})'    , 0, l(20),  2)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rd_go_i({})'                     , 0, l(20),  3)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rdmaskn_i({})'                   , 0, l(20),  3)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_wr_go_i({})'                     , 0, l(20),  2)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_data_len({})'     , 0, l(20),  4)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_insn_type({})'    , 0, l(20),  7)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'ldst_port0_ld_data_o({})'           , 0, l(20), 64)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_imm_data_imm({})' , 0, l(20), 64)
+                     , (IoPin.SOUTH|IoPin.A_BEGIN, 'src1_i({})'                         , 0, l(10), 64)
+                     , (IoPin.SOUTH|IoPin.A_BEGIN, 'src2_i({})'                         , 0,  l(5), 64)
+                     , (IoPin.EAST |IoPin.A_END  , 'src3_i({})'                         , 0,     0, 64)
+                     , (IoPin.EAST |IoPin.A_END  , 'cu_busy_o'                          , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'cu_ad_rel_o'                        , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'ldst_port0_addr_i_ok'               , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'ldst_port0_is_ld_i'                 , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'ldst_port0_is_st_i'                 , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'load_mem_o'                         , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'cu_st_rel_o'                        , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'stwd_mem_o'                         , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'ea({})'                             , 0, l(20), 64)
+                     , (IoPin.EAST |IoPin.A_END  , 'ldst_port0_st_data_i({})'           , 0, l(20), 64)
+                     , (IoPin.EAST |IoPin.A_END  , 'cu_rd_rel_o({})'                    , 0,    0,   3)
+                     , (IoPin.EAST |IoPin.A_END  , 'cu_wr_rel_o({})'                    , 0,    0,   2)
+                     , (IoPin.EAST |IoPin.A_END  , 'ldst_port0_addr_i_95'               , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'ldst_port0_addr_i_{}'               , 0, l(20), 64)
+                     , (IoPin.NORTH|IoPin.A_END  , 'o({})'                              , 0,     0, 64)
+                     ]
+            )
+        blockLdst0.state.cfg.etesian.uniformDensity      = True
+        blockLdst0.state.cfg.etesian.spaceMargin         = 0.20
+        blockLdst0.state.cfg.katana.searchHalo           = 1
+        blockLdst0.state.cfg.katana.hTracksReservedLocal = 10
+        blockLdst0.state.cfg.katana.vTracksReservedLocal = 10
+        blockLdst0.state.fixedHeight = l(5000)
+        blockLdst0.state.useSpares   = False
+       #rvalue = blockLdst0.build()
+
+        logical0 = af.getCell( 'logical0', CRL.Catalog.State.Views )
+        blockLogical0 = Block.create \
+            ( logical0
+            , ioPins=[ (IoPin.NORTH              , 'clk'                                 , l(805.0) )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_issue_i'                          , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_imm_data_imm_ok' , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_invert_a'        , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_invert_out'      , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_is_32bit'        , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_is_signed'       , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_oe_oe'           , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_oe_oe_ok'        , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_output_carry'    , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_rc_rc'           , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_rc_rc_ok'        , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_write_cr0'       , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_zero_a'          , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'rst'                                 , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_input_carry({})' , 0, l(20),  2)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rd_go_i({})'                      , 0, l(20),  2)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rdmaskn_i({})'                    , 0, l(20),  2)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_wr_go_i({})'                      , 0, l(20),  3)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_data_len({})'    , 0, l(20),  4)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_insn_type({})'   , 0, l(20),  7)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_fn_unit({})'     , 0, l(20), 11)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_insn({})'        , 0, l(20), 32)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_imm_data_imm({})', 0, l(20), 64)
+                     , (IoPin.SOUTH|IoPin.A_BEGIN, 'src1_i({})'                          , 0, l(10), 64)
+                     , (IoPin.SOUTH|IoPin.A_BEGIN, 'src2_i({})'                          , 0,  l(5), 64)
+                     , (IoPin.EAST |IoPin.A_END  , 'cu_busy_o'                           , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'cr_a_ok'                             , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'o_ok'                                , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'xer_ca_ok'                           , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'cu_rd_rel_o({})'                     , 0,     0,  2)
+                     , (IoPin.EAST |IoPin.A_END  , 'cu_wr_rel_o({})'                     , 0,     0,  3)
+                     , (IoPin.NORTH|IoPin.A_END  , 'dest3_o({})'                         , 0,     0,  2)
+                     , (IoPin.NORTH|IoPin.A_END  , 'dest2_o({})'                         , 0,     0,  4)
+                     , (IoPin.NORTH|IoPin.A_END  , 'dest1_o({})'                         , 0,     0, 64)
+                     ]
+            )
+        blockLogical0.state.cfg.etesian.uniformDensity = True
+        blockLogical0.state.cfg.etesian.spaceMargin    = 0.07
+        blockLogical0.state.cfg.katana.searchHalo      = 1
+        blockLogical0.state.fixedHeight = l(5000)
+        blockLogical0.state.useSpares   = False
+       #rvalue = blockLogical0.build()
+
+        shiftrot0 = af.getCell( 'shiftrot0', CRL.Catalog.State.Views )
+        blockShiftrot0 = Block.create \
+            ( shiftrot0
+            , ioPins=[ (IoPin.NORTH              , 'clk'                                   , l(805.0) )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_issue_i'                               , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_imm_data_imm_ok' , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_input_cr'        , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_is_32bit'        , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_is_signed'       , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_oe_oe'           , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_oe_oe_ok'        , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_output_carry'    , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_output_cr'       , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_rc_rc'           , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_rc_rc_ok'        , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'rst'                                   , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_input_carry({})' , 0, l(20),  2)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'src4_i({})'                            , 0, l(10),  2)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rd_go_i({})'                             , 0, l(20),  4)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rdmaskn_i({})'                           , 0, l(20),  4)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_wr_go_i({})'                             , 0, l(20),  3)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_insn_type({})'   , 0, l(20),  7)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_fn_unit({})'     , 0, l(20), 11)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_insn({})'        , 0, l(20), 32)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_imm_data_imm({})', 0, l(20), 64)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'src3_i({})'                            , 0, l(10), 64)
+                     , (IoPin.SOUTH|IoPin.A_BEGIN, 'src1_i({})'                            , 0, l(10), 64)
+                     , (IoPin.SOUTH|IoPin.A_BEGIN, 'src2_i({})'                            , 0,  l(5), 64)
+                     , (IoPin.EAST |IoPin.A_END  , 'cu_busy_o'                                , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'cr_a_ok'                               , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'o_ok'                                  , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'xer_ca_ok'                             , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'cu_rd_rel_o({})'                            , 0,     0,  4)
+                     , (IoPin.EAST |IoPin.A_END  , 'cu_wr_rel_o({})'                            , 0,     0,  3)
+                     , (IoPin.NORTH|IoPin.A_END  , 'dest3_o({})'                           , 0,     0,  2)
+                     , (IoPin.NORTH|IoPin.A_END  , 'dest2_o({})'                           , 0,     0,  4)
+                     , (IoPin.NORTH|IoPin.A_END  , 'dest1_o({})'                           , 0,     0, 64)
+                     ]
+            )
+        blockShiftrot0.state.cfg.etesian.uniformDensity = True
+        blockShiftrot0.state.cfg.etesian.spaceMargin    = 0.7
+        blockShiftrot0.state.cfg.katana.searchHalo      = 1
+        blockShiftrot0.state.fixedHeight = l(5000)
+        blockShiftrot0.state.useSpares   = False
+       #rvalue = blockShiftrot0.build()
+
+        spr0 = af.getCell( 'spr0', CRL.Catalog.State.Views )
+        blockSpr0 = Block.create \
+            ( spr0
+            , ioPins=[ (IoPin.NORTH              , 'clk'                          , l(805.0) )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_issue_i'                   , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_spr0_is_32bit'     , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'rst'                          , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'src4_i'                       , 0, l(10),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'src5_i({})'                   , 0, l(10),  2)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'src6_i({})'                   , 0, l(10),  2)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rd_go_i({})'               , 0, l(20),  6)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rdmaskn_i({})'             , 0, l(20),  6)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_wr_go_i({})'               , 0, l(20),  6)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_spr0_insn_type({})', 0, l(20),  7)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_spr0_fn_unit({})'  , 0, l(20), 11)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_spr0_insn({})'     , 0, l(20), 32)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'src3_i({})'                   , 0, l(10), 64)
+                     , (IoPin.SOUTH|IoPin.A_BEGIN, 'src1_i({})'                   , 0, l(10), 64)
+                     , (IoPin.SOUTH|IoPin.A_BEGIN, 'src2_i({})'                   , 0,  l(5), 64)
+                     , (IoPin.EAST |IoPin.A_END  , 'cu_busy_o'                    , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'dest4_o'                      , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'fast1_ok'                     , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'o_ok'                         , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'spr1_ok'                      , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'xer_ca_ok'                    , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'xer_ov_ok'                    , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'xer_so_ok'                    , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'cu_rd_rel_o({})'              , 0,     0,  6)
+                     , (IoPin.EAST |IoPin.A_END  , 'cu_wr_rel_o({})'              , 0,     0,  6)
+                     , (IoPin.NORTH|IoPin.A_END  , 'dest5_o({})'                  , 0,     0,  2)
+                     , (IoPin.NORTH|IoPin.A_END  , 'dest6_o({})'                  , 0,     0,  2)
+                     , (IoPin.EAST |IoPin.A_END  , 'dest3_o({})'                  , 0, l(20), 64)
+                     , (IoPin.EAST |IoPin.A_END  , 'dest2_o({})'                  , 0, l(20), 64)
+                     , (IoPin.EAST |IoPin.A_END  , 'dest1_o({})'                  , 0, l(20), 64)
+                     ]
+            )
+        blockSpr0.state.cfg.etesian.uniformDensity = True
+        blockSpr0.state.cfg.etesian.spaceMargin    = 0.5
+        blockSpr0.state.cfg.katana.searchHalo      = 1
+        blockSpr0.state.fixedHeight = l(5000)
+        blockSpr0.state.useSpares   = False
+       #rvalue = blockSpr0.build()
+
+        trap0 = af.getCell( 'trap0', CRL.Catalog.State.Views )
+        blockTrap0 = Block.create \
+            ( trap0
+            , ioPins=[ (IoPin.NORTH              , 'clk'                           , l(805.0) )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_issue_i'                    , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_trap0_is_32bit'     , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'rst'                           , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rd_go_i({})'                , 0, l(20),  4)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rdmaskn_i({})'              , 0, l(20),  4)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cu_wr_go_i({})'                , 0, l(20),  5)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_trap0_traptype({})' , 0, l(20),  5)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_trap0_insn_type({})', 0, l(20),  7)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_trap0_fn_unit({})'  , 0, l(20), 11)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_trap0_trapaddr({})' , 0, l(20), 13)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_trap0_insn({})'     , 0, l(20), 32)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_trap0_cia({})'      , 0, l(20), 64)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_trap0_msr({})'      , 0, l(20), 64)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'src3_i({})'                    , 0, l(10), 64)
+                     , (IoPin.SOUTH|IoPin.A_BEGIN, 'src4_i({})'                    , 0, l(10), 64)
+                     , (IoPin.SOUTH|IoPin.A_BEGIN, 'src1_i({})'                    , 0, l(10), 64)
+                     , (IoPin.SOUTH|IoPin.A_BEGIN, 'src2_i({})'                    , 0,  l(5), 64)
+                     , (IoPin.EAST |IoPin.A_END  , 'cu_busy_o'                     , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'fast1_ok'                      , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'fast2_ok'                      , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'msr_ok'                        , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'nia_ok'                        , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'o_ok'                          , 0, l(20),  1)
+                     , (IoPin.EAST |IoPin.A_END  , 'cu_rd_rel_o({})'               , 0,     0,  4)
+                     , (IoPin.EAST |IoPin.A_END  , 'cu_wr_rel_o({})'               , 0,     0,  5)
+                     , (IoPin.NORTH|IoPin.A_END  , 'dest5_o({})'                   , 0, l(10), 64)
+                     , (IoPin.NORTH|IoPin.A_END  , 'dest4_o({})'                   , 0, l(10), 64)
+                     , (IoPin.EAST |IoPin.A_END  , 'dest3_o({})'                   , 0, l(10), 64)
+                     , (IoPin.EAST |IoPin.A_END  , 'dest2_o({})'                   , 0, l(10), 64)
+                     , (IoPin.EAST |IoPin.A_END  , 'dest1_o({})'                   , 0, l(10), 64)
+                     ]
+            )
+        blockTrap0.state.cfg.etesian.uniformDensity = True
+        blockTrap0.state.cfg.etesian.spaceMargin    = 0.5
+        blockTrap0.state.cfg.katana.searchHalo      = 1
+        blockTrap0.state.fixedHeight = l(5000)
+        blockTrap0.state.useSpares   = False
+       #rvalue = blockTrap0.build()
+
+        fast = af.getCell( 'fast', CRL.Catalog.State.Views )
+        blockFast = Block.create \
+            ( fast
+            , ioPins=[ (IoPin.NORTH              , 'clk'             , l(805.0) )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'rst'             , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'cia_ren({})'     , 0, l(20),  8)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'fast_nia_wen({})', 0, l(20),  8)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'msr_ren({})'     , 0, l(20),  8)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'src1_ren({})'    , 0, l(20),  8)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'src2_ren({})'    , 0, l(20),  8)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'wen({})'         , 0, l(20),  8)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'wen_1({})'       , 0, l(20),  8)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'wen_3({})'       , 0, l(20),  8)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'wen_6({})'       , 0, l(20),  8)
+                     , (IoPin.SOUTH|IoPin.A_BEGIN, 'data_i({})'      , 0, l(20), 64)
+                     , (IoPin.SOUTH|IoPin.A_BEGIN, 'data_i_2({})'    , 0, l(20), 64)
+                     , (IoPin.SOUTH|IoPin.A_BEGIN, 'data_i_4({})'    , 0, l(10), 64)
+                     , (IoPin.SOUTH|IoPin.A_BEGIN, 'data_i_5({})'    , 0, l(10), 64)
+                     , (IoPin.SOUTH|IoPin.A_BEGIN, 'data_i_7({})'    , 0, l(10), 64)
+                     , (IoPin.NORTH|IoPin.A_END  , 'cia_data_o({})'  , 0, l(20), 64)
+                     , (IoPin.NORTH|IoPin.A_END  , 'msr_data_o({})'  , 0, l(10), 64)
+                     , (IoPin.NORTH|IoPin.A_END  , 'src1_data_o({})' , 0, l(10), 64)
+                     , (IoPin.NORTH|IoPin.A_END  , 'src2_data_o({})' , 0, l(10), 64)
+                     ]
+            )
+        blockFast.state.cfg.etesian.uniformDensity = True
+        blockFast.state.cfg.etesian.aspectRatio    = 1.0
+        blockFast.state.cfg.etesian.spaceMargin    = 0.6
+        blockFast.state.cfg.katana.searchHalo      = 1
+        blockFast.state.useSpares   = False
+       #rvalue = blockFast.build()
+        
+        cellInt  = af.getCell( 'int', CRL.Catalog.State.Views )
+        blockInt = Block.create \
+            ( cellInt
+            , ioPins=[ (IoPin.NORTH              , 'clk'             , l(805.0) )
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'rst'             , 0, l(20),  1)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'wen({})'         , 0, l(20), 32)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'wen_1({})'       , 0, l(20), 32)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'src1_ren({})'    , 0, l(20), 32)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'src2_ren({})'    , 0, l(20), 32)
+                     , (IoPin.WEST |IoPin.A_BEGIN, 'src3_ren({})'    , 0, l(20), 32)
+                     , (IoPin.SOUTH|IoPin.A_BEGIN, 'data_i({})'      , 0, l(20), 64)
+                     , (IoPin.SOUTH|IoPin.A_BEGIN, 'data_i_2({})'    , 0, l(20), 64)
+                     , (IoPin.NORTH|IoPin.A_END  , 'src1_data_o({})' , 0, l(10), 64)
+                     , (IoPin.NORTH|IoPin.A_END  , 'src2_data_o({})' , 0, l(10), 64)
+                     , (IoPin.NORTH|IoPin.A_END  , 'src3_data_o({})' , 0, l(10), 64)
+                     ]
+            )
+        blockInt.state.cfg.etesian.uniformDensity = True
+        blockInt.state.cfg.etesian.aspectRatio    = 1.0
+        blockInt.state.cfg.etesian.spaceMargin    = 0.07
+        blockInt.state.cfg.katana.searchHalo      = 1
+        blockInt.state.useSpares   = False
+       #rvalue = blockInt.build()
+
+        issuer      = af.getCell( 'test_issuer' , CRL.Catalog.State.Logical )
+        blockIssuer = Block.create \
+            ( issuer
+            , ioPins=[]
+            )
+        
+        # Cell width:
+        #
+        # ================  =================
+        # alu0              1200
+        # branch0           1750
+        # cr0                950
+        # ldst0             1100
+        # logical0          1800
+        # mul0              9600
+        # shiftrot0         2350
+        # spr0              1550
+        # trap0             3250
+        # fast              ?
+        # int               ?
+        # pdecode           ?
+        # ================  =================
+        
+        blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2031_fus.subckt_0_alu0'
+                                    , Transformation( l(1000), l(4000), Transformation.Orientation.ID ))
+        blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2031_fus.subckt_1_branch0'
+                                    , Transformation( l(2700), l(4000), Transformation.Orientation.ID ))
+        blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2031_fus.subckt_2_cr0'
+                                    , Transformation( l(4950), l(4000), Transformation.Orientation.ID ))
+        blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2031_fus.subckt_3_ldst0'
+                                    , Transformation( l(6400), l(4000), Transformation.Orientation.ID ))
+        blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2031_fus.subckt_4_logical0'
+                                    , Transformation( l(8000), l(4000), Transformation.Orientation.ID ))
+        blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2031_fus.subckt_5_mul0'
+                                    , Transformation( l(10300), l(4000), Transformation.Orientation.ID ))
+        blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2031_fus.subckt_6_shiftrot0'
+                                    , Transformation( l(20400), l(4000), Transformation.Orientation.ID ))
+        blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2031_fus.subckt_7_spr0'
+                                    , Transformation( l(23250), l(4000), Transformation.Orientation.ID ))
+        blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2031_fus.subckt_8_trap0'
+                                    , Transformation( l(25300), l(4000), Transformation.Orientation.ID ))
+        blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2030_fast'
+                                    , Transformation( l(1000), l(4000), Transformation.Orientation.ID ))
+        blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2032_int'
+                                    , Transformation( l(1000), l(4000), Transformation.Orientation.ID ))
+        blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2034_pdecode2'
+                                    , Transformation( l(1000), l(4000), Transformation.Orientation.ID ))
+        blockIssuer.state.cfg.etesian.uniformDensity = True
+        blockIssuer.state.cfg.etesian.aspectRatio    = 1.0
+        blockIssuer.state.cfg.etesian.spaceMargin    = 0.07
+        blockIssuer.state.cfg.katana.searchHalo      = 10000
+        blockIssuer.state.fixedHeight = l(15000)
+        blockIssuer.state.fixedWidth  = l(29550)
+        blockIssuer.state.useSpares   = False
+        blockIssuer.state.editor      = editor
+        rvalue = blockIssuer.build()
+    except Exception, e:
+        helpers.io.catch( e )
+        rvalue = False
+
+    sys.stdout.flush()
+    sys.stderr.flush()
+        
+    return rvalue