sim_ticks 727072000 # Number of ticks simulated
final_tick 727072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1240024 # Simulator instruction rate (inst/s)
-host_op_rate 1239964 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1802997891 # Simulator tick rate (ticks/s)
-host_mem_usage 256648 # Number of bytes of host memory used
-host_seconds 0.40 # Real time elapsed on the host
+host_inst_rate 1476552 # Simulator instruction rate (inst/s)
+host_op_rate 1476467 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2146892777 # Simulator tick rate (ticks/s)
+host_mem_usage 226332 # Number of bytes of host memory used
+host_seconds 0.34 # Real time elapsed on the host
sim_insts 500001 # Number of instructions simulated
sim_ops 500001 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25792 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 35473791 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 39963030 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 75436821 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 75436821 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 718 # Transaction distribution
+system.membus.trans_dist::ReadResp 718 # Transaction distribution
+system.membus.trans_dist::ReadExReq 139 # Transaction distribution
+system.membus.trans_dist::ReadExResp 139 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 1714 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 1714 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 54848 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 54848 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 54848 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 857000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer1.occupancy 7713000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 287.259400 # Cycle average of tags in use
-system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 287.259400 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.070132 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 180321 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 180321 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 180321 # number of overall hits
-system.cpu.dcache.overall_hits::total 180321 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 315 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 139 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 139 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 454 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 454 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 454 # number of overall misses
-system.cpu.dcache.overall_misses::total 454 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 17325000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 17325000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 7645000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 24970000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 24970000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 24970000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 24970000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 124435 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 56340 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 180775 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 180775 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002531 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.002531 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002467 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.002511 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.002511 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.002511 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.002511 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 139 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 454 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16695000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 16695000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7367000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 7367000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24062000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 24062000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24062000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 24062000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002531 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002531 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.002511 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.002511 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 481.542013 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 287.259400 # Cycle average of tags in use
+system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 287.259400 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.070132 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 180321 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 180321 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 180321 # number of overall hits
+system.cpu.dcache.overall_hits::total 180321 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 315 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 139 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 139 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 454 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 454 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 454 # number of overall misses
+system.cpu.dcache.overall_misses::total 454 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 17325000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 17325000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 7645000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 24970000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 24970000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 24970000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 24970000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 124435 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 56340 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 180775 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 180775 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002531 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.002531 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002467 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.002511 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.002511 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.002511 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.002511 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 139 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 454 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16695000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 16695000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7367000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 7367000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24062000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 24062000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24062000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 24062000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002531 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002531 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002467 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.002511 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.002511 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 75436821 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 718 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 718 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 139 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 139 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 806 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 908 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 1714 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 25792 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 29056 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 54848 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 54848 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 428500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 604500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 681000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
sim_seconds 0.000729 # Number of seconds simulated
-sim_ticks 729071000 # Number of ticks simulated
-final_tick 729071000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 729024000 # Number of ticks simulated
+final_tick 729024000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1157540 # Simulator instruction rate (inst/s)
-host_op_rate 1157526 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 421963637 # Simulator tick rate (ticks/s)
-host_mem_usage 274580 # Number of bytes of host memory used
-host_seconds 1.73 # Real time elapsed on the host
+host_inst_rate 1420709 # Simulator instruction rate (inst/s)
+host_op_rate 1420692 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 517863701 # Simulator tick rate (ticks/s)
+host_mem_usage 236964 # Number of bytes of host memory used
+host_seconds 1.41 # Real time elapsed on the host
sim_insts 1999959 # Number of instructions simulated
sim_ops 1999959 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory
system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory
system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 35376527 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 39853457 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 35376527 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 39853457 # Total read bandwidth from this memory (bytes/s)
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system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu0.committedInsts 500001 # Number of instructions committed
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system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu0.icache.avg_refs 1078.956803 # Average number of references to valid blocks.
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system.cpu0.icache.ReadReq_accesses::cpu0.inst 500020 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
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system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for demand accesses
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system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 55176.258993 # average WriteReq miss latency
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff