mention that the 4x4 crossbar is a major data bottleneck

diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn
index b71d52fa9fbd952bd5b203ef4921eda9d58f94c3..b59ebad67f82ac09d0d4e204941ba1f87da4c275 100644 (file)
--- a/3d_gpu/architecture/regfile.mdwn
+++ b/3d_gpu/architecture/regfile.mdwn
@@ -45,6 +45,10 @@ busy.  Below is the connectivity diagram:
 
 Notes:
 
+* There is only **one** 4x4 crossbar (or, one for reads, one for writes?)
+  and thus only **one** inter-Quadrant 32-bit-wide data path (total
+  bandwidth 4x32 bits).  These to be shared by **five** groups of
+  operand ports at each of the Quadrant Global Cyclic Buffers.
 * The **only** way for register results and operands to cross over between
   quadrants of the regfile is that 4x4 crossbar.  Data transfer bandwidth
   being limited, the placement of an operation adversely affects its