add links to bugreport and to memory/cache wiki page

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index 27e2af668cf8d2b61d5827d3fb9bf26a0e9db2b0..22168267b64d557ff3cc61c597505188bc2985db 100644 (file)
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -8,6 +8,11 @@ test infrastructure, and, just as with minerva's memory arrangement,
 a dynamic runtime config *selects* alternative memory arrangements
 rather than *replaces and discards* this code.
 
+Links:
+
+* https://bugs.libre-soc.org/show_bug.cgi?id=216
+* https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
+
 """
 
 from nmigen.compat.sim import run_simulation