Merge branch 'mmu'

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

diff --cc Makefile
Simple merge

diff --cc core.vhdl
Simple merge

diff --cc fetch1.vhdl
index 301f3178521837865feaa9280762ae3589d7cbe5,936e830c0593deca0c3d88726aa0895786f401fd..cb1d1df6d1948e0357028c13f977e7f9e88a599b
--- 1/fetch1.vhdl
--- 2/fetch1.vhdl
+++ b/fetch1.vhdl
@@@ -62,11 -62,9 +64,13 @@@ begi
        v_int := r_int;
  
        if rst = '1' then
 -          v.nia :=  RESET_ADDRESS;
 +          if alt_reset_in = '1' then
 +              v.nia :=  ALT_RESET_ADDRESS;
 +          else
 +              v.nia :=  RESET_ADDRESS;
 +          end if;
+             v.virt_mode := '0';
+             v.priv_mode := '1';
            v_int.stop_state := RUNNING;
        elsif e_in.redirect = '1' then
            v.nia := e_in.redirect_nia;

diff --cc fetch2.vhdl
Simple merge

diff --cc icache.vhdl
index 3eaf548b85385cfcc3f362aca582d4d6d97ea4dc,86c27462a43ca4b07820c85eba588a3889deb705..35d64a8673c5772edff808eb6f241c30d6b49244
--- 1/icache.vhdl
--- 2/icache.vhdl
+++ b/icache.vhdl
@@@ -385,8 -485,13 +485,13 @@@ begi
        end loop;
  
        -- Generate the "hit" and "miss" signals for the synchronous blocks
-       req_is_hit  <= i_in.req and is_hit and not flush_in and not rst;
-       req_is_miss <= i_in.req and not is_hit and not flush_in;
 -        if i_in.req = '1' and access_ok = '1' and flush_in = '0' then
++        if i_in.req = '1' and access_ok = '1' and flush_in = '0' and rst = '0' then
+             req_is_hit  <= is_hit;
+             req_is_miss <= not is_hit;
+         else
+             req_is_hit  <= '0';
+             req_is_miss <= '0';
+         end if;
        req_hit_way <= hit_way;
  
        -- The way to replace on a miss

diff --cc microwatt.core
Simple merge