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diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 85e61764945629751dfc5685767c03bd1b69dd68..195b3b4ab0db14fff639e23a4391caf2196c06e4 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -263,8 +263,8 @@ count and reducing assembler complexity are:
   option exists to include or exclude the failing element.
 * Predicate-result: a strategic mode that effectively turns all and any
   operations into a type of `cmp`. An `Rc=1 BO test` is performed and if
-  failing the result is **not** written to the regfile. The `Rc=1`
-  Vector of co-results **is** always written (subject to predication).
+  failing that element result is **not** written to the regfile. The `Rc=1`
+  Vector of co-results **is** always written (subject to usual predication).
   Termed "predicate-result" because the combination of producing then
   testing a result is as if the test was in a follow-up predicated
   copy/mv operation, it reduces regfile pressure and instruction count.
@@ -331,6 +331,12 @@ Also `SVLR` is introduced, which is a parallel twin of `LR`, and saving
 and restoring of LR and SVLR may be deferred until the final decision
 as to whether to branch.  In this way `sv.bclrl` does not corrupt `LR`.
 
+Vectorised Branch-Conditional due to its side-effects (e.g. reducing CTR
+or truncating VL) has practical uses even if the Branch is deliberately
+set to the next instruction (CIA+8). For example it may be used to reduce
+CTR by the number of bits set in a GPR, if that GPR is given as the predicate
+mask `sv.bc/pm=r3`.
+
 # SVP64Single 24-bits
 
 The `SVP64-Single` 24-bit encoding focusses primarily on ensuring that