add virtual reg illustration

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index 6ca79263cb273c90be54fb8a4c13491f18f07a2d..996ec164bc8cbfd94033f700b6b46c3b70058aab 100644 (file)
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -1037,6 +1037,7 @@ translates effectively to:
 Register File 
 
 | Reg Num | Bits |
+| ------- | ---- |
 | r0 | (32..0) |
 | r1 | (32..0) |
 | r2 | (32..0) |
@@ -1049,11 +1050,13 @@ Register File
 Vectorised CSR
 
 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+| - | - | - | - | - | - | - | - |  
 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
 
 Vector Length CSR
 
 | Reg Num | (3..0) |
+| ------- | ---- |
 | r0 | 2 |
 | r1 | 0 |
 | r2 | 1 |
@@ -1066,6 +1069,7 @@ Vector Length CSR
 Virtual Register Reordering:
 
 | Reg Num | Bits (0) | Bits (1) | Bits (2) |
+| ------- | -------- | -------- | -------- |
 | r0 | (32..0) | (32..0) |
 | r2 | (32..0) |
 | r3 | (32..0) |