---------- Begin Simulation Statistics ----------
sim_seconds 1.883224 # Number of seconds simulated
-sim_ticks 1883223940000 # Number of ticks simulated
-final_tick 1883223940000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 1883224346500 # Number of ticks simulated
+final_tick 1883224346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 180615 # Simulator instruction rate (inst/s)
-host_op_rate 180615 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6060637883 # Simulator tick rate (ticks/s)
-host_mem_usage 316396 # Number of bytes of host memory used
-host_seconds 310.73 # Real time elapsed on the host
-sim_insts 56122642 # Number of instructions simulated
-sim_ops 56122642 # Number of ops (including micro ops) simulated
+host_inst_rate 283997 # Simulator instruction rate (inst/s)
+host_op_rate 283997 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 9530044697 # Simulator tick rate (ticks/s)
+host_mem_usage 369276 # Number of bytes of host memory used
+host_seconds 197.61 # Real time elapsed on the host
+sim_insts 56120453 # Number of instructions simulated
+sim_ops 56120453 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 25930944 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 25931648 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 25931904 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1052544 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1052544 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4902720 # Number of bytes written to this memory
+system.physmem.bytes_read::total 25932608 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1052800 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1052800 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4903936 # Number of bytes written to this memory
system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7562048 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 405171 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 7563264 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 405182 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 405186 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 76605 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 405197 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 76624 # Number of write requests responded to by this memory
system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 118157 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 13769443 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 118176 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 13769813 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 510 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 13769952 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 558905 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 558905 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2603365 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::tsunami.ide 1412115 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4015480 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2603365 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 13769443 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total 13770323 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 559041 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 559041 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2604011 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::tsunami.ide 1412114 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4016125 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2604011 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 13769813 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1412624 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 17785432 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 405186 # Number of read requests accepted
-system.physmem.writeReqs 118157 # Number of write requests accepted
-system.physmem.readBursts 405186 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 118157 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 25919424 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 12480 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7560064 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 25931904 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 7562048 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 195 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total 17786448 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 405197 # Number of read requests accepted
+system.physmem.writeReqs 118176 # Number of write requests accepted
+system.physmem.readBursts 405197 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 118176 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 25920704 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 11904 # Total number of bytes read from write queue
+system.physmem.bytesWritten 7562112 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 25932608 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 7563264 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 186 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 157 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 25480 # Per bank write bursts
-system.physmem.perBankRdBursts::1 25741 # Per bank write bursts
-system.physmem.perBankRdBursts::2 25855 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 154 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 25484 # Per bank write bursts
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system.physmem.perBankRdBursts::3 25788 # Per bank write bursts
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system.physmem.perBankRdBursts::7 24586 # Per bank write bursts
system.physmem.perBankRdBursts::8 25127 # Per bank write bursts
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system.physmem.perBankRdBursts::11 24857 # Per bank write bursts
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system.physmem.perBankRdBursts::15 25740 # Per bank write bursts
system.physmem.perBankWrBursts::0 7812 # Per bank write bursts
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system.physmem.perBankWrBursts::2 8067 # Per bank write bursts
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-system.physmem.perBankWrBursts::4 7318 # Per bank write bursts
-system.physmem.perBankWrBursts::5 6954 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6788 # Per bank write bursts
-system.physmem.perBankWrBursts::7 6406 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7235 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6889 # Per bank write bursts
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system.physmem.perBankWrBursts::12 7045 # Per bank write bursts
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system.physmem.perBankWrBursts::14 7989 # Per bank write bursts
-system.physmem.perBankWrBursts::15 7937 # Per bank write bursts
+system.physmem.perBankWrBursts::15 7955 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 5 # Number of times write queue was full causing retry
-system.physmem.totGap 1883215178500 # Total gap between requests
+system.physmem.numWrRetry 7 # Number of times write queue was full causing retry
+system.physmem.totGap 1883215617500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 405186 # Read request sizes (log2)
+system.physmem.readPktSize::6 405197 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 118157 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 402670 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 2243 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 66 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 118176 # Write request sizes (log2)
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system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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-system.physmem.bytesPerActivate::samples 62955 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 531.800302 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 324.503879 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 415.177975 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 14434 22.93% 22.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 10626 16.88% 39.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 4984 7.92% 47.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3035 4.82% 52.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2479 3.94% 56.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2063 3.28% 59.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1365 2.17% 61.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1615 2.57% 64.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 22354 35.51% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 62955 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5310 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 76.265725 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 2898.384419 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191 5307 99.94% 99.94% # Reads before turning the bus around for writes
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+system.physmem.bytesPerActivate::samples 63140 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 530.294837 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 322.585016 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 415.640457 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 14650 23.20% 23.20% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::256-383 5075 8.04% 48.01% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::512-639 2370 3.75% 56.52% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1024-1151 22377 35.44% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 63140 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 5316 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 76.186983 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 2896.748549 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191 5313 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5310 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5310 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 22.245951 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.963647 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 20.434666 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 4660 87.76% 87.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 16 0.30% 88.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 15 0.28% 88.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 227 4.27% 92.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 38 0.72% 93.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 5 0.09% 93.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 8 0.15% 93.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 6 0.11% 93.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 26 0.49% 94.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 4 0.08% 94.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 5 0.09% 94.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 14 0.26% 94.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 2 0.04% 94.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 5 0.09% 94.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 26 0.49% 95.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 9 0.17% 95.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 5 0.09% 95.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 6 0.11% 95.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 182 3.43% 99.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 6 0.11% 99.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 1 0.02% 99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 2 0.04% 99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 3 0.06% 99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 2 0.04% 99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 6 0.11% 99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 5 0.09% 99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 4 0.08% 99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 2 0.04% 99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 7 0.13% 99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155 1 0.02% 99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 1 0.02% 99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 5 0.09% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 2 0.04% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183 1 0.02% 99.94% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 5316 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 5316 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 22.226862 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.933757 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 20.590348 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 4662 87.70% 87.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 15 0.28% 87.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 21 0.40% 88.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 225 4.23% 92.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 46 0.87% 93.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 10 0.19% 93.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 7 0.13% 93.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 7 0.13% 93.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 19 0.36% 94.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 3 0.06% 94.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 2 0.04% 94.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 2 0.04% 94.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 12 0.23% 94.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 1 0.02% 94.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 6 0.11% 94.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 29 0.55% 95.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 14 0.26% 95.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 2 0.04% 95.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 12 0.23% 95.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 164 3.09% 98.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 5 0.09% 99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 1 0.02% 99.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 2 0.04% 99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 3 0.06% 99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 1 0.02% 99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 4 0.08% 99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 3 0.06% 99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 8 0.15% 99.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 6 0.11% 99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 12 0.23% 99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151 1 0.02% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155 3 0.06% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167 1 0.02% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171 1 0.02% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 3 0.06% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227 3 0.06% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5310 # Writes before turning the bus around for reads
-system.physmem.totQLat 2131293750 # Total ticks spent queuing
-system.physmem.totMemAccLat 9724875000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2024955000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 5262.57 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total 5316 # Writes before turning the bus around for reads
+system.physmem.totQLat 2156220500 # Total ticks spent queuing
+system.physmem.totMemAccLat 9750176750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2025055000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 5323.86 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 24012.57 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 24073.86 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 13.76 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW 4.02 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 4.02 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing
-system.physmem.readRowHits 364467 # Number of row buffer hits during reads
-system.physmem.writeRowHits 95695 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 89.99 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 80.99 # Row buffer hit rate for writes
-system.physmem.avgGap 3598433.87 # Average gap between requests
-system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 1774121817500 # Time in different power states
+system.physmem.avgWrQLen 23.67 # Average write queue length when enqueuing
+system.physmem.readRowHits 364400 # Number of row buffer hits during reads
+system.physmem.writeRowHits 95629 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 89.97 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 80.92 # Row buffer hit rate for writes
+system.physmem.avgGap 3598228.45 # Average gap between requests
+system.physmem.pageHitRate 87.93 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 1774012993500 # Time in different power states
system.physmem.memoryStateTime::REF 62884900000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 46214912500 # Time in different power states
+system.physmem.memoryStateTime::ACT 46323736500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 17814330 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 295751 # Transaction distribution
-system.membus.trans_dist::ReadResp 295735 # Transaction distribution
+system.membus.trans_dist::ReadReq 295760 # Transaction distribution
+system.membus.trans_dist::ReadResp 295744 # Transaction distribution
system.membus.trans_dist::WriteReq 9618 # Transaction distribution
system.membus.trans_dist::WriteResp 9618 # Transaction distribution
-system.membus.trans_dist::Writeback 76605 # Transaction distribution
+system.membus.trans_dist::Writeback 76624 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 157 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 157 # Transaction distribution
-system.membus.trans_dist::ReadExReq 116539 # Transaction distribution
-system.membus.trans_dist::ReadExResp 116539 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 154 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 154 # Transaction distribution
+system.membus.trans_dist::ReadExReq 116541 # Transaction distribution
+system.membus.trans_dist::ReadExResp 116541 # Transaction distribution
system.membus.trans_dist::BadAddressError 16 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33096 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887261 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887296 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920389 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920424 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1003681 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44308 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30833664 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30877972 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 33538260 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 33538260 # Total data (bytes)
-system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 29840000 # Layer occupancy (ticks)
+system.membus.pkt_count::total 1003716 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44308 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30835584 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30879892 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 33540180 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 158 # Total snoops (count)
+system.membus.snoop_fanout::samples 523708 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 523708 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 523708 # Request fanout histogram
+system.membus.reqLayer0.occupancy 30927500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 1547069500 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 1547261750 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 19500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 20000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3825068843 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 3825161596 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 43112000 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 43114249 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 41685 # number of replacements
-system.iocache.tags.tagsinuse 1.288165 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 1.288180 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 1728026235000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide 1.288165 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide 0.080510 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.080510 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 1728025257000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide 1.288180 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide 0.080511 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.080511 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 375533 # Number of tag accesses
-system.iocache.tags.data_accesses 375533 # Number of data accesses
+system.iocache.tags.tag_accesses 375525 # Number of tag accesses
+system.iocache.tags.data_accesses 375525 # Number of data accesses
system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::tsunami.ide 1 # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total 1 # number of WriteInvalidateReq misses
system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
system.iocache.demand_misses::total 173 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
system.iocache.overall_misses::total 173 # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide 21132383 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 21132383 # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 21132383 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 21132383 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 21132383 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 21132383 # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41553 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total 41553 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.000024 # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total 0.000024 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122152.502890 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 122152.502890 # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 122152.502890 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 122152.502890 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 122152.502890 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 122152.502890 # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12135383 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 12135383 # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2514597305 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2514597305 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 12135383 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 12135383 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 12135383 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 12135383 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512658057 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512658057 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999976 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999976 # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70146.722543 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60516.877768 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60516.877768 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 70146.722543 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 70146.722543 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60470.207379 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60470.207379 # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 14964215 # Number of BP lookups
-system.cpu.branchPred.condPredicted 12981470 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 376025 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 10003487 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 5188980 # Number of BTB hits
+system.cpu.branchPred.lookups 14964931 # Number of BP lookups
+system.cpu.branchPred.condPredicted 12983118 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 374694 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9691016 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 5184483 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 51.871712 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 807651 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 32040 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 53.497827 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 807557 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 32108 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 9238395 # DTB read hits
-system.cpu.dtb.read_misses 17814 # DTB read misses
+system.cpu.dtb.read_hits 9237824 # DTB read hits
+system.cpu.dtb.read_misses 17804 # DTB read misses
system.cpu.dtb.read_acv 211 # DTB read access violations
-system.cpu.dtb.read_accesses 766068 # DTB read accesses
-system.cpu.dtb.write_hits 6385066 # DTB write hits
-system.cpu.dtb.write_misses 2311 # DTB write misses
+system.cpu.dtb.read_accesses 766148 # DTB read accesses
+system.cpu.dtb.write_hits 6384867 # DTB write hits
+system.cpu.dtb.write_misses 2306 # DTB write misses
system.cpu.dtb.write_acv 159 # DTB write access violations
-system.cpu.dtb.write_accesses 298441 # DTB write accesses
-system.cpu.dtb.data_hits 15623461 # DTB hits
-system.cpu.dtb.data_misses 20125 # DTB misses
+system.cpu.dtb.write_accesses 298467 # DTB write accesses
+system.cpu.dtb.data_hits 15622691 # DTB hits
+system.cpu.dtb.data_misses 20110 # DTB misses
system.cpu.dtb.data_acv 370 # DTB access violations
-system.cpu.dtb.data_accesses 1064509 # DTB accesses
-system.cpu.itb.fetch_hits 4000795 # ITB hits
-system.cpu.itb.fetch_misses 6874 # ITB misses
-system.cpu.itb.fetch_acv 703 # ITB acv
-system.cpu.itb.fetch_accesses 4007669 # ITB accesses
+system.cpu.dtb.data_accesses 1064615 # DTB accesses
+system.cpu.itb.fetch_hits 3999749 # ITB hits
+system.cpu.itb.fetch_misses 6851 # ITB misses
+system.cpu.itb.fetch_acv 647 # ITB acv
+system.cpu.itb.fetch_accesses 4006600 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.numCycles 176776474 # number of cpu cycles simulated
+system.cpu.numCycles 174888375 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 56122642 # Number of instructions committed
-system.cpu.committedOps 56122642 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 2532635 # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends 5494 # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles 3591582755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi 3.149825 # CPI: cycles per instruction
-system.cpu.ipc 0.317478 # IPC: instructions per cycle
+system.cpu.committedInsts 56120453 # Number of instructions committed
+system.cpu.committedOps 56120453 # Number of ops (including micro ops) committed
+system.cpu.discardedOps 2530516 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends 5527 # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles 3591560318 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi 3.116304 # CPI: cycles per instruction
+system.cpu.ipc 0.320893 # IPC: instructions per cycle
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei 211451 # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0 74783 40.94% 40.94% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei 211459 # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0 74787 40.94% 40.94% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1900 1.04% 42.05% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31 105851 57.95% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total 182665 # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0 73416 49.32% 49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::31 105855 57.95% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total 182673 # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0 73420 49.32% 49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22 1900 1.28% 50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31 73416 49.32% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total 148863 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1832860357500 97.33% 97.33% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21 80169000 0.00% 97.33% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22 672803000 0.04% 97.37% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 49609630000 2.63% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1883222959500 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0 0.981720 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::31 73420 49.32% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total 148871 # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0 1832868777500 97.33% 97.33% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21 80360500 0.00% 97.33% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22 672864500 0.04% 97.37% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 49601349000 2.63% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total 1883223351500 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0 0.981721 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31 0.693579 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total 0.814951 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31 0.693590 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total 0.814959 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl 175508 91.23% 93.43% # number of callpals executed
+system.cpu.kern.callpal::swpipl 175516 91.23% 93.43% # number of callpals executed
system.cpu.kern.callpal::rdps 6803 3.54% 96.96% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::rti 5125 2.66% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.callpal::total 192390 # number of callpals executed
-system.cpu.kern.mode_switch::kernel 5869 # number of protection mode switches
+system.cpu.kern.callpal::total 192398 # number of callpals executed
+system.cpu.kern.mode_switch::kernel 5867 # number of protection mode switches
system.cpu.kern.mode_switch::user 1741 # number of protection mode switches
-system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches
+system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches
system.cpu.kern.mode_good::kernel 1910
system.cpu.kern.mode_good::user 1741
system.cpu.kern.mode_good::idle 169
-system.cpu.kern.mode_switch_good::kernel 0.325439 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel 0.325550 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::idle 0.080553 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.393571 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 36245351000 1.92% 1.92% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 4057630500 0.22% 2.14% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1842919968000 97.86% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::kernel 36222818500 1.92% 1.92% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user 4061127000 0.22% 2.14% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle 1842939396000 97.86% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4175 # number of times the context was actually changed
-system.cpu.tickCycles 85798616 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 90977858 # Total number of cycles that the object has spent stopped
+system.cpu.tickCycles 83840328 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 91048047 # Total number of cycles that the object has spent stopped
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.iobus.throughput 1436853 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
-system.iobus.trans_dist::WriteReq 51169 # Transaction distribution
+system.iobus.trans_dist::WriteReq 51170 # Transaction distribution
system.iobus.trans_dist::WriteResp 51170 # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq 1 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5092 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 116546 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20368 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 44308 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 2705916 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 2705916 # Total data (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20368 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 44308 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2705916 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 4703000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer29.occupancy 374409688 # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy 374407689 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 23478000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 42012000 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 42013751 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.icache.tags.replacements 1458007 # number of replacements
-system.cpu.icache.tags.tagsinuse 509.627041 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 18950160 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 1458518 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 12.992750 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 31562091250 # Cycle when the warmup percentage was hit.
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 126942050 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 2557486 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2557452 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 2557139 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::WriteReq 9618 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 9618 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 838282 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41557 # Transaction distribution
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-system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution
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-system.cpu.toL2Bus.trans_dist::ReadExResp 304264 # Transaction distribution
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+system.cpu.toL2Bus.trans_dist::ReadExResp 304253 # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution
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-system.cpu.toL2Bus.tot_pkt_size::total 236396692 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 236386772 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 2673536 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 2697842997 # Layer occupancy (ticks)
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system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
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system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
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-system.cpu.l2cache.ReadReq_hits::total 2261673 # number of ReadReq hits
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system.cpu.l2cache.UpgradeReq_hits::cpu.inst 4 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
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-system.cpu.l2cache.ReadExReq_hits::total 187588 # number of ReadExReq hits
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11376.108760 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26987.502110 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26987.502110 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26987.502110 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26987.502110 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 1.903124 # Number of seconds simulated
-sim_ticks 1903123778500 # Number of ticks simulated
-final_tick 1903123778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.905068 # Number of seconds simulated
+sim_ticks 1905067807000 # Number of ticks simulated
+final_tick 1905067807000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 103415 # Simulator instruction rate (inst/s)
-host_op_rate 103415 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3505224116 # Simulator tick rate (ticks/s)
-host_mem_usage 322696 # Number of bytes of host memory used
-host_seconds 542.94 # Real time elapsed on the host
-sim_insts 56148221 # Number of instructions simulated
-sim_ops 56148221 # Number of ops (including micro ops) simulated
+host_inst_rate 162284 # Simulator instruction rate (inst/s)
+host_op_rate 162284 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5403466257 # Simulator tick rate (ticks/s)
+host_mem_usage 375680 # Number of bytes of host memory used
+host_seconds 352.56 # Real time elapsed on the host
+sim_insts 57215334 # Number of instructions simulated
+sim_ops 57215334 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst 744192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24296448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 865344 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24709248 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 238144 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 1067328 # Number of bytes read from this memory
-system.physmem.bytes_read::total 26347072 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 744192 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 238144 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 982336 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 5275328 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst 118912 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 545600 # Number of bytes read from this memory
+system.physmem.bytes_read::total 26240064 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 865344 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 118912 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 984256 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 5157696 # Number of bytes written to this memory
system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7934656 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 11628 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 379632 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 7817024 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 13521 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 386082 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 3721 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 16677 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 411673 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 82427 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 1858 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 8525 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 410001 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 80589 # Number of write requests responded to by this memory
system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 123979 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 391037 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 12766615 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 122141 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 454233 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 12970272 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 125133 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 560830 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 13844119 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 391037 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 125133 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 516170 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2771931 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::tsunami.ide 1397349 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4169280 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2771931 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 391037 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 12766615 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1397853 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 125133 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 560830 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 18013399 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 411673 # Number of read requests accepted
-system.physmem.writeReqs 123979 # Number of write requests accepted
-system.physmem.readBursts 411673 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 123979 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 26335040 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 12032 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7932928 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 26347072 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 7934656 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 188 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_read::cpu1.inst 62419 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 286394 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 13773822 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 454233 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 62419 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 516651 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2707356 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::tsunami.ide 1395923 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4103279 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2707356 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 454233 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 12970272 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1396427 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 62419 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 286394 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 17877100 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 410001 # Number of read requests accepted
+system.physmem.writeReqs 122141 # Number of write requests accepted
+system.physmem.readBursts 410001 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 122141 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 26227648 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 12416 # Total number of bytes read from write queue
+system.physmem.bytesWritten 7815104 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 26240064 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 7817024 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 194 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 3444 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 25632 # Per bank write bursts
-system.physmem.perBankRdBursts::1 25720 # Per bank write bursts
-system.physmem.perBankRdBursts::2 26346 # Per bank write bursts
-system.physmem.perBankRdBursts::3 25660 # Per bank write bursts
-system.physmem.perBankRdBursts::4 25672 # Per bank write bursts
-system.physmem.perBankRdBursts::5 25150 # Per bank write bursts
-system.physmem.perBankRdBursts::6 25568 # Per bank write bursts
-system.physmem.perBankRdBursts::7 25491 # Per bank write bursts
-system.physmem.perBankRdBursts::8 25973 # Per bank write bursts
-system.physmem.perBankRdBursts::9 26167 # Per bank write bursts
-system.physmem.perBankRdBursts::10 25812 # Per bank write bursts
-system.physmem.perBankRdBursts::11 25687 # Per bank write bursts
-system.physmem.perBankRdBursts::12 26023 # Per bank write bursts
-system.physmem.perBankRdBursts::13 25844 # Per bank write bursts
-system.physmem.perBankRdBursts::14 25108 # Per bank write bursts
-system.physmem.perBankRdBursts::15 25632 # Per bank write bursts
-system.physmem.perBankWrBursts::0 8431 # Per bank write bursts
-system.physmem.perBankWrBursts::1 7989 # Per bank write bursts
-system.physmem.perBankWrBursts::2 8275 # Per bank write bursts
-system.physmem.perBankWrBursts::3 7382 # Per bank write bursts
-system.physmem.perBankWrBursts::4 7684 # Per bank write bursts
-system.physmem.perBankWrBursts::5 7400 # Per bank write bursts
-system.physmem.perBankWrBursts::6 7193 # Per bank write bursts
-system.physmem.perBankWrBursts::7 7021 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7374 # Per bank write bursts
-system.physmem.perBankWrBursts::9 7755 # Per bank write bursts
-system.physmem.perBankWrBursts::10 7777 # Per bank write bursts
-system.physmem.perBankWrBursts::11 7454 # Per bank write bursts
-system.physmem.perBankWrBursts::12 8052 # Per bank write bursts
-system.physmem.perBankWrBursts::13 8097 # Per bank write bursts
-system.physmem.perBankWrBursts::14 7762 # Per bank write bursts
-system.physmem.perBankWrBursts::15 8306 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 6364 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 25988 # Per bank write bursts
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+system.physmem.perBankRdBursts::2 25753 # Per bank write bursts
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+system.physmem.perBankRdBursts::4 25192 # Per bank write bursts
+system.physmem.perBankRdBursts::5 25524 # Per bank write bursts
+system.physmem.perBankRdBursts::6 25779 # Per bank write bursts
+system.physmem.perBankRdBursts::7 25095 # Per bank write bursts
+system.physmem.perBankRdBursts::8 25528 # Per bank write bursts
+system.physmem.perBankRdBursts::9 25751 # Per bank write bursts
+system.physmem.perBankRdBursts::10 25719 # Per bank write bursts
+system.physmem.perBankRdBursts::11 25446 # Per bank write bursts
+system.physmem.perBankRdBursts::12 25795 # Per bank write bursts
+system.physmem.perBankRdBursts::13 25643 # Per bank write bursts
+system.physmem.perBankRdBursts::14 25930 # Per bank write bursts
+system.physmem.perBankRdBursts::15 25199 # Per bank write bursts
+system.physmem.perBankWrBursts::0 8301 # Per bank write bursts
+system.physmem.perBankWrBursts::1 7506 # Per bank write bursts
+system.physmem.perBankWrBursts::2 7807 # Per bank write bursts
+system.physmem.perBankWrBursts::3 7337 # Per bank write bursts
+system.physmem.perBankWrBursts::4 6902 # Per bank write bursts
+system.physmem.perBankWrBursts::5 7063 # Per bank write bursts
+system.physmem.perBankWrBursts::6 7447 # Per bank write bursts
+system.physmem.perBankWrBursts::7 6982 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7245 # Per bank write bursts
+system.physmem.perBankWrBursts::9 7339 # Per bank write bursts
+system.physmem.perBankWrBursts::10 7570 # Per bank write bursts
+system.physmem.perBankWrBursts::11 7510 # Per bank write bursts
+system.physmem.perBankWrBursts::12 8378 # Per bank write bursts
+system.physmem.perBankWrBursts::13 8362 # Per bank write bursts
+system.physmem.perBankWrBursts::14 8512 # Per bank write bursts
+system.physmem.perBankWrBursts::15 7850 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 7 # Number of times write queue was full causing retry
-system.physmem.totGap 1903119235000 # Total gap between requests
+system.physmem.totGap 1905063366000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 411673 # Read request sizes (log2)
+system.physmem.readPktSize::6 410001 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 123979 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 317912 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 40920 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 43295 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 9256 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 77 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 122141 # Write request sizes (log2)
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system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::17 3331 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::28 8320 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 6563 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 6410 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::32 6098 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 278 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 199 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 168 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 171 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 186 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 174 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 147 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 148 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 166 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 139 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 140 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 145 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 129 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 108 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 81 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 59 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 56 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 65 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 84 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 79 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 77 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 70 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 64910 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 527.930488 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 320.008348 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 417.202697 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 14944 23.02% 23.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 11454 17.65% 40.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 5213 8.03% 48.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2920 4.50% 53.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2279 3.51% 56.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1787 2.75% 59.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1551 2.39% 61.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1716 2.64% 64.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 23046 35.50% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 64910 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5635 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 73.021650 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 2812.727565 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191 5632 99.95% 99.95% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15 1622 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 2255 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 3209 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 4243 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 5603 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 7045 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::26 9245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 8130 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 8196 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 6416 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 6332 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 6360 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 6016 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 305 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 205 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 186 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 175 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 182 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 171 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 133 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 149 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 123 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 132 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 147 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 165 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 157 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 150 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 145 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 149 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 119 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 103 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 102 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 94 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 74 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 59 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 51 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 64430 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 528.357101 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 319.789036 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 417.784578 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 14909 23.14% 23.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 11361 17.63% 40.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 5102 7.92% 48.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2869 4.45% 53.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2286 3.55% 56.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1687 2.62% 59.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1558 2.42% 61.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1655 2.57% 64.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 23003 35.70% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 64430 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 5515 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 74.305712 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 2843.118152 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191 5512 99.95% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5635 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5635 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 21.996806 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.958563 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 19.289473 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 4843 85.94% 85.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 143 2.54% 88.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 10 0.18% 88.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 227 4.03% 92.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 45 0.80% 93.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 4 0.07% 93.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 10 0.18% 93.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 10 0.18% 93.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 34 0.60% 94.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 6 0.11% 94.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 5 0.09% 94.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 2 0.04% 94.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 9 0.16% 94.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 2 0.04% 94.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 4 0.07% 95.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 1 0.02% 95.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 41 0.73% 95.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 13 0.23% 95.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 2 0.04% 96.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 176 3.12% 99.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 5 0.09% 99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 3 0.05% 99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 3 0.05% 99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 1 0.02% 99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 6 0.11% 99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 3 0.05% 99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 6 0.11% 99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 10 0.18% 99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 6 0.11% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151 1 0.02% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155 1 0.02% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 1 0.02% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195 1 0.02% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5635 # Writes before turning the bus around for reads
-system.physmem.totQLat 3887945250 # Total ticks spent queuing
-system.physmem.totMemAccLat 11603289000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2057425000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 9448.57 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 5515 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 5515 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 22.141614 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.970992 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 20.024334 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 4751 86.15% 86.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 123 2.23% 88.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 15 0.27% 88.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 231 4.19% 92.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 39 0.71% 93.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 12 0.22% 93.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 8 0.15% 93.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 4 0.07% 93.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 23 0.42% 94.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 3 0.05% 94.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 5 0.09% 94.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 2 0.04% 94.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 7 0.13% 94.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 3 0.05% 94.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 5 0.09% 94.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 28 0.51% 95.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 10 0.18% 95.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 2 0.04% 95.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 17 0.31% 95.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 177 3.21% 99.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 3 0.05% 99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 2 0.04% 99.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 2 0.04% 99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 4 0.07% 99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 2 0.04% 99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 4 0.07% 99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 5 0.09% 99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 3 0.05% 99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 5 0.09% 99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 8 0.15% 99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151 1 0.02% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155 2 0.04% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163 4 0.07% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171 2 0.04% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227 3 0.05% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 5515 # Writes before turning the bus around for reads
+system.physmem.totQLat 3875472500 # Total ticks spent queuing
+system.physmem.totMemAccLat 11559353750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2049035000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 9456.82 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 28198.57 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 13.84 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 4.17 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 13.84 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 4.17 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 28206.82 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.14 # Data bus utilization in percentage
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing
-system.physmem.readRowHits 371100 # Number of row buffer hits during reads
-system.physmem.writeRowHits 99427 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 80.20 # Row buffer hit rate for writes
-system.physmem.avgGap 3552902.32 # Average gap between requests
-system.physmem.pageHitRate 87.87 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 1802319562500 # Time in different power states
-system.physmem.memoryStateTime::REF 63549460000 # Time in different power states
+system.physmem.avgRdQLen 1.97 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 26.10 # Average write queue length when enqueuing
+system.physmem.readRowHits 369467 # Number of row buffer hits during reads
+system.physmem.writeRowHits 98020 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 90.16 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 80.25 # Row buffer hit rate for writes
+system.physmem.avgGap 3579990.62 # Average gap between requests
+system.physmem.pageHitRate 87.88 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 1804432107750 # Time in different power states
+system.physmem.memoryStateTime::REF 63614200000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 37254262500 # Time in different power states
+system.physmem.memoryStateTime::ACT 37016700250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 18054612 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 296849 # Transaction distribution
-system.membus.trans_dist::ReadResp 296569 # Transaction distribution
-system.membus.trans_dist::WriteReq 12351 # Transaction distribution
-system.membus.trans_dist::WriteResp 12351 # Transaction distribution
-system.membus.trans_dist::Writeback 82427 # Transaction distribution
+system.membus.trans_dist::ReadReq 296853 # Transaction distribution
+system.membus.trans_dist::ReadResp 296773 # Transaction distribution
+system.membus.trans_dist::WriteReq 13665 # Transaction distribution
+system.membus.trans_dist::WriteResp 13665 # Transaction distribution
+system.membus.trans_dist::Writeback 80589 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 5284 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 1479 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 3444 # Transaction distribution
-system.membus.trans_dist::ReadExReq 122594 # Transaction distribution
-system.membus.trans_dist::ReadExResp 122459 # Transaction distribution
-system.membus.trans_dist::BadAddressError 280 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39092 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 916085 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 560 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 955737 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83294 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 83294 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1039031 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68194 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31621440 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total 31689634 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 34349922 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 34349922 # Total data (bytes)
-system.membus.snoop_data_through_bus 10240 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 35504996 # Layer occupancy (ticks)
+system.membus.trans_dist::UpgradeReq 14563 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 9639 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 6364 # Transaction distribution
+system.membus.trans_dist::ReadExReq 121274 # Transaction distribution
+system.membus.trans_dist::ReadExResp 120582 # Transaction distribution
+system.membus.trans_dist::BadAddressError 80 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 41714 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 931819 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 973693 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83296 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 83296 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1056989 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 78682 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31396800 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 31475482 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 34135770 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 18692 # Total snoops (count)
+system.membus.snoop_fanout::samples 557285 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 557285 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 557285 # Request fanout histogram
+system.membus.reqLayer0.occupancy 40450499 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 1560042750 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 1545398747 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 374000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 102000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3834491323 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 3825672402 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 43141738 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 43153245 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 345839 # number of replacements
-system.l2c.tags.tagsinuse 65302.356632 # Cycle average of tags in use
-system.l2c.tags.total_refs 2646364 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 411006 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 6.438748 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 7093732750 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 53566.898021 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 4193.415796 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 5564.276304 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 1386.450480 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 591.316031 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.817366 # Average percentage of cache occupancy
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.783743 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.881289 # mshr miss rate for UpgradeReq accesses
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+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.966278 # mshr miss rate for SCUpgradeReq accesses
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75995.036384 # average ReadReq mshr miss latency
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+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10018.587068 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10012.048060 # average UpgradeReq mshr miss latency
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+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10023.274139 # average SCUpgradeReq mshr miss latency
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+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 91836.015146 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 71935.263085 # average ReadExReq mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58333.083894 # average overall mshr miss latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.tags.replacements 41695 # number of replacements
-system.iocache.tags.tagsinuse 0.219567 # Cycle average of tags in use
+system.iocache.tags.replacements 41697 # number of replacements
+system.iocache.tags.tagsinuse 0.496947 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 41713 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 1710336549000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide 0.219567 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide 0.013723 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.013723 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 1710336805000 # Cycle when the warmup percentage was hit.
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system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 375543 # Number of tag accesses
-system.iocache.tags.data_accesses 375543 # Number of data accesses
+system.iocache.tags.tag_accesses 375577 # Number of tag accesses
+system.iocache.tags.data_accesses 375577 # Number of data accesses
system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits
-system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
-system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses
-system.iocache.demand_misses::total 175 # number of demand (read+write) misses
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-system.iocache.overall_misses::total 175 # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide 21364383 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 21364383 # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 21364383 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 21364383 # number of demand (read+write) miss cycles
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-system.iocache.overall_miss_latency::total 21364383 # number of overall miss cycles
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-system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
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-system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
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-system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses
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-system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses
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system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
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system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122082.188571 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 122082.188571 # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 122082.188571 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 122082.188571 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 122082.188571 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 122082.188571 # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121956.966102 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 121956.966102 # average ReadReq miss latency
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+system.iocache.demand_avg_miss_latency::total 121956.966102 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 121956.966102 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 121956.966102 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 41552 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses
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+system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
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-system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12263383 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 12263383 # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2507056568 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2507056568 # number of WriteInvalidateReq MSHR miss cycles
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-system.iocache.overall_mshr_miss_latency::tsunami.ide 12263383 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 12263383 # number of overall MSHR miss cycles
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system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
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system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70076.474286 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60335.400655 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60335.400655 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 70076.474286 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 70076.474286 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 69951.316384 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60474.936465 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60474.936465 # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 69951.316384 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 69951.316384 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 13702956 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 11991857 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 276088 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 8588922 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 4683455 # Number of BTB hits
+system.cpu0.branchPred.lookups 14962614 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 13045209 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 300344 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 9143692 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 5116520 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 54.529020 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 677984 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 15448 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 55.956828 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 756655 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 14726 # Number of incorrect RAS predictions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 7950804 # DTB read hits
-system.cpu0.dtb.read_misses 30543 # DTB read misses
-system.cpu0.dtb.read_acv 546 # DTB read access violations
-system.cpu0.dtb.read_accesses 683229 # DTB read accesses
-system.cpu0.dtb.write_hits 5159026 # DTB write hits
-system.cpu0.dtb.write_misses 6845 # DTB write misses
-system.cpu0.dtb.write_acv 353 # DTB write access violations
-system.cpu0.dtb.write_accesses 234573 # DTB write accesses
-system.cpu0.dtb.data_hits 13109830 # DTB hits
-system.cpu0.dtb.data_misses 37388 # DTB misses
-system.cpu0.dtb.data_acv 899 # DTB access violations
-system.cpu0.dtb.data_accesses 917802 # DTB accesses
-system.cpu0.itb.fetch_hits 1312718 # ITB hits
-system.cpu0.itb.fetch_misses 29261 # ITB misses
-system.cpu0.itb.fetch_acv 629 # ITB acv
-system.cpu0.itb.fetch_accesses 1341979 # ITB accesses
+system.cpu0.dtb.read_hits 8668714 # DTB read hits
+system.cpu0.dtb.read_misses 31568 # DTB read misses
+system.cpu0.dtb.read_acv 533 # DTB read access violations
+system.cpu0.dtb.read_accesses 683834 # DTB read accesses
+system.cpu0.dtb.write_hits 5507711 # DTB write hits
+system.cpu0.dtb.write_misses 6832 # DTB write misses
+system.cpu0.dtb.write_acv 377 # DTB write access violations
+system.cpu0.dtb.write_accesses 235007 # DTB write accesses
+system.cpu0.dtb.data_hits 14176425 # DTB hits
+system.cpu0.dtb.data_misses 38400 # DTB misses
+system.cpu0.dtb.data_acv 910 # DTB access violations
+system.cpu0.dtb.data_accesses 918841 # DTB accesses
+system.cpu0.itb.fetch_hits 1355401 # ITB hits
+system.cpu0.itb.fetch_misses 29256 # ITB misses
+system.cpu0.itb.fetch_acv 621 # ITB acv
+system.cpu0.itb.fetch_accesses 1384657 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 99665250 # number of cpu cycles simulated
+system.cpu0.numCycles 108456707 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 22511576 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 60582407 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 13702956 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 5361439 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 70984108 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 933480 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 621 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles 27412 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 1463366 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 292819 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 7109889 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 200075 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples 95746858 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.632735 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 1.928110 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 24325754 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 66694894 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 14962614 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 5873175 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 76828249 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1001726 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 825 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles 30281 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 1454626 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 459540 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 204 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 7777949 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 213350 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 103600342 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.643771 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 1.943909 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 84335489 88.08% 88.08% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 757900 0.79% 88.87% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 1598110 1.67% 90.54% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 658612 0.69% 91.23% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 2290747 2.39% 93.62% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 510807 0.53% 94.16% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 540667 0.56% 94.72% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 744782 0.78% 95.50% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 4309744 4.50% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 91056774 87.89% 87.89% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 810107 0.78% 88.67% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 1760430 1.70% 90.37% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 739408 0.71% 91.09% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 2516394 2.43% 93.52% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 557837 0.54% 94.05% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 633248 0.61% 94.67% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 717698 0.69% 95.36% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4808446 4.64% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 95746858 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.137490 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.607859 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 18154184 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 68366814 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 7221268 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 1568077 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 436514 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 432928 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 30567 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 53177978 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 98719 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 436514 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 18925396 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 44877173 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 16564638 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 7942906 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 7000229 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 51314401 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 200370 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 1702156 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents 121650 # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents 3596195 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands 34369689 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 62476617 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 62360377 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 107565 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 30276917 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 4092764 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 1298231 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 191875 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 11393500 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 8037568 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 5366781 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1135735 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 800748 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 45795204 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1644687 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 45103865 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 41971 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 5328763 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 2477826 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 1134880 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 95746858 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.471074 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.201865 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 103600342 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.137959 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.614945 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 19762809 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 73625982 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 8017389 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 1725855 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 468306 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 492047 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 33030 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 58728782 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 102789 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 468306 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 20585060 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 48251734 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 17899835 # count of cycles rename stalled for serializing inst
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+system.cpu0.rename.UnblockCycles 7576350 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 56729728 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 201548 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 2018005 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 142949 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 3756211 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands 38050244 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 69305662 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 69181835 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 114815 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 33467059 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 4583177 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 1358842 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 197413 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 12487165 # count of insts added to the skid buffer
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+system.cpu0.memDep0.insertedStores 5770533 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1295730 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 947864 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 50680779 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1726956 # Number of non-speculative instructions added to the IQ
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+system.cpu0.iq.iqSquashedInstsExamined 5972660 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 2859786 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu0.iq.issued_per_cycle::2 3430688 3.58% 92.61% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2350675 2.46% 95.06% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2374207 2.48% 97.54% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1175968 1.23% 98.77% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 779493 0.81% 99.58% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 300669 0.31% 99.90% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 97495 0.10% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 83011266 80.13% 80.13% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 8965198 8.65% 88.78% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 3720190 3.59% 92.37% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2652497 2.56% 94.93% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2683429 2.59% 97.52% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1272361 1.23% 98.75% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 837773 0.81% 99.56% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 348219 0.34% 99.89% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 109409 0.11% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 95746858 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 103600342 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 143906 17.61% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 17.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 398143 48.73% 66.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 274956 33.65% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 174041 19.05% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 435557 47.67% 66.72% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 304020 33.28% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 30829458 68.35% 68.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 46395 0.10% 68.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 26948 0.06% 68.52% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.52% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.52% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.52% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 8252345 18.30% 86.82% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5217820 11.57% 98.39% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess 725236 1.61% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 34383436 69.05% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 54432 0.11% 69.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 27661 0.06% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 8987932 18.05% 87.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5577936 11.20% 98.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess 760973 1.53% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 45103865 # Type of FU issued
-system.cpu0.iq.rate 0.452554 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 817005 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.018114 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 186342910 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 52562719 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 43916640 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 470653 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 221373 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 216432 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 45663938 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 253152 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 522094 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 49798033 # Type of FU issued
+system.cpu0.iq.rate 0.459151 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 913618 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.018346 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 203658933 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 58161397 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 48529720 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 503398 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 236532 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 231367 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 50437037 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 270834 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 558638 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 946690 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 4799 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 15752 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 387148 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1034329 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 4271 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 17854 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 485625 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 13610 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 357638 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 18828 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 348593 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 436514 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 41413967 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 1424350 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 50298451 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 103444 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 8037568 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 5366781 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 1456887 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 31578 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 1238658 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 15752 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 134081 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 309122 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 443203 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 44677716 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 8001376 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 426148 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 468306 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 44263410 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 1515089 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 55600538 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 120472 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 8791454 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 5770533 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 1526368 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 47186 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 1245112 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 17854 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 151677 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 326896 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 478573 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 49327282 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 8721913 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 470750 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 2858560 # number of nop insts executed
-system.cpu0.iew.exec_refs 13178604 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 7039370 # Number of branches executed
-system.cpu0.iew.exec_stores 5177228 # Number of stores executed
-system.cpu0.iew.exec_rate 0.448278 # Inst execution rate
-system.cpu0.iew.wb_sent 44227196 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 44133072 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 22691402 # num instructions producing a value
-system.cpu0.iew.wb_consumers 31140086 # num instructions consuming a value
+system.cpu0.iew.exec_nop 3192803 # number of nop insts executed
+system.cpu0.iew.exec_refs 14249477 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 7854369 # Number of branches executed
+system.cpu0.iew.exec_stores 5527564 # Number of stores executed
+system.cpu0.iew.exec_rate 0.454811 # Inst execution rate
+system.cpu0.iew.wb_sent 48871282 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 48761087 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 25232648 # num instructions producing a value
+system.cpu0.iew.wb_consumers 34850080 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.442813 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.728688 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.449590 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.724034 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 5846321 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 509807 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 407712 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 94708833 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.468364 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.405169 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 6529157 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 538982 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 437949 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 102449449 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.477940 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.411753 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 79035549 83.45% 83.45% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 6314508 6.67% 90.12% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 3292930 3.48% 93.60% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 1802282 1.90% 95.50% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 1366338 1.44% 96.94% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 489382 0.52% 97.46% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 366889 0.39% 97.85% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 390234 0.41% 98.26% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1650721 1.74% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 85074848 83.04% 83.04% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 6905483 6.74% 89.78% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 3794087 3.70% 93.48% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 1998795 1.95% 95.44% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 1509892 1.47% 96.91% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 553563 0.54% 97.45% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 413229 0.40% 97.85% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 408476 0.40% 98.25% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1791076 1.75% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 94708833 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 44358216 # Number of instructions committed
-system.cpu0.commit.committedOps 44358216 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 102449449 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 48964739 # Number of instructions committed
+system.cpu0.commit.committedOps 48964739 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 12070511 # Number of memory references committed
-system.cpu0.commit.loads 7090878 # Number of loads committed
-system.cpu0.commit.membars 170277 # Number of memory barriers committed
-system.cpu0.commit.branches 6663650 # Number of branches committed
-system.cpu0.commit.fp_insts 213529 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 41141903 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 549728 # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass 2498518 5.63% 5.63% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 28814427 64.96% 70.59% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 45393 0.10% 70.69% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.69% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd 26477 0.06% 70.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 7261155 16.37% 87.13% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 4985127 11.24% 98.37% # Class of committed instruction
-system.cpu0.commit.op_class_0::IprAccess 725236 1.63% 100.00% # Class of committed instruction
+system.cpu0.commit.refs 13042033 # Number of memory references committed
+system.cpu0.commit.loads 7757125 # Number of loads committed
+system.cpu0.commit.membars 182252 # Number of memory barriers committed
+system.cpu0.commit.branches 7421354 # Number of branches committed
+system.cpu0.commit.fp_insts 228314 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 45387875 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 614232 # Number of function calls committed.
+system.cpu0.commit.op_class_0::No_OpClass 2794177 5.71% 5.71% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 32097051 65.55% 71.26% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult 53183 0.11% 71.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd 27190 0.06% 71.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead 7939377 16.21% 87.64% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite 5290905 10.81% 98.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::IprAccess 760973 1.55% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total 44358216 # Class of committed instruction
-system.cpu0.commit.bw_lim_events 1650721 # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total 48964739 # Class of committed instruction
+system.cpu0.commit.bw_lim_events 1791076 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 143064224 # The number of ROB reads
-system.cpu0.rob.rob_writes 101447849 # The number of ROB writes
-system.cpu0.timesIdled 414726 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 3918392 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 3706577488 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 41863465 # Number of Instructions Simulated
-system.cpu0.committedOps 41863465 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 2.380721 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.380721 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.420041 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.420041 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 58777310 # number of integer regfile reads
-system.cpu0.int_regfile_writes 31962259 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 106639 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 106808 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 1588469 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 729535 # number of misc regfile writes
+system.cpu0.rob.rob_reads 155949601 # The number of ROB reads
+system.cpu0.rob.rob_writes 112132496 # The number of ROB writes
+system.cpu0.timesIdled 444606 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 4856365 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 3701678908 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 46174329 # Number of Instructions Simulated
+system.cpu0.committedOps 46174329 # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi 2.348853 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.348853 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.425740 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.425740 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 65048250 # number of integer regfile reads
+system.cpu0.int_regfile_writes 35377381 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 113752 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 114375 # number of floating regfile writes
+system.cpu0.misc_regfile_reads 1675774 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 759002 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.throughput 115690704 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 2250904 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2250609 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 12351 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 12351 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 841911 # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq 2231724 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2231628 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 13665 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 13665 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 804733 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq 41559 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 5326 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 1552 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 6878 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 312265 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 312265 # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError 280 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1525692 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2740000 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 708608 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1000724 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 5975024 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 48817472 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 104660497 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22674112 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39558737 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 215710818 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 215700578 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 4473152 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 5085967365 # Layer occupancy (ticks)
+system.toL2Bus.trans_dist::UpgradeReq 14709 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 9717 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 24426 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 295921 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 295921 # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1632137 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3219560 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 626624 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 407513 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 5885834 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 52223552 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 123671600 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20051136 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 14868394 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 210814682 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 92075 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 3391171 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 3.012307 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.110253 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 3349435 98.77% 98.77% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 41736 1.23% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3391171 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 4911486557 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 720000 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 3437989936 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 3677796473 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 4906988127 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 5655554210 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 1597018302 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 1411093549 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 1654443775 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%)
-system.iobus.throughput 1434388 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 7370 # Transaction distribution
-system.iobus.trans_dist::ReadResp 7370 # Transaction distribution
-system.iobus.trans_dist::WriteReq 53903 # Transaction distribution
-system.iobus.trans_dist::WriteResp 53903 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10492 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes)
+system.toL2Bus.respLayer3.occupancy 701201756 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 7369 # Transaction distribution
+system.iobus.trans_dist::ReadResp 7369 # Transaction distribution
+system.iobus.trans_dist::WriteReq 55215 # Transaction distribution
+system.iobus.trans_dist::WriteResp 55217 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 2 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13126 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 464 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 39092 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 122546 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 41968 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 68194 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 2729818 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 2729818 # Total data (bytes)
-system.iobus.reqLayer0.occupancy 9847000 # Layer occupancy (ticks)
+system.iobus.pkt_count_system.bridge.master::total 41714 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83458 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total 83458 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 125172 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 52504 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1856 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 78682 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661640 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::total 2661640 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2740322 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 12481000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 347000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer29.occupancy 374411689 # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy 374418188 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 26741000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 28049000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 42019262 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 42021755 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.icache.tags.replacements 762211 # number of replacements
-system.cpu0.icache.tags.tagsinuse 508.848890 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 6309809 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 762721 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 8.272762 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 26485928250 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.848890 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993845 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 418 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 7872808 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 7872808 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 6309809 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 6309809 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 6309809 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 6309809 # number of demand (read+write) hits
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-system.cpu0.dcache.WriteReq_avg_miss_latency::total 45202.008596 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16085.640759 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16085.640759 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6250.729765 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6250.729765 # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37247.913936 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 37247.913936 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37247.913936 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 37247.913936 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 3702426 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 3454 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 160595 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 88 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.054429 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 39.250000 # average number of cycles each access was blocked
+system.cpu0.dcache.tags.tag_accesses 53654077 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 53654077 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 6167393 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 6167393 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 3426848 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 3426848 # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 149101 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 149101 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171294 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 171294 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 9594241 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 9594241 # number of demand (read+write) hits
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+system.cpu0.dcache.overall_hits::total 9594241 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 1498647 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 1498647 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 1667216 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 1667216 # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19081 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 19081 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4721 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 4721 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 3165863 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 3165863 # number of demand (read+write) misses
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+system.cpu0.dcache.overall_misses::total 3165863 # number of overall misses
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+system.cpu0.dcache.ReadReq_miss_latency::total 39188841077 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77581958562 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 77581958562 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 288599741 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 288599741 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 35650235 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total 35650235 # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 116770799639 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 116770799639 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 116770799639 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 116770799639 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 7666040 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 7666040 # number of ReadReq accesses(hits+misses)
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+system.cpu0.dcache.WriteReq_accesses::total 5094064 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 168182 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 168182 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 176015 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 176015 # number of StoreCondReq accesses(hits+misses)
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+system.cpu0.dcache.overall_accesses::total 12760104 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195492 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.195492 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.327286 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.327286 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113454 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113454 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.026822 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.026822 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248106 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.248106 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248106 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.248106 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26149.480883 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 26149.480883 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46533.837584 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 46533.837584 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15124.979875 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15124.979875 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7551.416014 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7551.416014 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36884.350220 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 36884.350220 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36884.350220 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 36884.350220 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 3791444 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 2983 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 159835 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 87 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.720987 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 34.287356 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 568073 # number of writebacks
-system.cpu0.dcache.writebacks::total 568073 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 499697 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 499697 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1402831 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 1402831 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4326 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4326 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 1902528 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 1902528 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 1902528 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 1902528 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 822474 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 822474 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 241450 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 241450 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 12284 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12284 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 766 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 766 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 1063924 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 1063924 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 1063924 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 1063924 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24909734008 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24909734008 # number of ReadReq MSHR miss cycles
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-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10782476086 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 145144507 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145144507 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3254941 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3254941 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35692210094 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 35692210094 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35692210094 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 35692210094 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 992378000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 992378000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1672126998 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1672126998 # number of WriteReq MSHR uncacheable cycles
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-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2664504998 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.117705 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.117705 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050341 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050341 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075031 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075031 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004479 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004479 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090286 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.090286 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090286 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.090286 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30286.348271 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30286.348271 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44657.179896 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44657.179896 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11815.736486 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11815.736486 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4249.270235 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4249.270235 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33547.706503 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33547.706503 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33547.706503 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33547.706503 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 710527 # number of writebacks
+system.cpu0.dcache.writebacks::total 710527 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 518299 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 518299 # number of ReadReq MSHR hits
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+system.cpu0.dcache.WriteReq_mshr_hits::total 1417662 # number of WriteReq MSHR hits
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+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4443 # number of LoadLockedReq MSHR hits
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+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249554 # number of WriteReq MSHR misses
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+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27067717433 # number of ReadReq MSHR miss cycles
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3652205498 # number of overall MSHR uncacheable cycles
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+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048989 # mshr miss rate for WriteReq accesses
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+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087037 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087037 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.026822 # mshr miss rate for StoreCondReq accesses
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+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096387 # mshr miss rate for demand accesses
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+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096387 # mshr miss rate for overall accesses
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+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27610.315350 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27610.315350 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45192.335454 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45192.335454 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10099.689712 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10099.689712 # average LoadLockedReq mshr miss latency
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+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5551.104639 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31177.805642 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31177.805642 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31177.805642 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31177.805642 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 5770916 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 5004196 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 122577 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 3556553 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 1526133 # Number of BTB hits
+system.cpu1.branchPred.lookups 4639832 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 4063901 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 82203 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 2874870 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 1132301 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 42.910453 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 301064 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 7748 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 39.386164 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 224009 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 7064 # Number of incorrect RAS predictions.
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 3015540 # DTB read hits
-system.cpu1.dtb.read_misses 12269 # DTB read misses
-system.cpu1.dtb.read_acv 5 # DTB read access violations
-system.cpu1.dtb.read_accesses 293761 # DTB read accesses
-system.cpu1.dtb.write_hits 1836726 # DTB write hits
-system.cpu1.dtb.write_misses 2353 # DTB write misses
-system.cpu1.dtb.write_acv 39 # DTB write access violations
-system.cpu1.dtb.write_accesses 109652 # DTB write accesses
-system.cpu1.dtb.data_hits 4852266 # DTB hits
-system.cpu1.dtb.data_misses 14622 # DTB misses
-system.cpu1.dtb.data_acv 44 # DTB access violations
-system.cpu1.dtb.data_accesses 403413 # DTB accesses
-system.cpu1.itb.fetch_hits 632341 # ITB hits
-system.cpu1.itb.fetch_misses 5352 # ITB misses
-system.cpu1.itb.fetch_acv 51 # ITB acv
-system.cpu1.itb.fetch_accesses 637693 # ITB accesses
+system.cpu1.dtb.read_hits 2413283 # DTB read hits
+system.cpu1.dtb.read_misses 10075 # DTB read misses
+system.cpu1.dtb.read_acv 6 # DTB read access violations
+system.cpu1.dtb.read_accesses 292262 # DTB read accesses
+system.cpu1.dtb.write_hits 1597058 # DTB write hits
+system.cpu1.dtb.write_misses 2093 # DTB write misses
+system.cpu1.dtb.write_acv 37 # DTB write access violations
+system.cpu1.dtb.write_accesses 110264 # DTB write accesses
+system.cpu1.dtb.data_hits 4010341 # DTB hits
+system.cpu1.dtb.data_misses 12168 # DTB misses
+system.cpu1.dtb.data_acv 43 # DTB access violations
+system.cpu1.dtb.data_accesses 402526 # DTB accesses
+system.cpu1.itb.fetch_hits 608432 # ITB hits
+system.cpu1.itb.fetch_misses 5602 # ITB misses
+system.cpu1.itb.fetch_acv 65 # ITB acv
+system.cpu1.itb.fetch_accesses 614034 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 26335588 # number of cpu cycles simulated
+system.cpu1.numCycles 19085086 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 9800268 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 22981944 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 5770916 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 1827197 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 14019681 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 419510 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 307 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles 23776 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 208449 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 196331 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 2522136 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 89875 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 24458620 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.939626 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.331670 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 8490084 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 17874574 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 4639832 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 1356310 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 9216388 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 327612 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.MiscStallCycles 26792 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 219924 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 67319 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 1967111 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 67009 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples 18184335 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.982966 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.394246 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 20375648 83.31% 83.31% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 230665 0.94% 84.25% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 464859 1.90% 86.15% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 295118 1.21% 87.36% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 600413 2.45% 89.81% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 204861 0.84% 90.65% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 257669 1.05% 91.70% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 270860 1.11% 92.81% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 1758527 7.19% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 15065350 82.85% 82.85% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 205923 1.13% 83.98% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 307986 1.69% 85.67% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 226074 1.24% 86.92% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 391185 2.15% 89.07% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 151633 0.83% 89.90% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 170482 0.94% 90.84% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 296956 1.63% 92.47% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 1368746 7.53% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 24458620 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.219130 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.872657 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 8213195 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 12716086 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 2925937 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 406668 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 196733 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 189397 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 13167 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 19294426 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 40930 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 196733 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 8443455 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 3954170 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 7253500 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 3074788 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 1535972 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 18421784 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 5378 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 385976 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 36959 # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents 551165 # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands 12165906 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 21959681 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 21890085 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 63650 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 10221482 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 1944424 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 582778 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 59316 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 3316426 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 3128488 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 1940399 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 395849 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 259099 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 16224994 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 722304 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 15758531 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 26415 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 2553169 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 1203962 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 524576 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 24458620 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.644294 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.366216 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 18184335 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.243113 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.936573 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 6979571 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 8518725 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 2274233 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 256003 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 155802 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 137194 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 8084 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 14619784 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 26597 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 155802 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 7159934 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 614392 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 6924569 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 2350603 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 979033 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 13886683 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 9133 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 71770 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 16856 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 365854 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands 9047331 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 16422939 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 16337871 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 78141 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 7835755 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 1211576 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 562751 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 58900 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 2353285 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 2494844 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 1679253 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 277357 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 156260 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 12201401 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 661557 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 11978627 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 22551 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 1735034 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 788886 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 473891 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 18184335 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.658733 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.375592 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 17964380 73.45% 73.45% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 2773024 11.34% 84.79% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 1191873 4.87% 89.66% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 895755 3.66% 93.32% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 840464 3.44% 96.76% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 400907 1.64% 98.40% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 238226 0.97% 99.37% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 113179 0.46% 99.83% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 40812 0.17% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 13164849 72.40% 72.40% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 2231541 12.27% 84.67% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 929377 5.11% 89.78% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 639609 3.52% 93.30% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 582340 3.20% 96.50% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 317160 1.74% 98.24% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 211313 1.16% 99.41% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 78701 0.43% 99.84% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 29445 0.16% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 24458620 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 18184335 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 56470 15.54% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 15.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 184321 50.72% 66.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 122598 33.74% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 24291 8.14% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 162499 54.43% 62.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 111756 37.43% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 3518 0.02% 0.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 10371294 65.81% 65.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 24284 0.15% 65.99% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.99% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 11773 0.07% 66.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 66.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 3139820 19.92% 86.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 1865147 11.84% 97.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess 340936 2.16% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 3518 0.03% 0.03% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 7464610 62.32% 62.35% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 20078 0.17% 62.51% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.51% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 12377 0.10% 62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 62.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 2524426 21.07% 83.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 1623488 13.55% 97.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess 328371 2.74% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 15758531 # Type of FU issued
-system.cpu1.iq.rate 0.598374 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 363389 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.023060 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 56111313 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 19387392 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 15262127 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 254173 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 119441 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 117263 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 15982004 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 136398 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 157695 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 11978627 # Type of FU issued
+system.cpu1.iq.rate 0.627643 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 298546 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.024923 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 42145115 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 14453685 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 11556214 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 317571 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 148430 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 146304 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 12102736 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 170919 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 117615 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 453605 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 1302 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 6552 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 197079 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 314973 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 1097 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 4259 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 145447 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 5589 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 74646 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 424 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 56672 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 196733 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 3102898 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 407577 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 17959821 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 47400 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 3128488 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 1940399 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 647154 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 24325 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 312873 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 6552 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 58721 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 143362 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 202083 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 15559963 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 3035862 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 198568 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 155802 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 328818 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 249531 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 13597003 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 38106 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 2494844 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 1679253 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 593871 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 4649 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 243688 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 4259 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 37580 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 120039 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 157619 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 11824953 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 2433073 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 153674 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 1012523 # number of nop insts executed
-system.cpu1.iew.exec_refs 4881099 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 2446532 # Number of branches executed
-system.cpu1.iew.exec_stores 1845237 # Number of stores executed
-system.cpu1.iew.exec_rate 0.590834 # Inst execution rate
-system.cpu1.iew.wb_sent 15420680 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 15379390 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 7566791 # num instructions producing a value
-system.cpu1.iew.wb_consumers 10761562 # num instructions consuming a value
+system.cpu1.iew.exec_nop 734045 # number of nop insts executed
+system.cpu1.iew.exec_refs 4040076 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 1766091 # Number of branches executed
+system.cpu1.iew.exec_stores 1607003 # Number of stores executed
+system.cpu1.iew.exec_rate 0.619591 # Inst execution rate
+system.cpu1.iew.wb_sent 11733612 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 11702518 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 5498346 # num instructions producing a value
+system.cpu1.iew.wb_consumers 7839453 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.583977 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.703131 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.613176 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.701369 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 2776166 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 197728 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 185190 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 23976589 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.630910 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.597118 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 1874564 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 187666 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 145503 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 17835799 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.653281 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.639800 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 18550941 77.37% 77.37% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 2272481 9.48% 86.85% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 1151381 4.80% 91.65% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 578443 2.41% 94.06% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 385291 1.61% 95.67% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 189866 0.79% 96.46% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 157998 0.66% 97.12% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 143488 0.60% 97.72% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 546700 2.28% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 13664737 76.61% 76.61% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 1906046 10.69% 87.30% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 699754 3.92% 91.22% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 424730 2.38% 93.61% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 316948 1.78% 95.38% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 133544 0.75% 96.13% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 114109 0.64% 96.77% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 155571 0.87% 97.64% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 420360 2.36% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 23976589 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 15127070 # Number of instructions committed
-system.cpu1.commit.committedOps 15127070 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 17835799 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 11651787 # Number of instructions committed
+system.cpu1.commit.committedOps 11651787 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 4418203 # Number of memory references committed
-system.cpu1.commit.loads 2674883 # Number of loads committed
-system.cpu1.commit.membars 66521 # Number of memory barriers committed
-system.cpu1.commit.branches 2263870 # Number of branches committed
-system.cpu1.commit.fp_insts 115331 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 13957396 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 240978 # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass 845832 5.59% 5.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 9417463 62.26% 67.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 23911 0.16% 68.01% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 0 0.00% 68.01% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 11769 0.08% 68.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 68.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 68.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 68.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 1759 0.01% 68.09% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 68.09% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 68.09% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 68.09% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 68.09% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 68.09% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 68.09% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 68.09% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 68.09% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 68.09% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 68.09% # Class of committed instruction
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+system.cpu1.icache.overall_mshr_miss_rate::total 0.159282 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11616.894442 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11616.894442 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11616.894442 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11616.894442 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11616.894442 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11616.894442 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements 360788 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 496.086183 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 3613456 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 361109 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 10.006552 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 40126349500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 496.086183 # Average occupied blocks per requestor
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-system.cpu1.dcache.tags.occ_percent::total 0.968918 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 321 # Occupied blocks per task id
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-system.cpu1.dcache.tags.tag_accesses 18510307 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 18510307 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 2220866 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 2220866 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 1307515 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 1307515 # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 45364 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 45364 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 48883 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 48883 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 3528381 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 3528381 # number of demand (read+write) hits
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-system.cpu1.dcache.overall_hits::total 3528381 # number of overall hits
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-system.cpu1.dcache.ReadReq_misses::total 524895 # number of ReadReq misses
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-system.cpu1.dcache.LoadLockedReq_misses::total 8897 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 786 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 786 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 903784 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 903784 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 903784 # number of overall misses
-system.cpu1.dcache.overall_misses::total 903784 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8191623763 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 8191623763 # number of ReadReq miss cycles
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-system.cpu1.dcache.WriteReq_miss_latency::total 14087810149 # number of WriteReq miss cycles
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-system.cpu1.dcache.LoadLockedReq_miss_latency::total 135761491 # number of LoadLockedReq miss cycles
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-system.cpu1.dcache.StoreCondReq_miss_latency::total 5726098 # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 22279433912 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 22279433912 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 22279433912 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 22279433912 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 2745761 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 2745761 # number of ReadReq accesses(hits+misses)
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-system.cpu1.dcache.WriteReq_accesses::total 1686404 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 54261 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 54261 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 49669 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 49669 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 4432165 # number of demand (read+write) accesses
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-system.cpu1.dcache.overall_accesses::total 4432165 # number of overall (read+write) accesses
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-system.cpu1.dcache.ReadReq_miss_rate::total 0.191166 # miss rate for ReadReq accesses
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-system.cpu1.dcache.WriteReq_miss_rate::total 0.224673 # miss rate for WriteReq accesses
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-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.163967 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.015825 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.015825 # miss rate for StoreCondReq accesses
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-system.cpu1.dcache.demand_miss_rate::total 0.203915 # miss rate for demand accesses
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-system.cpu1.dcache.overall_miss_rate::total 0.203915 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15606.214125 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15606.214125 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37181.892715 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 37181.892715 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15259.243678 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15259.243678 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7285.111959 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7285.111959 # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24651.281625 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 24651.281625 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24651.281625 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 24651.281625 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 560522 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 381 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 27149 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 19 # number of cycles access was blocked
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-system.cpu1.dcache.avg_blocked_cycles::no_targets 20.052632 # average number of cycles each access was blocked
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+system.cpu1.dcache.tags.total_refs 3241153 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 140473 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 23.073139 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 39570817000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.227589 # Average occupied blocks per requestor
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+system.cpu1.dcache.tags.tag_accesses 15302146 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 15302146 # Number of data accesses
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+system.cpu1.dcache.ReadReq_hits::total 1936775 # number of ReadReq hits
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+system.cpu1.dcache.overall_hits::total 3148850 # number of overall hits
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+system.cpu1.dcache.ReadReq_misses::total 269383 # number of ReadReq misses
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+system.cpu1.dcache.demand_misses::total 534807 # number of demand (read+write) misses
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+system.cpu1.dcache.overall_misses::total 534807 # number of overall misses
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+system.cpu1.dcache.ReadReq_miss_latency::total 4084517434 # number of ReadReq miss cycles
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+system.cpu1.dcache.LoadLockedReq_miss_latency::total 77678496 # number of LoadLockedReq miss cycles
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+system.cpu1.dcache.demand_miss_latency::total 12636630475 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 12636630475 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 12636630475 # number of overall miss cycles
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+system.cpu1.dcache.demand_accesses::total 3683657 # number of demand (read+write) accesses
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+system.cpu1.dcache.overall_accesses::total 3683657 # number of overall (read+write) accesses
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+system.cpu1.dcache.ReadReq_miss_rate::total 0.122105 # miss rate for ReadReq accesses
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+system.cpu1.dcache.WriteReq_miss_rate::total 0.179644 # miss rate for WriteReq accesses
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+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.151263 # miss rate for LoadLockedReq accesses
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+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100708 # miss rate for StoreCondReq accesses
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+system.cpu1.dcache.demand_miss_rate::total 0.145184 # miss rate for demand accesses
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+system.cpu1.dcache.overall_miss_rate::total 0.145184 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15162.491449 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15162.491449 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32220.571768 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 32220.571768 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9543.985256 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9543.985256 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7361.636309 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7361.636309 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23628.393935 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 23628.393935 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23628.393935 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 23628.393935 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 376916 # number of cycles access was blocked
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+system.cpu1.dcache.blocked::no_mshrs 18544 # number of cycles access was blocked
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+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 20.325496 # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets 31.272727 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 273838 # number of writebacks
-system.cpu1.dcache.writebacks::total 273838 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 229504 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 229504 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 313811 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 313811 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1705 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1705 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 543315 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 543315 # number of demand (read+write) MSHR hits
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-system.cpu1.dcache.overall_mshr_hits::total 543315 # number of overall MSHR hits
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-system.cpu1.dcache.ReadReq_mshr_misses::total 295391 # number of ReadReq MSHR misses
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-system.cpu1.dcache.WriteReq_mshr_misses::total 65078 # number of WriteReq MSHR misses
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-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7192 # number of LoadLockedReq MSHR misses
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-system.cpu1.dcache.StoreCondReq_mshr_misses::total 786 # number of StoreCondReq MSHR misses
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-system.cpu1.dcache.overall_mshr_misses::total 360469 # number of overall MSHR misses
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-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 81043507 # number of LoadLockedReq MSHR miss cycles
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-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4153902 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5956844830 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 5956844830 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5956844830 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 5956844830 # number of overall MSHR miss cycles
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-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.107581 # mshr miss rate for ReadReq accesses
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-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.132545 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.132545 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.015825 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.015825 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.081330 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.081330 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.081330 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.081330 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12928.078899 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12928.078899 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32852.986816 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32852.986816 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11268.563265 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11268.563265 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5284.862595 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5284.862595 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16525.262450 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16525.262450 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16525.262450 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16525.262450 # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 94206 # number of writebacks
+system.cpu1.dcache.writebacks::total 94206 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 165989 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 165989 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 215339 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 215339 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 655 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 655 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 381328 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 381328 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 381328 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 381328 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 103394 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 103394 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 50085 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 50085 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7484 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7484 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 4996 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 4996 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 153479 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 153479 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 153479 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 153479 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1212902508 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1212902508 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1317911046 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1317911046 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 54853004 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 54853004 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 26784265 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 26784265 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2530813554 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 2530813554 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2530813554 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 2530813554 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29140000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29140000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 708818500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 708818500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 737958500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 737958500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.046866 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.046866 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033899 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033899 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.139090 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.139090 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100708 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100708 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.041665 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.041665 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.041665 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.041665 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11730.879045 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11730.879045 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26313.487990 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26313.487990 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7329.369856 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7329.369856 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5361.141914 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5361.141914 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16489.640628 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16489.640628 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16489.640628 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16489.640628 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 4820 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 161850 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 55184 39.67% 39.67% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 131 0.09% 39.77% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1924 1.38% 41.15% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 16 0.01% 41.16% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 81844 58.84% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 139099 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 54289 49.07% 49.07% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1924 1.74% 50.93% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 16 0.01% 50.94% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 54273 49.06% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 110633 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1865924468000 98.05% 98.05% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 60967000 0.00% 98.05% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 531593000 0.03% 98.08% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 8367000 0.00% 98.08% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 36597541500 1.92% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1903122936500 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.983782 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce 6701 # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei 170162 # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0 59106 40.33% 40.33% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21 131 0.09% 40.42% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22 1925 1.31% 41.73% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30 339 0.23% 41.96% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 85060 58.04% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 146561 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 58406 49.14% 49.14% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21 131 0.11% 49.25% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22 1925 1.62% 50.86% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30 339 0.29% 51.15% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31 58067 48.85% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total 118868 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0 1864755925000 97.88% 97.88% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 61031500 0.00% 97.89% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 543238000 0.03% 97.92% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30 152147500 0.01% 97.92% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 39554606000 2.08% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1905066948000 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0 0.988157 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.663127 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.795354 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31 0.682659 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total 0.811048 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed
system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 225 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir 105 0.07% 0.07% # number of callpals executed
-system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed
-system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 2905 1.98% 2.05% # number of callpals executed
-system.cpu0.kern.callpal::tbi 50 0.03% 2.09% # number of callpals executed
-system.cpu0.kern.callpal::wrent 7 0.00% 2.09% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 132721 90.43% 92.52% # number of callpals executed
-system.cpu0.kern.callpal::rdps 6135 4.18% 96.70% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp 1 0.00% 96.70% # number of callpals executed
-system.cpu0.kern.callpal::wrusp 3 0.00% 96.70% # number of callpals executed
-system.cpu0.kern.callpal::rdusp 9 0.01% 96.71% # number of callpals executed
-system.cpu0.kern.callpal::whami 2 0.00% 96.71% # number of callpals executed
-system.cpu0.kern.callpal::rti 4306 2.93% 99.65% # number of callpals executed
-system.cpu0.kern.callpal::callsys 382 0.26% 99.91% # number of callpals executed
+system.cpu0.kern.callpal::wripir 439 0.28% 0.28% # number of callpals executed
+system.cpu0.kern.callpal::wrmces 1 0.00% 0.28% # number of callpals executed
+system.cpu0.kern.callpal::wrfen 1 0.00% 0.29% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.29% # number of callpals executed
+system.cpu0.kern.callpal::swpctx 3223 2.08% 2.37% # number of callpals executed
+system.cpu0.kern.callpal::tbi 50 0.03% 2.40% # number of callpals executed
+system.cpu0.kern.callpal::wrent 7 0.00% 2.41% # number of callpals executed
+system.cpu0.kern.callpal::swpipl 139738 90.30% 92.70% # number of callpals executed
+system.cpu0.kern.callpal::rdps 6333 4.09% 96.79% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp 1 0.00% 96.79% # number of callpals executed
+system.cpu0.kern.callpal::wrusp 3 0.00% 96.80% # number of callpals executed
+system.cpu0.kern.callpal::rdusp 9 0.01% 96.80% # number of callpals executed
+system.cpu0.kern.callpal::whami 2 0.00% 96.80% # number of callpals executed
+system.cpu0.kern.callpal::rti 4427 2.86% 99.66% # number of callpals executed
+system.cpu0.kern.callpal::callsys 382 0.25% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 146768 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 6331 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1342 # number of protection mode switches
+system.cpu0.kern.callpal::total 154756 # number of callpals executed
+system.cpu0.kern.mode_switch::kernel 6973 # number of protection mode switches
+system.cpu0.kern.mode_switch::user 1341 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
-system.cpu0.kern.mode_good::kernel 1341
-system.cpu0.kern.mode_good::user 1342
+system.cpu0.kern.mode_good::kernel 1340
+system.cpu0.kern.mode_good::user 1341
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.211815 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.192170 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.349668 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1901148119000 99.90% 99.90% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 1974809500 0.10% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total 0.322468 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 1903068198000 99.90% 99.90% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 1998742000 0.10% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 2906 # number of times the context was actually changed
+system.cpu0.kern.swap_context 3224 # number of times the context was actually changed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 3853 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 75635 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 26441 39.26% 39.26% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1922 2.85% 42.12% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 105 0.16% 42.27% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 38878 57.73% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 67346 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 25959 48.22% 48.22% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1922 3.57% 51.78% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 105 0.20% 51.98% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 25854 48.02% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 53840 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1868834322000 98.22% 98.22% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 532397000 0.03% 98.24% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 48831000 0.00% 98.25% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 33374320500 1.75% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1902789870500 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.981771 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce 2621 # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei 71304 # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0 23839 38.11% 38.11% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22 1924 3.08% 41.19% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30 439 0.70% 41.89% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31 36346 58.11% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total 62548 # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0 23162 48.01% 48.01% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22 1924 3.99% 51.99% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30 439 0.91% 52.90% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31 22723 47.10% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total 48248 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0 1872982420000 98.33% 98.33% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 531501500 0.03% 98.36% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30 197949500 0.01% 98.37% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 31046317000 1.63% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1904758188000 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0 0.971601 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.665003 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total 0.799454 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31 0.625186 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total 0.771376 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed
system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed
system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed
system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 101 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed
-system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::swpctx 1334 1.92% 1.95% # number of callpals executed
-system.cpu1.kern.callpal::tbi 3 0.00% 1.95% # number of callpals executed
-system.cpu1.kern.callpal::wrent 7 0.01% 1.96% # number of callpals executed
-system.cpu1.kern.callpal::swpipl 62422 89.83% 91.80% # number of callpals executed
-system.cpu1.kern.callpal::rdps 2621 3.77% 95.57% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp 1 0.00% 95.57% # number of callpals executed
-system.cpu1.kern.callpal::wrusp 4 0.01% 95.57% # number of callpals executed
-system.cpu1.kern.callpal::whami 3 0.00% 95.58% # number of callpals executed
-system.cpu1.kern.callpal::rti 2896 4.17% 99.75% # number of callpals executed
-system.cpu1.kern.callpal::callsys 133 0.19% 99.94% # number of callpals executed
+system.cpu1.kern.callpal::wripir 339 0.52% 0.52% # number of callpals executed
+system.cpu1.kern.callpal::wrmces 1 0.00% 0.53% # number of callpals executed
+system.cpu1.kern.callpal::wrfen 1 0.00% 0.53% # number of callpals executed
+system.cpu1.kern.callpal::swpctx 1674 2.58% 3.11% # number of callpals executed
+system.cpu1.kern.callpal::tbi 3 0.00% 3.11% # number of callpals executed
+system.cpu1.kern.callpal::wrent 7 0.01% 3.13% # number of callpals executed
+system.cpu1.kern.callpal::swpipl 56749 87.55% 90.68% # number of callpals executed
+system.cpu1.kern.callpal::rdps 2425 3.74% 94.42% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp 1 0.00% 94.42% # number of callpals executed
+system.cpu1.kern.callpal::wrusp 4 0.01% 94.42% # number of callpals executed
+system.cpu1.kern.callpal::whami 3 0.00% 94.43% # number of callpals executed
+system.cpu1.kern.callpal::rti 3435 5.30% 99.73% # number of callpals executed
+system.cpu1.kern.callpal::callsys 133 0.21% 99.93% # number of callpals executed
system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 69486 # number of callpals executed
-system.cpu1.kern.mode_switch::kernel 1712 # number of protection mode switches
+system.cpu1.kern.callpal::total 64819 # number of callpals executed
+system.cpu1.kern.mode_switch::kernel 1725 # number of protection mode switches
system.cpu1.kern.mode_switch::user 395 # number of protection mode switches
-system.cpu1.kern.mode_switch::idle 2056 # number of protection mode switches
-system.cpu1.kern.mode_good::kernel 462
+system.cpu1.kern.mode_switch::idle 2719 # number of protection mode switches
+system.cpu1.kern.mode_good::kernel 758
system.cpu1.kern.mode_good::user 395
-system.cpu1.kern.mode_good::idle 67
-system.cpu1.kern.mode_switch_good::kernel 0.269860 # fraction of useful protection mode switches
+system.cpu1.kern.mode_good::idle 363
+system.cpu1.kern.mode_switch_good::kernel 0.439420 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle 0.032588 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total 0.221955 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 38841912000 2.04% 2.04% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 712477500 0.04% 2.08% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1862932175500 97.92% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 1335 # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle 0.133505 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total 0.313288 # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel 6292990000 0.33% 0.33% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user 709362000 0.04% 0.37% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle 1897439269000 99.63% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context 1675 # number of times the context was actually changed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 1.860009 # Number of seconds simulated
-sim_ticks 1860008936000 # Number of ticks simulated
-final_tick 1860008936000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.859039 # Number of seconds simulated
+sim_ticks 1859038679000 # Number of ticks simulated
+final_tick 1859038679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 106543 # Simulator instruction rate (inst/s)
-host_op_rate 106543 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3740252336 # Simulator tick rate (ticks/s)
-host_mem_usage 320492 # Number of bytes of host memory used
-host_seconds 497.30 # Real time elapsed on the host
-sim_insts 52983264 # Number of instructions simulated
-sim_ops 52983264 # Number of ops (including micro ops) simulated
+host_inst_rate 164972 # Simulator instruction rate (inst/s)
+host_op_rate 164972 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5794497034 # Simulator tick rate (ticks/s)
+host_mem_usage 371088 # Number of bytes of host memory used
+host_seconds 320.83 # Real time elapsed on the host
+sim_insts 52927600 # Number of instructions simulated
+sim_ops 52927600 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 968512 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24900352 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 968256 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24892608 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 25869824 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 968512 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 968512 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4866048 # Number of bytes written to this memory
+system.physmem.bytes_read::total 25861824 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 968256 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 968256 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4860032 # Number of bytes written to this memory
system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7525376 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 15133 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 389068 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 7519360 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 15129 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 388947 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 404216 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 76032 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 404091 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 75938 # Number of write requests responded to by this memory
system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 117584 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 520703 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 13387222 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 117490 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 520837 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 13390043 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 13908441 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 520703 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 520703 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2616142 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::tsunami.ide 1429739 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4045882 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2616142 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 520703 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 13387222 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1430255 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 17954322 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 404216 # Number of read requests accepted
-system.physmem.writeReqs 117584 # Number of write requests accepted
-system.physmem.readBursts 404216 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 117584 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 25858752 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 11072 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7523328 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 25869824 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 7525376 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 173 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_read::total 13911396 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 520837 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 520837 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2614272 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::tsunami.ide 1430486 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4044757 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2614272 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 520837 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 13390043 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1431002 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 17956154 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 404091 # Number of read requests accepted
+system.physmem.writeReqs 117490 # Number of write requests accepted
+system.physmem.readBursts 404091 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 117490 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 25850368 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 11456 # Total number of bytes read from write queue
+system.physmem.bytesWritten 7517888 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 25861824 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 7519360 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 179 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 213 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 25622 # Per bank write bursts
-system.physmem.perBankRdBursts::1 25451 # Per bank write bursts
-system.physmem.perBankRdBursts::2 25608 # Per bank write bursts
-system.physmem.perBankRdBursts::3 25528 # Per bank write bursts
-system.physmem.perBankRdBursts::4 25399 # Per bank write bursts
-system.physmem.perBankRdBursts::5 24757 # Per bank write bursts
-system.physmem.perBankRdBursts::6 24940 # Per bank write bursts
-system.physmem.perBankRdBursts::7 25074 # Per bank write bursts
-system.physmem.perBankRdBursts::8 24966 # Per bank write bursts
-system.physmem.perBankRdBursts::9 25053 # Per bank write bursts
-system.physmem.perBankRdBursts::10 25586 # Per bank write bursts
-system.physmem.perBankRdBursts::11 24884 # Per bank write bursts
-system.physmem.perBankRdBursts::12 24485 # Per bank write bursts
-system.physmem.perBankRdBursts::13 25285 # Per bank write bursts
-system.physmem.perBankRdBursts::14 25789 # Per bank write bursts
-system.physmem.perBankRdBursts::15 25616 # Per bank write bursts
-system.physmem.perBankWrBursts::0 7925 # Per bank write bursts
-system.physmem.perBankWrBursts::1 7509 # Per bank write bursts
-system.physmem.perBankWrBursts::2 7974 # Per bank write bursts
-system.physmem.perBankWrBursts::3 7525 # Per bank write bursts
-system.physmem.perBankWrBursts::4 7335 # Per bank write bursts
-system.physmem.perBankWrBursts::5 6682 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6769 # Per bank write bursts
-system.physmem.perBankWrBursts::7 6701 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7135 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6719 # Per bank write bursts
-system.physmem.perBankWrBursts::10 7431 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6970 # Per bank write bursts
-system.physmem.perBankWrBursts::12 7113 # Per bank write bursts
-system.physmem.perBankWrBursts::13 7882 # Per bank write bursts
-system.physmem.perBankWrBursts::14 8065 # Per bank write bursts
-system.physmem.perBankWrBursts::15 7817 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 193 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 25747 # Per bank write bursts
+system.physmem.perBankRdBursts::1 25572 # Per bank write bursts
+system.physmem.perBankRdBursts::2 25523 # Per bank write bursts
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+system.physmem.perBankRdBursts::4 25392 # Per bank write bursts
+system.physmem.perBankRdBursts::5 24811 # Per bank write bursts
+system.physmem.perBankRdBursts::6 25029 # Per bank write bursts
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+system.physmem.perBankRdBursts::8 24968 # Per bank write bursts
+system.physmem.perBankRdBursts::9 25052 # Per bank write bursts
+system.physmem.perBankRdBursts::10 25439 # Per bank write bursts
+system.physmem.perBankRdBursts::11 24779 # Per bank write bursts
+system.physmem.perBankRdBursts::12 24568 # Per bank write bursts
+system.physmem.perBankRdBursts::13 25250 # Per bank write bursts
+system.physmem.perBankRdBursts::14 25688 # Per bank write bursts
+system.physmem.perBankRdBursts::15 25605 # Per bank write bursts
+system.physmem.perBankWrBursts::0 8041 # Per bank write bursts
+system.physmem.perBankWrBursts::1 7603 # Per bank write bursts
+system.physmem.perBankWrBursts::2 7894 # Per bank write bursts
+system.physmem.perBankWrBursts::3 7385 # Per bank write bursts
+system.physmem.perBankWrBursts::4 7327 # Per bank write bursts
+system.physmem.perBankWrBursts::5 6730 # Per bank write bursts
+system.physmem.perBankWrBursts::6 6858 # Per bank write bursts
+system.physmem.perBankWrBursts::7 6765 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7133 # Per bank write bursts
+system.physmem.perBankWrBursts::9 6722 # Per bank write bursts
+system.physmem.perBankWrBursts::10 7301 # Per bank write bursts
+system.physmem.perBankWrBursts::11 6871 # Per bank write bursts
+system.physmem.perBankWrBursts::12 7190 # Per bank write bursts
+system.physmem.perBankWrBursts::13 7853 # Per bank write bursts
+system.physmem.perBankWrBursts::14 7964 # Per bank write bursts
+system.physmem.perBankWrBursts::15 7830 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 9 # Number of times write queue was full causing retry
-system.physmem.totGap 1860003602000 # Total gap between requests
+system.physmem.totGap 1859033424000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 404216 # Read request sizes (log2)
+system.physmem.readPktSize::6 404091 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 117584 # Write request sizes (log2)
+system.physmem.writePktSize::6 117490 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 315071 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 37801 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 42911 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 8183 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::16 2253 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 3103 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::28 7965 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::34 134 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 133 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 139 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 134 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 133 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 119 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 123 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 116 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 136 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 136 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 93 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 78 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 66 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 71 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 71 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 71 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 51 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 47 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 61090 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 546.434703 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 336.353089 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 417.871718 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 13232 21.66% 21.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 10443 17.09% 38.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 4742 7.76% 46.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2710 4.44% 50.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2446 4.00% 54.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1597 2.61% 57.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1401 2.29% 59.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1610 2.64% 62.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 22909 37.50% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 61090 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5256 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 76.868151 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 2912.510758 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191 5253 99.94% 99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15 1544 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 2141 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 3054 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 4174 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::22 8408 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::24 9005 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 8758 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 8976 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 7859 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 7939 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 6211 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 6103 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::36 154 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 160 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 113 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 117 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 141 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 120 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 129 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 155 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 146 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 137 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 88 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 88 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 84 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 87 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 95 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 92 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 84 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 92 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 82 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 56 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 61280 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 544.521149 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 334.160448 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 418.029082 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 13483 22.00% 22.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 10372 16.93% 38.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 4758 7.76% 46.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2785 4.54% 51.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2293 3.74% 54.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1673 2.73% 57.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1477 2.41% 60.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1592 2.60% 62.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 22847 37.28% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 61280 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 5232 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 77.198394 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 2919.153555 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191 5229 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5256 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5256 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 22.365297 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 19.103318 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 20.103778 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 4494 85.50% 85.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 124 2.36% 87.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 9 0.17% 88.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 232 4.41% 92.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 40 0.76% 93.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 6 0.11% 93.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 12 0.23% 93.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 3 0.06% 93.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 27 0.51% 94.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 3 0.06% 94.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 1 0.02% 94.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 1 0.02% 94.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 15 0.29% 94.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 5 0.10% 94.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 3 0.06% 94.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 31 0.59% 95.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 8 0.15% 95.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 4 0.08% 95.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 5 0.10% 95.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 188 3.58% 99.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 2 0.04% 99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 5 0.10% 99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 3 0.06% 99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 11 0.21% 99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 3 0.06% 99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 1 0.02% 99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 7 0.13% 99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 5 0.10% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151 1 0.02% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 2 0.04% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167 2 0.04% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227 2 0.04% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5256 # Writes before turning the bus around for reads
-system.physmem.totQLat 3626109250 # Total ticks spent queuing
-system.physmem.totMemAccLat 11201915500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2020215000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 8974.56 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 5232 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 5232 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 22.451644 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 19.067800 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 21.155033 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 4469 85.42% 85.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 138 2.64% 88.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 12 0.23% 88.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 232 4.43% 92.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 44 0.84% 93.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 2 0.04% 93.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 5 0.10% 93.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 10 0.19% 93.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 17 0.32% 94.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 2 0.04% 94.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 1 0.02% 94.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 2 0.04% 94.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 7 0.13% 94.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 3 0.06% 94.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 4 0.08% 94.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 1 0.02% 94.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 28 0.54% 95.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 15 0.29% 95.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 15 0.29% 95.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 171 3.27% 98.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 6 0.11% 99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 1 0.02% 99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 2 0.04% 99.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 2 0.04% 99.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 1 0.02% 99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 5 0.10% 99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 1 0.02% 99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 6 0.11% 99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 4 0.08% 99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 11 0.21% 99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151 1 0.02% 99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155 2 0.04% 99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 1 0.02% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163 1 0.02% 99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175 1 0.02% 99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 1 0.02% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187 1 0.02% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227 7 0.13% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 5232 # Writes before turning the bus around for reads
+system.physmem.totQLat 3681492750 # Total ticks spent queuing
+system.physmem.totMemAccLat 11254842750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2019560000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 9114.59 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 27724.56 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 13.90 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 27864.59 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 13.91 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 13.91 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 4.05 # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.14 # Data bus utilization in percentage
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.48 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.10 # Average write queue length when enqueuing
-system.physmem.readRowHits 364992 # Number of row buffer hits during reads
-system.physmem.writeRowHits 95512 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 90.33 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 81.23 # Row buffer hit rate for writes
-system.physmem.avgGap 3564591.03 # Average gap between requests
-system.physmem.pageHitRate 88.28 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 1761923491250 # Time in different power states
-system.physmem.memoryStateTime::REF 62109580000 # Time in different power states
+system.physmem.avgRdQLen 1.92 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.45 # Average write queue length when enqueuing
+system.physmem.readRowHits 364830 # Number of row buffer hits during reads
+system.physmem.writeRowHits 95269 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 90.32 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 81.09 # Row buffer hit rate for writes
+system.physmem.avgGap 3564227.65 # Average gap between requests
+system.physmem.pageHitRate 88.24 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 1761056207000 # Time in different power states
+system.physmem.memoryStateTime::REF 62077340000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 35970256750 # Time in different power states
+system.physmem.memoryStateTime::ACT 35903990500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 17983494 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 296097 # Transaction distribution
-system.membus.trans_dist::ReadResp 296008 # Transaction distribution
-system.membus.trans_dist::WriteReq 9598 # Transaction distribution
-system.membus.trans_dist::WriteResp 9598 # Transaction distribution
-system.membus.trans_dist::Writeback 76032 # Transaction distribution
+system.membus.trans_dist::ReadReq 296046 # Transaction distribution
+system.membus.trans_dist::ReadResp 295957 # Transaction distribution
+system.membus.trans_dist::WriteReq 9597 # Transaction distribution
+system.membus.trans_dist::WriteResp 9597 # Transaction distribution
+system.membus.trans_dist::Writeback 75938 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 207 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 213 # Transaction distribution
-system.membus.trans_dist::ReadExReq 115296 # Transaction distribution
-system.membus.trans_dist::ReadExResp 115296 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 188 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 5 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 193 # Transaction distribution
+system.membus.trans_dist::ReadExReq 115222 # Transaction distribution
+system.membus.trans_dist::ReadExResp 115222 # Transaction distribution
system.membus.trans_dist::BadAddressError 89 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884860 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884476 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 178 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 918094 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917708 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1001386 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30734912 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30779060 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 33439348 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 33439348 # Total data (bytes)
-system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 29284000 # Layer occupancy (ticks)
+system.membus.pkt_count::total 1001000 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30720896 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30765036 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 33425324 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 158 # Total snoops (count)
+system.membus.snoop_fanout::samples 522030 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 522030 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 522030 # Request fanout histogram
+system.membus.reqLayer0.occupancy 31457000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 1484965250 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 1484421249 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 112000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 110500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3755505039 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 3754388311 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.respLayer2.occupancy 43151211 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 41685 # number of replacements
-system.iocache.tags.tagsinuse 1.268186 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 1.260487 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 1709354954000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide 1.268186 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide 0.079262 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.079262 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 1709355301000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide 1.260487 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide 0.078780 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.078780 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 376037 # Number of tag accesses
-system.iocache.tags.data_accesses 376037 # Number of data accesses
+system.iocache.tags.tag_accesses 376213 # Number of tag accesses
+system.iocache.tags.data_accesses 376213 # Number of data accesses
system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::tsunami.ide 64 # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total 64 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::tsunami.ide 86 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total 86 # number of WriteInvalidateReq misses
system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
system.iocache.demand_misses::total 173 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41616 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total 41616 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41638 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 41638 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.001538 # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total 0.001538 # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.002065 # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total 0.002065 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2528134047 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2528134047 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2529714027 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2529714027 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.998462 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.998462 # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.997935 # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.997935 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60842.656118 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60842.656118 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60880.680280 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60880.680280 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 17833670 # Number of BP lookups
-system.cpu.branchPred.condPredicted 15506350 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 381114 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 12104225 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 5926115 # Number of BTB hits
+system.cpu.branchPred.lookups 17804968 # Number of BP lookups
+system.cpu.branchPred.condPredicted 15499600 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 379466 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 11923628 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 5932721 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 48.959062 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 921355 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 21398 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 49.756005 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 914118 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 21281 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 10317598 # DTB read hits
-system.cpu.dtb.read_misses 42841 # DTB read misses
-system.cpu.dtb.read_acv 498 # DTB read access violations
-system.cpu.dtb.read_accesses 968680 # DTB read accesses
-system.cpu.dtb.write_hits 6661505 # DTB write hits
-system.cpu.dtb.write_misses 9470 # DTB write misses
-system.cpu.dtb.write_acv 409 # DTB write access violations
-system.cpu.dtb.write_accesses 342844 # DTB write accesses
-system.cpu.dtb.data_hits 16979103 # DTB hits
-system.cpu.dtb.data_misses 52311 # DTB misses
-system.cpu.dtb.data_acv 907 # DTB access violations
-system.cpu.dtb.data_accesses 1311524 # DTB accesses
-system.cpu.itb.fetch_hits 1772041 # ITB hits
-system.cpu.itb.fetch_misses 34420 # ITB misses
-system.cpu.itb.fetch_acv 658 # ITB acv
-system.cpu.itb.fetch_accesses 1806461 # ITB accesses
+system.cpu.dtb.read_hits 10302215 # DTB read hits
+system.cpu.dtb.read_misses 41309 # DTB read misses
+system.cpu.dtb.read_acv 513 # DTB read access violations
+system.cpu.dtb.read_accesses 965594 # DTB read accesses
+system.cpu.dtb.write_hits 6646492 # DTB write hits
+system.cpu.dtb.write_misses 9371 # DTB write misses
+system.cpu.dtb.write_acv 419 # DTB write access violations
+system.cpu.dtb.write_accesses 342338 # DTB write accesses
+system.cpu.dtb.data_hits 16948707 # DTB hits
+system.cpu.dtb.data_misses 50680 # DTB misses
+system.cpu.dtb.data_acv 932 # DTB access violations
+system.cpu.dtb.data_accesses 1307932 # DTB accesses
+system.cpu.itb.fetch_hits 1774610 # ITB hits
+system.cpu.itb.fetch_misses 34401 # ITB misses
+system.cpu.itb.fetch_acv 653 # ITB acv
+system.cpu.itb.fetch_accesses 1809011 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.numCycles 118354133 # number of cpu cycles simulated
+system.cpu.numCycles 118301061 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 29610053 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 78304025 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 17833670 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 6847470 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 80574615 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1256858 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 1099 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 26263 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1650622 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 440507 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 235 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 9057340 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 272482 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 112931823 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.693374 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.013486 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 29562966 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 78094807 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 17804968 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 6846839 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 80553195 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1252096 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 1416 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 27926 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1649882 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 450417 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 232 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 9025532 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 274121 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 112872082 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.691888 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.011514 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 98319716 87.06% 87.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 938849 0.83% 87.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1975725 1.75% 89.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 910849 0.81% 90.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2798510 2.48% 92.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 647409 0.57% 93.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 732146 0.65% 94.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1011734 0.90% 95.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 5596885 4.96% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 98296528 87.09% 87.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 933530 0.83% 87.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1975700 1.75% 89.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 908755 0.81% 90.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2800334 2.48% 92.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 638924 0.57% 93.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 725896 0.64% 94.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1007040 0.89% 95.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 5585375 4.95% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 112931823 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.150681 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.661608 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 24101711 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 76820135 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 9519710 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1904377 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 585889 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 591731 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 42945 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 68430953 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 130896 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 585889 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 25024532 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 47243324 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 20763433 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 10413926 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 8900717 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 65988448 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 204336 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 2037147 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 141186 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 4759131 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 44017538 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 79991288 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 79809724 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 169111 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 38182266 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 5835264 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1692739 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 242112 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13540611 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 10451547 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 6960595 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1482211 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1061862 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 58727790 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2141622 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 57666213 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 56106 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 7541795 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 3548748 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1480432 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 112931823 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.510629 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.253101 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 112872082 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.150506 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.660136 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 24068860 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 76820836 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 9500551 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1898196 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 583638 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 588301 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 42850 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 68299285 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 133126 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 583638 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 24994916 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 47249741 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 20742683 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 10385328 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 8915774 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 65865702 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 202022 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 2036806 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 141544 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 4770005 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 43944287 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 79812474 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 79631676 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 168345 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 38137411 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 5806868 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1690855 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 241233 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 13548292 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 10425085 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 6927485 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1490397 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1054253 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 58626057 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2139161 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 57592696 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 51229 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 7502337 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 3486338 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1478017 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 112872082 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.510247 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.252928 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 89418441 79.18% 79.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 10028401 8.88% 88.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 4312192 3.82% 91.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 2973812 2.63% 94.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 3078524 2.73% 97.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 1589541 1.41% 98.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1010242 0.89% 99.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 396621 0.35% 99.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 124049 0.11% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 89394835 79.20% 79.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 10016384 8.87% 88.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 4304507 3.81% 91.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 2950730 2.61% 94.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 3082787 2.73% 97.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 1592384 1.41% 98.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1013037 0.90% 99.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 395526 0.35% 99.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 121892 0.11% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 112931823 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 112872082 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 207021 18.24% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 552834 48.70% 66.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 375297 33.06% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 212963 18.82% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 545078 48.16% 66.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 373836 33.03% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 39135351 67.87% 67.88% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 61883 0.11% 67.99% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.99% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 38374 0.07% 68.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 10730394 18.61% 86.67% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 6740242 11.69% 98.35% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 949047 1.65% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 39097776 67.89% 67.90% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 61804 0.11% 68.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 38376 0.07% 68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 10712581 18.60% 86.68% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 6722276 11.67% 98.35% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess 948961 1.65% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 57666213 # Type of FU issued
-system.cpu.iq.rate 0.487234 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1135152 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.019685 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 228740415 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 68094123 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 55977641 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 715091 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 336647 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 329707 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 58410087 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 383992 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 639401 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 57592696 # Type of FU issued
+system.cpu.iq.rate 0.486832 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1131877 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.019653 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 228528169 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 67952558 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 55916727 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 712410 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 334609 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 328997 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 58334880 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 382407 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 639606 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1358213 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 3975 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 20004 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 581979 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1340629 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 4088 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 20047 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 553798 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 18257 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 542602 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 18287 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 539247 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 585889 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 44309531 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 608680 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 64580146 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 145680 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 10451547 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 6960595 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1891521 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 42330 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 362520 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 20004 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 191994 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 411566 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 603560 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 57078103 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 10388088 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 588109 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 583638 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 44307486 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 616008 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 64468948 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 145079 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 10425085 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 6927485 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1890835 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 42893 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 369751 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 20047 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 190429 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 410127 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 600556 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 57009373 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 10371242 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 583322 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 3710734 # number of nop insts executed
-system.cpu.iew.exec_refs 17074164 # number of memory reference insts executed
-system.cpu.iew.exec_branches 8987700 # Number of branches executed
-system.cpu.iew.exec_stores 6686076 # Number of stores executed
-system.cpu.iew.exec_rate 0.482265 # Inst execution rate
-system.cpu.iew.wb_sent 56446206 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 56307348 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 28961590 # num instructions producing a value
-system.cpu.iew.wb_consumers 40346871 # num instructions consuming a value
+system.cpu.iew.exec_nop 3703730 # number of nop insts executed
+system.cpu.iew.exec_refs 17042240 # number of memory reference insts executed
+system.cpu.iew.exec_branches 8981920 # Number of branches executed
+system.cpu.iew.exec_stores 6670998 # Number of stores executed
+system.cpu.iew.exec_rate 0.481901 # Inst execution rate
+system.cpu.iew.wb_sent 56380366 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 56245724 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 28936691 # num instructions producing a value
+system.cpu.iew.wb_consumers 40310167 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.475753 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.717815 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.475446 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.717851 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 8290413 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 661190 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 549582 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 111493844 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.503831 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.456125 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 8239182 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 661144 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 548042 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 111437316 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.503568 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.455315 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 91848046 82.38% 82.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 7822356 7.02% 89.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4123652 3.70% 93.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2157766 1.94% 95.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1851713 1.66% 96.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 614180 0.55% 97.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 473259 0.42% 97.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 509141 0.46% 98.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2093731 1.88% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 91810154 82.39% 82.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 7802563 7.00% 89.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 4132031 3.71% 93.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2155493 1.93% 95.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1853584 1.66% 96.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 616181 0.55% 97.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 467348 0.42% 97.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 515869 0.46% 98.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2084093 1.87% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 111493844 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 56174099 # Number of instructions committed
-system.cpu.commit.committedOps 56174099 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 111437316 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 56116260 # Number of instructions committed
+system.cpu.commit.committedOps 56116260 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 15471950 # Number of memory references committed
-system.cpu.commit.loads 9093334 # Number of loads committed
-system.cpu.commit.membars 226345 # Number of memory barriers committed
-system.cpu.commit.branches 8441019 # Number of branches committed
-system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 52023449 # Number of committed integer instructions.
-system.cpu.commit.function_calls 740634 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 3198108 5.69% 5.69% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 36220301 64.48% 70.17% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 60671 0.11% 70.28% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 38087 0.07% 70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction
+system.cpu.commit.refs 15458143 # Number of memory references committed
+system.cpu.commit.loads 9084456 # Number of loads committed
+system.cpu.commit.membars 226334 # Number of memory barriers committed
+system.cpu.commit.branches 8434463 # Number of branches committed
+system.cpu.commit.fp_insts 324518 # Number of committed floating point instructions.
+system.cpu.commit.int_insts 51967854 # Number of committed integer instructions.
+system.cpu.commit.function_calls 739911 # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass 3195933 5.70% 5.70% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 36178550 64.47% 70.17% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 60663 0.11% 70.27% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.27% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd 38089 0.07% 70.34% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.34% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.34% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.34% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 9319679 16.59% 86.94% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 6384570 11.37% 98.31% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess 949047 1.69% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 9310790 16.59% 86.94% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 6379639 11.37% 98.31% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess 948960 1.69% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 56174099 # Class of committed instruction
-system.cpu.commit.bw_lim_events 2093731 # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total 56116260 # Class of committed instruction
+system.cpu.commit.bw_lim_events 2084093 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 173614429 # The number of ROB reads
-system.cpu.rob.rob_writes 130369620 # The number of ROB writes
-system.cpu.timesIdled 576556 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 5422310 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 3601657297 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 52983264 # Number of Instructions Simulated
-system.cpu.committedOps 52983264 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 2.233802 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.233802 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.447667 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.447667 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 74755796 # number of integer regfile reads
-system.cpu.int_regfile_writes 40630218 # number of integer regfile writes
-system.cpu.fp_regfile_reads 167440 # number of floating regfile reads
-system.cpu.fp_regfile_writes 167913 # number of floating regfile writes
-system.cpu.misc_regfile_reads 2030226 # number of misc regfile reads
-system.cpu.misc_regfile_writes 939431 # number of misc regfile writes
+system.cpu.rob.rob_reads 173459156 # The number of ROB reads
+system.cpu.rob.rob_writes 130141826 # The number of ROB writes
+system.cpu.timesIdled 576115 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 5428979 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 3599776298 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 52927600 # Number of Instructions Simulated
+system.cpu.committedOps 52927600 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 2.235149 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.235149 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.447398 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.447398 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 74648651 # number of integer regfile reads
+system.cpu.int_regfile_writes 40584029 # number of integer regfile writes
+system.cpu.fp_regfile_reads 166982 # number of floating regfile reads
+system.cpu.fp_regfile_writes 167600 # number of floating regfile writes
+system.cpu.misc_regfile_reads 2029015 # number of misc regfile reads
+system.cpu.misc_regfile_writes 939371 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.iobus.throughput 1454701 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
-system.iobus.trans_dist::WriteReq 51086 # Transaction distribution
-system.iobus.trans_dist::WriteResp 51150 # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq 64 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::WriteReq 51063 # Transaction distribution
+system.iobus.trans_dist::WriteResp 51149 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 86 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 33054 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 2705756 # Total data (bytes)
-system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks)
+system.iobus.pkt_count::total 116504 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20200 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 44140 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2705748 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 4661000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer29.occupancy 374510641 # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy 374547621 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 42014789 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.throughput 114654995 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 2149538 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2149432 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 845214 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 2147499 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2147393 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 842679 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41561 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 94 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 122 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 302210 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 302210 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 81 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 26 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 107 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 301934 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 301934 # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError 89 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2074480 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3693292 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 5767772 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66377344 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144210036 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 210587380 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 210577396 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 2681920 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 2503268997 # Layer occupancy (ticks)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2074254 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3686339 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 5760593 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66370688 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143907436 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 210278124 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 42060 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 3326850 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.012545 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.111298 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 3285116 98.75% 98.75% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 41734 1.25% 100.00% # Request fanout histogram
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system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58618.183562 # average overall mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu.dcache.tags.warmup_cycle 25219000 # Cycle when the warmup percentage was hit.
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-system.cpu.dcache.avg_blocked_cycles::no_targets 98.857143 # average number of cycles each access was blocked
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+system.cpu.dcache.overall_avg_miss_latency::total 31525.310365 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 3999248 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 1376 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 180044 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 22 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.212615 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 62.545455 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 845214 # number of writebacks
-system.cpu.dcache.writebacks::total 845214 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 683673 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 683673 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664672 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1664672 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5215 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 5215 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 2348345 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 2348345 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 2348345 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 2348345 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1097777 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1097777 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291406 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 291406 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18220 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 18220 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 28 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 28 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1389183 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1389183 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1389183 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1389183 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27531600277 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 27531600277 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11750999106 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 11750999106 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 207629251 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 207629251 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 383994 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 383994 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39282599383 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 39282599383 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39282599383 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 39282599383 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423287000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423287000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997974498 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997974498 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421261498 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421261498 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120953 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120953 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047397 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047397 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086828 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086828 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091248 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.091248 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091248 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.091248 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25079.410734 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25079.410734 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40325.178981 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40325.178981 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11395.677881 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11395.677881 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13714.071429 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13714.071429 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28277.483516 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28277.483516 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28277.483516 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28277.483516 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 842679 # number of writebacks
+system.cpu.dcache.writebacks::total 842679 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 680758 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 680758 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664340 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1664340 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5292 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 5292 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 2345098 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 2345098 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 2345098 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 2345098 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1096091 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1096091 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291116 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 291116 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17991 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 17991 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 26 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 26 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1387207 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1387207 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1387207 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1387207 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27515724784 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 27515724784 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11792803134 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 11792803134 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204517750 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204517750 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 349995 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 349995 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39308527918 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 39308527918 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39308527918 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 39308527918 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423597000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423597000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1999614498 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1999614498 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3423211498 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 3423211498 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120930 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120930 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047388 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047388 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085843 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085843 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000121 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000121 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.091221 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.091221 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25103.503983 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25103.503983 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40508.948783 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40508.948783 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11367.781113 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11367.781113 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13461.346154 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13461.346154 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28336.454414 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28336.454414 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28336.454414 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28336.454414 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei 211008 # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei 210986 # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0 74656 40.97% 40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31 105564 57.93% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total 182238 # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31 105550 57.93% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total 182216 # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0 73289 49.32% 49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1818262027500 97.76% 97.76% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21 61927000 0.00% 97.76% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22 526143500 0.03% 97.79% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 41157993000 2.21% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1860008091000 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31 73289 49.32% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total 148588 # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0 1817327743500 97.76% 97.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21 61881000 0.00% 97.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22 521765000 0.03% 97.79% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 41126450000 2.21% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total 1859037839500 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0 0.981689 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31 0.694328 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total 0.815434 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31 0.694353 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total 0.815450 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx 4177 2.18% 2.18% # number of callpals executed
+system.cpu.kern.callpal::swpctx 4178 2.18% 2.18% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl 175121 91.22% 93.43% # number of callpals executed
-system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed
+system.cpu.kern.callpal::swpipl 175101 91.22% 93.43% # number of callpals executed
+system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed
system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed
-system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed
+system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.callpal::total 191967 # number of callpals executed
-system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches
+system.cpu.kern.callpal::total 191946 # number of callpals executed
+system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches
system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
-system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches
+system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
system.cpu.kern.mode_good::kernel 1910
system.cpu.kern.mode_good::user 1740
system.cpu.kern.mode_good::idle 170
-system.cpu.kern.mode_switch_good::kernel 0.326496 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel 0.326440 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.394302 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 29080060000 1.56% 1.56% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 2655672500 0.14% 1.71% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1828272350500 98.29% 100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context 4178 # number of times the context was actually changed
+system.cpu.kern.mode_ticks::kernel 29097785000 1.57% 1.57% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user 2655967500 0.14% 1.71% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle 1827284079000 98.29% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context 4179 # number of times the context was actually changed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
sim_seconds 1.841612 # Number of seconds simulated
-sim_ticks 1841612285000 # Number of ticks simulated
-final_tick 1841612285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 1841612450000 # Number of ticks simulated
+final_tick 1841612450000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 168459 # Simulator instruction rate (inst/s)
-host_op_rate 168459 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4750760669 # Simulator tick rate (ticks/s)
-host_mem_usage 319468 # Number of bytes of host memory used
-host_seconds 387.65 # Real time elapsed on the host
-sim_insts 65302548 # Number of instructions simulated
-sim_ops 65302548 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
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+system.physmem.wrQLenPdf::49 36 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 33 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 34 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 32 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 30 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 30 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 30 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 29 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 28 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 25 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 17 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 11 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 21530 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 386.758569 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 220.447203 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 381.120515 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 7019 32.60% 32.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 4847 22.51% 55.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 1849 8.59% 63.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 1051 4.88% 68.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 911 4.23% 72.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 506 2.35% 75.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 375 1.74% 76.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 418 1.94% 78.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 4554 21.15% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 21530 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 2040 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 40.873529 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 1027.655163 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 2038 99.90% 99.90% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 6 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 21619 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 384.870346 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 218.868855 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 380.663334 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 7130 32.98% 32.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 4830 22.34% 55.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 1852 8.57% 63.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 1050 4.86% 68.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 916 4.24% 72.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 498 2.30% 75.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 396 1.83% 77.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 403 1.86% 78.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 4544 21.02% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 21619 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 2039 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 40.867092 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 1027.907354 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 2037 99.90% 99.90% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103 1 0.05% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 2040 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 2040 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 22.900490 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.614282 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 22.575456 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3 33 1.62% 1.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7 7 0.34% 1.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11 1 0.05% 2.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15 5 0.25% 2.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 1695 83.09% 85.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 37 1.81% 87.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 5 0.25% 87.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 107 5.25% 92.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 7 0.34% 92.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 2 0.10% 93.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 1 0.05% 93.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 3 0.15% 93.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 8 0.39% 93.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 1 0.05% 93.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 1 0.05% 93.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 2 0.10% 93.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 1 0.05% 93.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 2 0.10% 94.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 2 0.10% 94.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 8 0.39% 94.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 3 0.15% 94.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 3 0.15% 94.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 2 0.10% 94.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 78 3.82% 98.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 1 0.05% 98.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 2 0.10% 98.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 1 0.05% 98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 7 0.34% 99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 2 0.10% 99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 3 0.15% 99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 1 0.05% 99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 3 0.15% 99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151 1 0.05% 99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155 1 0.05% 99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227 4 0.20% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 2040 # Writes before turning the bus around for reads
-system.physmem.totQLat 869064750 # Total ticks spent queuing
-system.physmem.totMemAccLat 2432646000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 416955000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10421.57 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 2039 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 2039 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 22.888180 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.579378 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 22.470267 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-7 42 2.06% 2.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-15 4 0.20% 2.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23 1722 84.45% 86.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31 114 5.59% 92.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39 19 0.93% 93.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47 3 0.15% 93.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55 5 0.25% 93.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63 2 0.10% 93.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71 2 0.10% 93.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79 3 0.15% 93.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87 15 0.74% 94.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95 5 0.25% 94.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103 79 3.87% 98.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119 5 0.25% 99.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127 1 0.05% 99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135 5 0.25% 99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143 5 0.25% 99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151 3 0.15% 99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159 1 0.05% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183 1 0.05% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231 2 0.10% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263 1 0.05% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 2039 # Writes before turning the bus around for reads
+system.physmem.totQLat 882163500 # Total ticks spent queuing
+system.physmem.totMemAccLat 2444769750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 416695000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 10585.24 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29171.57 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 29335.24 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.62 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 8.28 # Average write queue length when enqueuing
-system.physmem.readRowHits 71609 # Number of row buffer hits during reads
-system.physmem.writeRowHits 36969 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 85.87 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 79.09 # Row buffer hit rate for writes
-system.physmem.avgGap 14138993.30 # Average gap between requests
-system.physmem.pageHitRate 83.44 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 1766589196000 # Time in different power states
+system.physmem.avgWrQLen 8.38 # Average write queue length when enqueuing
+system.physmem.readRowHits 71513 # Number of row buffer hits during reads
+system.physmem.writeRowHits 36876 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 85.81 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 78.97 # Row buffer hit rate for writes
+system.physmem.avgGap 14150190.45 # Average gap between requests
+system.physmem.pageHitRate 83.35 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 1766563042250 # Time in different power states
system.physmem.memoryStateTime::REF 61495460000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 13527240250 # Time in different power states
+system.physmem.memoryStateTime::ACT 13553394000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 18112095 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 44765 # Transaction distribution
-system.membus.trans_dist::ReadResp 44760 # Transaction distribution
-system.membus.trans_dist::WriteReq 3528 # Transaction distribution
-system.membus.trans_dist::WriteResp 3528 # Transaction distribution
-system.membus.trans_dist::Writeback 29460 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 17280 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 17280 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 50 # Transaction distribution
+system.membus.trans_dist::ReadReq 294949 # Transaction distribution
+system.membus.trans_dist::ReadResp 294942 # Transaction distribution
+system.membus.trans_dist::WriteReq 9810 # Transaction distribution
+system.membus.trans_dist::WriteResp 9810 # Transaction distribution
+system.membus.trans_dist::Writeback 75403 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 148 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 52 # Transaction distribution
-system.membus.trans_dist::ReadExReq 41656 # Transaction distribution
-system.membus.trans_dist::ReadExResp 41656 # Transaction distribution
-system.membus.trans_dist::BadAddressError 5 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 12900 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 196412 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 10 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 209322 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 34645 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 34645 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 243967 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15792 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7224576 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total 7240368 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 1106880 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 1106880 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 8347248 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 33351936 # Total data (bytes)
-system.membus.snoop_data_through_bus 3520 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 11434500 # Layer occupancy (ticks)
+system.membus.trans_dist::UpgradeResp 150 # Transaction distribution
+system.membus.trans_dist::ReadExReq 115716 # Transaction distribution
+system.membus.trans_dist::ReadExResp 115716 # Transaction distribution
+system.membus.trans_dist::BadAddressError 7 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 882385 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 14 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 916307 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83395 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 83395 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 999702 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30639616 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 30685184 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2666880 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2666880 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 33352064 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 55 # Total snoops (count)
+system.membus.snoop_fanout::samples 520629 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 520629 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 520629 # Request fanout histogram
+system.membus.reqLayer0.occupancy 11839500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 517398750 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 516853000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 6500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 783386948 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 782820695 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 17911250 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 17912499 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 337577 # number of replacements
-system.l2c.tags.tagsinuse 65421.096735 # Cycle average of tags in use
-system.l2c.tags.total_refs 2486717 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 402739 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 6.174513 # Average number of references to valid blocks.
+system.l2c.tags.replacements 337573 # number of replacements
+system.l2c.tags.tagsinuse 65418.651212 # Cycle average of tags in use
+system.l2c.tags.total_refs 2486411 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 402735 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 6.173814 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 54723.362784 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 2335.935658 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 2702.236553 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 571.913553 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 605.884543 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 2280.035703 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 2201.727940 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.835012 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.035644 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.041233 # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks 54701.898581 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 2338.827583 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 2722.708612 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 571.952854 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 605.884854 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst 2274.772027 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data 2202.606700 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.834685 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst 0.035688 # Average percentage of cache occupancy
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
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system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
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system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average ReadReq mshr miss latency
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system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency
system.cpu0.dtb.fetch_misses 0 # ITB misses
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system.cpu0.dtb.read_misses 5970 # DTB read misses
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system.cpu0.dtb.write_misses 674 # DTB write misses
system.cpu0.dtb.write_acv 81 # DTB write access violations
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system.cpu0.itb.fetch_misses 3015 # ITB misses
system.cpu0.itb.fetch_acv 97 # ITB acv
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system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
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system.cpu0.kern.inst.arm 0 # number of arm instructions executed
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system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl
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system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl
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system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl
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system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
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system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed
system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 175298 91.20% 93.41% # number of callpals executed
+system.cpu0.kern.callpal::swpipl 175299 91.20% 93.41% # number of callpals executed
system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed
system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 192209 # number of callpals executed
+system.cpu0.kern.callpal::total 192210 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches
+system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches
-system.cpu0.kern.mode_good::kernel 1906
-system.cpu0.kern.mode_good::user 1737
+system.cpu0.kern.mode_good::kernel 1907
+system.cpu0.kern.mode_good::user 1738
system.cpu0.kern.mode_good::idle 169
-system.cpu0.kern.mode_switch_good::kernel 0.321851 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.322020 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.390894 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 29707694000 1.61% 1.61% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 2577107000 0.14% 1.75% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle 1809326710000 98.25% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total 0.391059 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 29705567000 1.61% 1.61% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 2577814500 0.14% 1.75% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::idle 1809328294500 98.25% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 4175 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.throughput 112481926 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 825463 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 825443 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 3528 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 3528 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 385263 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 17281 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 33 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 137914 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 137914 # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError 5 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 903973 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1415042 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 2319015 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 28925888 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 57212080 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 86137968 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 204476224 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 2671872 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 2218881500 # Layer occupancy (ticks)
+system.toL2Bus.trans_dist::ReadReq 2062606 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2062584 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 835833 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 17283 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 38 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 46 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 302707 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 302707 # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError 7 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1928849 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3657196 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 5586045 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61721856 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142735808 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 204457664 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 41925 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 3235706 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.012896 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.112826 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 3193978 98.71% 98.71% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 41728 1.29% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3235706 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 2218971499 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 2036319024 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 2034366165 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 2306325269 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 2306919756 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.iobus.throughput 1470003 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 2992 # Transaction distribution
-system.iobus.trans_dist::ReadResp 2992 # Transaction distribution
-system.iobus.trans_dist::WriteReq 20808 # Transaction distribution
-system.iobus.trans_dist::WriteResp 20808 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 54 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 7420 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2926 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 18 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 12900 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34700 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total 34700 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 47600 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 55 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 3710 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 2083 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 16 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 15792 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1107376 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1107376 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 1123168 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 2707176 # Total data (bytes)
+system.iobus.trans_dist::ReadReq 7317 # Transaction distribution
+system.iobus.trans_dist::ReadResp 7317 # Transaction distribution
+system.iobus.trans_dist::WriteReq 51362 # Transaction distribution
+system.iobus.trans_dist::WriteResp 27090 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 24272 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5192 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 756 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18256 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 33908 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 117358 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20768 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 952 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9128 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 45568 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2707176 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 2208000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 105000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 5525000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 5523000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 2081000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 2079000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer29.occupancy 155677802 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 9372000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 9370000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 17532750 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 17534501 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.icache.tags.replacements 964098 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.196429 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 40281211 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 964609 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 41.759108 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 10190294250 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 265.809335 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 64.640468 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst 180.746626 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.519159 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.126251 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst 0.353021 # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements 963743 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.196442 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 40274426 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 964254 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 41.767445 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 10190503250 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 263.296847 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.404531 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst 180.495065 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.514252 # Average percentage of cache occupancy
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system.cpu0.icache.tags.occ_percent::total 0.998431 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 42226967 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 42226967 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 30459275 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 7343645 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst 2478291 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 40281211 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 30459275 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 7343645 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst 2478291 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 40281211 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 30459275 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 7343645 # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst 2478291 # number of overall hits
-system.cpu0.icache.overall_hits::total 40281211 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 512792 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst 124421 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst 343745 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 980958 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 512792 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst 124421 # number of demand (read+write) misses
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-system.cpu0.icache.demand_misses::total 980958 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 512792 # number of overall misses
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-system.cpu0.icache.overall_misses::cpu2.inst 343745 # number of overall misses
-system.cpu0.icache.overall_misses::total 980958 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1775017500 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4831640896 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 6606658396 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 1775017500 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst 4831640896 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 6606658396 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 1775017500 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst 4831640896 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 6606658396 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 30972067 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst 7468066 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst 2822036 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 41262169 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 30972067 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst 7468066 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst 2822036 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 41262169 # number of demand (read+write) accesses
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-system.cpu0.dcache.writebacks::writebacks 835818 # number of writebacks
-system.cpu0.dcache.writebacks::total 835818 # number of writebacks
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-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1640 # number of LoadLockedReq MSHR hits
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-system.cpu0.dcache.overall_mshr_hits::total 831211 # number of overall MSHR hits
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-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 6047 # number of LoadLockedReq MSHR misses
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-system.cpu0.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses
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-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96407501 # number of LoadLockedReq MSHR miss cycles
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-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 124998 # number of StoreCondReq MSHR miss cycles
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-system.cpu0.dcache.overall_mshr_miss_latency::total 10958142950 # number of overall MSHR miss cycles
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-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082508 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086925 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040574 # mshr miss rate for ReadReq accesses
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-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100592 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.102549 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040011 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000163 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000045 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069141 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071318 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.033159 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069141 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071318 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.033159 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21067.619409 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16736.864428 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17870.119316 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35704.472211 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31067.517737 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32535.542482 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11178.774929 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12049.776914 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11824.788544 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 13888.666667 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13888.666667 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25674.260736 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20463.018083 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21905.420811 # average overall mshr miss latency
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-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21905.420811 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 835833 # number of writebacks
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+system.cpu0.dcache.ReadReq_mshr_misses::total 362857 # number of ReadReq MSHR misses
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+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 114498 # number of StoreCondReq MSHR miss cycles
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+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 249745500 # number of ReadReq MSHR uncacheable cycles
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+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 420262500 # number of WriteReq MSHR uncacheable cycles
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1333212000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083075 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086781 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040600 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051159 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047167 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022366 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100695 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.103022 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040066 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000145 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069491 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071226 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.033168 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069491 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071226 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.033168 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21037.194886 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16748.244464 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17877.013920 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35701.168912 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31132.717850 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32580.329109 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11185.982865 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12131.377415 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11887.901814 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14312.250000 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14312.250000 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25632.102160 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20488.581777 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21918.158626 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25632.102160 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20488.581777 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21918.158626 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 1168812 # DTB read hits
-system.cpu1.dtb.read_misses 1325 # DTB read misses
-system.cpu1.dtb.read_acv 34 # DTB read access violations
-system.cpu1.dtb.read_accesses 141647 # DTB read accesses
-system.cpu1.dtb.write_hits 873733 # DTB write hits
-system.cpu1.dtb.write_misses 170 # DTB write misses
+system.cpu1.dtb.read_hits 1168269 # DTB read hits
+system.cpu1.dtb.read_misses 1330 # DTB read misses
+system.cpu1.dtb.read_acv 35 # DTB read access violations
+system.cpu1.dtb.read_accesses 141659 # DTB read accesses
+system.cpu1.dtb.write_hits 872893 # DTB write hits
+system.cpu1.dtb.write_misses 171 # DTB write misses
system.cpu1.dtb.write_acv 22 # DTB write access violations
-system.cpu1.dtb.write_accesses 57095 # DTB write accesses
-system.cpu1.dtb.data_hits 2042545 # DTB hits
-system.cpu1.dtb.data_misses 1495 # DTB misses
-system.cpu1.dtb.data_acv 56 # DTB access violations
-system.cpu1.dtb.data_accesses 198742 # DTB accesses
-system.cpu1.itb.fetch_hits 849434 # ITB hits
-system.cpu1.itb.fetch_misses 664 # ITB misses
+system.cpu1.dtb.write_accesses 57101 # DTB write accesses
+system.cpu1.dtb.data_hits 2041162 # DTB hits
+system.cpu1.dtb.data_misses 1501 # DTB misses
+system.cpu1.dtb.data_acv 57 # DTB access violations
+system.cpu1.dtb.data_accesses 198760 # DTB accesses
+system.cpu1.itb.fetch_hits 849127 # ITB hits
+system.cpu1.itb.fetch_misses 665 # ITB misses
system.cpu1.itb.fetch_acv 34 # ITB acv
-system.cpu1.itb.fetch_accesses 850098 # ITB accesses
+system.cpu1.itb.fetch_accesses 849792 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 953402608 # number of cpu cycles simulated
+system.cpu1.numCycles 953403050 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 7466514 # Number of instructions committed
-system.cpu1.committedOps 7466514 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 6940405 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 43972 # Number of float alu accesses
-system.cpu1.num_func_calls 203873 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 905018 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 6940405 # number of integer instructions
-system.cpu1.num_fp_insts 43972 # number of float instructions
-system.cpu1.num_int_register_reads 9656232 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 5062933 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 23750 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 24129 # number of times the floating registers were written
-system.cpu1.num_mem_refs 2049510 # number of memory refs
-system.cpu1.num_load_insts 1173515 # Number of load instructions
-system.cpu1.num_store_insts 875995 # Number of store instructions
-system.cpu1.num_idle_cycles 923975227.132686 # Number of idle cycles
-system.cpu1.num_busy_cycles 29427380.867314 # Number of busy cycles
+system.cpu1.committedInsts 7463992 # Number of instructions committed
+system.cpu1.committedOps 7463992 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 6937939 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 43895 # Number of float alu accesses
+system.cpu1.num_func_calls 203449 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 905325 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 6937939 # number of integer instructions
+system.cpu1.num_fp_insts 43895 # number of float instructions
+system.cpu1.num_int_register_reads 9652072 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 5060714 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 23736 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 24066 # number of times the floating registers were written
+system.cpu1.num_mem_refs 2048141 # number of memory refs
+system.cpu1.num_load_insts 1172984 # Number of load instructions
+system.cpu1.num_store_insts 875157 # Number of store instructions
+system.cpu1.num_idle_cycles 923975246.943285 # Number of idle cycles
+system.cpu1.num_busy_cycles 29427803.056715 # Number of busy cycles
system.cpu1.not_idle_fraction 0.030866 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.969134 # Percentage of idle cycles
-system.cpu1.Branches 1173577 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 399506 5.35% 5.35% # Class of executed instruction
-system.cpu1.op_class::IntAlu 4845173 64.88% 70.23% # Class of executed instruction
-system.cpu1.op_class::IntMult 8216 0.11% 70.34% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 70.34% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 5112 0.07% 70.41% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 70.41% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 70.41% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 70.41% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 810 0.01% 70.42% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 70.42% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 70.42% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 70.42% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 70.42% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 70.42% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 70.42% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 70.42% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 70.42% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 70.42% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 70.42% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.42% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 70.42% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.42% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.42% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.42% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.42% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.42% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.42% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 70.42% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.42% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.42% # Class of executed instruction
-system.cpu1.op_class::MemRead 1201694 16.09% 86.51% # Class of executed instruction
-system.cpu1.op_class::MemWrite 877208 11.75% 98.25% # Class of executed instruction
-system.cpu1.op_class::IprAccess 130346 1.75% 100.00% # Class of executed instruction
+system.cpu1.Branches 1173357 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 399705 5.35% 5.35% # Class of executed instruction
+system.cpu1.op_class::IntAlu 4844088 64.89% 70.24% # Class of executed instruction
+system.cpu1.op_class::IntMult 8214 0.11% 70.35% # Class of executed instruction
+system.cpu1.op_class::IntDiv 0 0.00% 70.35% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 5110 0.07% 70.42% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 70.42% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 70.42% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 70.42% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 810 0.01% 70.43% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 70.43% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 70.43% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 70.43% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 70.43% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 70.43% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 70.43% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 70.43% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 70.43% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 70.43% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 70.43% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.43% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 70.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 70.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.43% # Class of executed instruction
+system.cpu1.op_class::MemRead 1201071 16.09% 86.52% # Class of executed instruction
+system.cpu1.op_class::MemWrite 876369 11.74% 98.26% # Class of executed instruction
+system.cpu1.op_class::IprAccess 130183 1.74% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 7468065 # Class of executed instruction
+system.cpu1.op_class::total 7465550 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed
system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu1.kern.swap_context 0 # number of times the context was actually changed
-system.cpu2.branchPred.lookups 9007020 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 8266685 # Number of conditional branches predicted
+system.cpu2.branchPred.lookups 9020137 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 8282573 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 125563 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 6913379 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 4889018 # Number of BTB hits
+system.cpu2.branchPred.BTBLookups 6965204 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 4892106 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 70.718212 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 301119 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 7670 # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct 70.236364 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 299658 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 7807 # Number of incorrect RAS predictions.
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
-system.cpu2.dtb.read_hits 3485225 # DTB read hits
-system.cpu2.dtb.read_misses 12620 # DTB read misses
+system.cpu2.dtb.read_hits 3485260 # DTB read hits
+system.cpu2.dtb.read_misses 12402 # DTB read misses
system.cpu2.dtb.read_acv 152 # DTB read access violations
-system.cpu2.dtb.read_accesses 227645 # DTB read accesses
-system.cpu2.dtb.write_hits 2140940 # DTB write hits
-system.cpu2.dtb.write_misses 2817 # DTB write misses
-system.cpu2.dtb.write_acv 139 # DTB write access violations
-system.cpu2.dtb.write_accesses 85106 # DTB write accesses
-system.cpu2.dtb.data_hits 5626165 # DTB hits
-system.cpu2.dtb.data_misses 15437 # DTB misses
-system.cpu2.dtb.data_acv 291 # DTB access violations
-system.cpu2.dtb.data_accesses 312751 # DTB accesses
-system.cpu2.itb.fetch_hits 539657 # ITB hits
-system.cpu2.itb.fetch_misses 5944 # ITB misses
-system.cpu2.itb.fetch_acv 165 # ITB acv
-system.cpu2.itb.fetch_accesses 545601 # ITB accesses
+system.cpu2.dtb.read_accesses 227268 # DTB read accesses
+system.cpu2.dtb.write_hits 2138350 # DTB write hits
+system.cpu2.dtb.write_misses 2805 # DTB write misses
+system.cpu2.dtb.write_acv 140 # DTB write access violations
+system.cpu2.dtb.write_accesses 85115 # DTB write accesses
+system.cpu2.dtb.data_hits 5623610 # DTB hits
+system.cpu2.dtb.data_misses 15207 # DTB misses
+system.cpu2.dtb.data_acv 292 # DTB access violations
+system.cpu2.dtb.data_accesses 312383 # DTB accesses
+system.cpu2.itb.fetch_hits 538601 # ITB hits
+system.cpu2.itb.fetch_misses 5813 # ITB misses
+system.cpu2.itb.fetch_acv 166 # ITB acv
+system.cpu2.itb.fetch_accesses 544414 # ITB accesses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.read_acv 0 # DTB read access violations
system.cpu2.itb.data_misses 0 # DTB misses
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses
-system.cpu2.numCycles 29515720 # number of cpu cycles simulated
+system.cpu2.numCycles 29513686 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 9404916 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 35474807 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 9007020 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 5190137 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 18003717 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 410566 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles 517 # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles 9775 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 1999 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 235781 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 98995 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 442 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 2822037 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 92550 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples 27961187 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.268716 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.388099 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles 9389582 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 35469274 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 9020137 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 5191764 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 18021119 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 410530 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles 647 # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles 9356 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 1948 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 228650 # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles 98931 # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles 387 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 2818143 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 92772 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples 27955647 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.268770 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.388372 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 20241670 72.39% 72.39% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 312691 1.12% 73.51% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 474251 1.70% 75.21% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 3278987 11.73% 86.93% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 837934 3.00% 89.93% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 194435 0.70% 90.63% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 239683 0.86% 91.48% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 437644 1.57% 93.05% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 1943892 6.95% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 20239272 72.40% 72.40% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 311789 1.12% 73.51% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 473018 1.69% 75.21% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 3278988 11.73% 86.93% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 836372 2.99% 89.93% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 194449 0.70% 90.62% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 239819 0.86% 91.48% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 437682 1.57% 93.05% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 1944258 6.95% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 27961187 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.305160 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 1.201895 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 7704419 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 13193149 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 6090024 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 535254 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 192290 # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved 176132 # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred 13346 # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts 32094888 # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts 42715 # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles 192290 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 7987526 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 4830275 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 6354829 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 6312082 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 2038145 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 31271508 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 68877 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 405466 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents 55957 # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents 963204 # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands 20931686 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 38638449 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 38578281 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 56251 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 19026086 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 1905600 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 533120 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 63723 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 3942739 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 3510198 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 2234995 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 462280 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 329256 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 28739879 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 680947 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 28391596 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 17529 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 2438506 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 1151582 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 487021 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 27961187 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.015393 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.594251 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 27955647 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.305626 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 1.201791 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 7697914 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 13194592 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 6089531 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 535341 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 192357 # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved 175638 # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred 13257 # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts 32098439 # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts 42458 # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles 192357 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 7981444 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 4806689 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 6360452 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 6310892 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 2057913 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 31276153 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 68586 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 406035 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents 57262 # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents 980638 # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands 20937225 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 38641604 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 38581458 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 56230 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 19023888 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 1913337 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 532654 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 63537 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 3939185 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 3509523 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 2229292 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 463055 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 331167 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 28745476 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 680921 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 28394222 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 16375 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 2445259 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 1154216 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 487025 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 27955647 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.015688 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.594887 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 17574861 62.85% 62.85% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 2788082 9.97% 72.83% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 1379347 4.93% 77.76% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 4037262 14.44% 92.20% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 1018579 3.64% 95.84% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 572705 2.05% 97.89% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 385941 1.38% 99.27% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 155733 0.56% 99.83% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 48677 0.17% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 17573743 62.86% 62.86% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 2782129 9.95% 72.81% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 1379697 4.94% 77.75% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 4038946 14.45% 92.20% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 1015784 3.63% 95.83% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 573145 2.05% 97.88% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 387606 1.39% 99.27% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 155412 0.56% 99.82% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 49185 0.18% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 27961187 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 27955647 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 82533 21.35% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 178965 46.29% 67.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 125088 32.36% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 83781 21.60% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 179225 46.21% 67.82% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 124810 32.18% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 2456 0.01% 0.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 22261960 78.41% 78.42% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 21111 0.07% 78.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 78.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 20516 0.07% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 78.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 3614417 12.73% 91.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 2165470 7.63% 98.93% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess 304438 1.07% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 22268545 78.43% 78.43% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 21109 0.07% 78.51% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 78.51% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 20518 0.07% 78.58% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 78.58% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 78.58% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 78.58% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 3613635 12.73% 91.31% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 2162330 7.62% 98.93% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess 304401 1.07% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 28391596 # Type of FU issued
-system.cpu2.iq.rate 0.961914 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 386586 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.013616 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 84894790 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 31745632 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 27810644 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 253704 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 119619 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 117118 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 28639647 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 136079 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 206810 # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total 28394222 # Type of FU issued
+system.cpu2.iq.rate 0.962070 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 387816 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.013658 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 84894498 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 31757890 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 27813110 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 253784 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 119651 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses 117192 # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses 28643478 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 136104 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 207211 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 438537 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 1486 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 6057 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 183313 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 438819 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 1413 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 6020 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 178766 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 5003 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 177760 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads 5023 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 176307 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 192290 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 4010862 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 349296 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 30806306 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 54542 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 3510198 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 2234995 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 606167 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 15566 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 285460 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 6057 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 62858 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 135105 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 197963 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 28193561 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 3506622 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 198035 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles 192357 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 4003600 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 328635 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 30811270 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 51966 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 3509523 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 2229292 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 606230 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 15640 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 265026 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 6020 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 63511 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 134698 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 198209 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 28196871 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 3506429 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 197351 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 1385480 # number of nop insts executed
-system.cpu2.iew.exec_refs 5655108 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 5954900 # Number of branches executed
-system.cpu2.iew.exec_stores 2148486 # Number of stores executed
-system.cpu2.iew.exec_rate 0.955205 # Inst execution rate
-system.cpu2.iew.wb_sent 27969918 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 27927762 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 15888662 # num instructions producing a value
-system.cpu2.iew.wb_consumers 19538696 # num instructions consuming a value
+system.cpu2.iew.exec_nop 1384873 # number of nop insts executed
+system.cpu2.iew.exec_refs 5652310 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 5956275 # Number of branches executed
+system.cpu2.iew.exec_stores 2145881 # Number of stores executed
+system.cpu2.iew.exec_rate 0.955383 # Inst execution rate
+system.cpu2.iew.wb_sent 27971955 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 27930302 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 15891558 # num instructions producing a value
+system.cpu2.iew.wb_consumers 19546280 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 0.946200 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.813189 # average fanout of values written-back
+system.cpu2.iew.wb_rate 0.946351 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.813022 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 2672008 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 193926 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 180997 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 27494343 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.021637 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.858517 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 2680068 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 193896 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 181086 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 27486207 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.021790 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 1.858200 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 18377188 66.84% 66.84% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 2251123 8.19% 75.03% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1180007 4.29% 79.32% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 3743706 13.62% 92.94% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 543464 1.98% 94.91% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 201872 0.73% 95.65% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 166281 0.60% 96.25% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 179533 0.65% 96.90% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 851169 3.10% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 18368842 66.83% 66.83% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 2248676 8.18% 75.01% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1182960 4.30% 79.31% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 3745017 13.63% 92.94% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 544035 1.98% 94.92% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 201250 0.73% 95.65% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 165260 0.60% 96.25% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 179807 0.65% 96.91% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 850360 3.09% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 27494343 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 28089240 # Number of instructions committed
-system.cpu2.commit.committedOps 28089240 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 27486207 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 28085126 # Number of instructions committed
+system.cpu2.commit.committedOps 28085126 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 5123343 # Number of memory references committed
-system.cpu2.commit.loads 3071661 # Number of loads committed
-system.cpu2.commit.membars 68272 # Number of memory barriers committed
-system.cpu2.commit.branches 5784239 # Number of branches committed
-system.cpu2.commit.fp_insts 115390 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 26574373 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 240380 # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass 1220895 4.35% 4.35% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu 21328709 75.93% 80.28% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult 20651 0.07% 80.35% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv 0 0.00% 80.35% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd 20067 0.07% 80.42% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 80.42% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 80.42% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult 0 0.00% 80.42% # Class of committed instruction
+system.cpu2.commit.refs 5121230 # Number of memory references committed
+system.cpu2.commit.loads 3070704 # Number of loads committed
+system.cpu2.commit.membars 68250 # Number of memory barriers committed
+system.cpu2.commit.branches 5783973 # Number of branches committed
+system.cpu2.commit.fp_insts 115466 # Number of committed floating point instructions.
+system.cpu2.commit.int_insts 26570607 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 240322 # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass 1220562 4.35% 4.35% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu 21327099 75.94% 80.28% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult 20651 0.07% 80.36% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv 0 0.00% 80.36% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd 20069 0.07% 80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv 1228 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead 3139933 11.18% 91.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite 2053319 7.31% 98.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::IprAccess 304438 1.08% 100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead 3138954 11.18% 91.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite 2052162 7.31% 98.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::IprAccess 304401 1.08% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total 28089240 # Class of committed instruction
-system.cpu2.commit.bw_lim_events 851169 # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total 28085126 # Class of committed instruction
+system.cpu2.commit.bw_lim_events 850360 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 57327258 # The number of ROB reads
-system.cpu2.rob.rob_writes 61989353 # The number of ROB writes
-system.cpu2.timesIdled 175568 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 1554533 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 1746289037 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 26870801 # Number of Instructions Simulated
-system.cpu2.committedOps 26870801 # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi 1.098431 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 1.098431 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.910389 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.910389 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 36957190 # number of integer regfile reads
-system.cpu2.int_regfile_writes 19824047 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 70953 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 70972 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 3637810 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 273227 # number of misc regfile writes
+system.cpu2.rob.rob_reads 57323983 # The number of ROB reads
+system.cpu2.rob.rob_writes 61998256 # The number of ROB writes
+system.cpu2.timesIdled 175445 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 1558039 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 1746293269 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 26867020 # Number of Instructions Simulated
+system.cpu2.committedOps 26867020 # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi 1.098510 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 1.098510 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.910324 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.910324 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 36957336 # number of integer regfile reads
+system.cpu2.int_regfile_writes 19827241 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 70923 # number of floating regfile reads
+system.cpu2.fp_regfile_writes 71075 # number of floating regfile writes
+system.cpu2.misc_regfile_reads 3638892 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 273174 # number of misc regfile writes
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed
---------- Begin Simulation Statistics ----------
-sim_seconds 1.145505 # Number of seconds simulated
-sim_ticks 1145504982000 # Number of ticks simulated
-final_tick 1145504982000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.658500 # Number of seconds simulated
+sim_ticks 2658500429500 # Number of ticks simulated
+final_tick 2658500429500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 113120 # Simulator instruction rate (inst/s)
-host_op_rate 136231 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2095202848 # Simulator tick rate (ticks/s)
-host_mem_usage 413760 # Number of bytes of host memory used
-host_seconds 546.73 # Real time elapsed on the host
-sim_insts 61845931 # Number of instructions simulated
-sim_ops 74481224 # Number of ops (including micro ops) simulated
+host_inst_rate 100914 # Simulator instruction rate (inst/s)
+host_op_rate 121517 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4256503307 # Simulator tick rate (ticks/s)
+host_mem_usage 437672 # Number of bytes of host memory used
+host_seconds 624.57 # Real time elapsed on the host
+sim_insts 63028509 # Number of instructions simulated
+sim_ops 75896503 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 256 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 4 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 223 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 391 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 615 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 223 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 391 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 615 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 223 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 391 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 615 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 7004988 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 576 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 3603320 # Number of bytes read from this memory
-system.physmem.bytes_read::total 60941044 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 751104 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 270784 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1021888 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4281152 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.inst 670652 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 5012160 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 503736 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 5163008 # Number of bytes read from this memory
+system.physmem.bytes_read::total 134034100 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 219584 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 61824 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 281408 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4338816 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.inst 17000 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.inst 3010344 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7308496 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory
+system.physmem.bytes_written::cpu1.inst 3012136 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7367952 # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 109512 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 9 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 56320 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 6457305 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 66893 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 10538 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 78315 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 7889 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 80672 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15512856 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 67794 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.inst 4250 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.inst 752586 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 823729 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 43938393 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 335 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 112 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 6115196 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 503 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 3145617 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 53200156 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 655697 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 236388 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 892085 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3737349 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.inst 14841 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.inst 2627962 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6380152 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3737349 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 43938393 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 335 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 112 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 6130037 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 503 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 5773579 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 59580308 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 6457305 # Number of read requests accepted
-system.physmem.writeReqs 823729 # Number of write requests accepted
-system.physmem.readBursts 6457305 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 823729 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 413239936 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 27584 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7320448 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 60941044 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 7308496 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 431 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 709326 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 12284 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 403300 # Per bank write bursts
-system.physmem.perBankRdBursts::1 403658 # Per bank write bursts
-system.physmem.perBankRdBursts::2 403038 # Per bank write bursts
-system.physmem.perBankRdBursts::3 403410 # Per bank write bursts
-system.physmem.perBankRdBursts::4 406147 # Per bank write bursts
-system.physmem.perBankRdBursts::5 403703 # Per bank write bursts
-system.physmem.perBankRdBursts::6 403511 # Per bank write bursts
-system.physmem.perBankRdBursts::7 403334 # Per bank write bursts
-system.physmem.perBankRdBursts::8 403656 # Per bank write bursts
-system.physmem.perBankRdBursts::9 404136 # Per bank write bursts
-system.physmem.perBankRdBursts::10 403079 # Per bank write bursts
-system.physmem.perBankRdBursts::11 402530 # Per bank write bursts
-system.physmem.perBankRdBursts::12 403635 # Per bank write bursts
-system.physmem.perBankRdBursts::13 403544 # Per bank write bursts
-system.physmem.perBankRdBursts::14 403293 # Per bank write bursts
-system.physmem.perBankRdBursts::15 402900 # Per bank write bursts
-system.physmem.perBankWrBursts::0 6991 # Per bank write bursts
-system.physmem.perBankWrBursts::1 7395 # Per bank write bursts
-system.physmem.perBankWrBursts::2 6850 # Per bank write bursts
-system.physmem.perBankWrBursts::3 7056 # Per bank write bursts
-system.physmem.perBankWrBursts::4 7584 # Per bank write bursts
-system.physmem.perBankWrBursts::5 7290 # Per bank write bursts
-system.physmem.perBankWrBursts::6 7311 # Per bank write bursts
-system.physmem.perBankWrBursts::7 7141 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7309 # Per bank write bursts
-system.physmem.perBankWrBursts::9 7743 # Per bank write bursts
-system.physmem.perBankWrBursts::10 6877 # Per bank write bursts
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+system.physmem.bytesWritten 7383872 # Total number of bytes written to DRAM
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 1145502120500 # Total gap between requests
+system.physmem.totGap 2658500409000 # Total gap between requests
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-system.physmem.rdPerTurnAround::mean 970.665664 # Reads before turning the bus around for writes
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-system.physmem.rdPerTurnAround::0-65535 6645 99.89% 99.89% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.97% # Reads before turning the bus around for writes
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-system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6652 # Reads before turning the bus around for writes
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-system.physmem.totQLat 165525335000 # Total ticks spent queuing
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+system.physmem.wrPerTurnAround::19 190 2.86% 96.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 92 1.39% 98.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 40 0.60% 98.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 30 0.45% 99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 20 0.30% 99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 15 0.23% 99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 13 0.20% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 1 0.02% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28 1 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6640 # Writes before turning the bus around for reads
+system.physmem.totQLat 403478953250 # Total ticks spent queuing
+system.physmem.totMemAccLat 694311028250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 77555220000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 26012.37 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44385.52 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 360.75 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 6.39 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 53.20 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 6.38 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 44762.37 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 373.41 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.78 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 50.42 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.77 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 2.87 # Data bus utilization in percentage
-system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 3.81 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 26.84 # Average write queue length when enqueuing
-system.physmem.readRowHits 6016106 # Number of row buffer hits during reads
-system.physmem.writeRowHits 94363 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 93.17 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 82.48 # Row buffer hit rate for writes
-system.physmem.avgGap 157326.85 # Average gap between requests
-system.physmem.pageHitRate 92.99 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 907058635500 # Time in different power states
-system.physmem.memoryStateTime::REF 38250680000 # Time in different power states
+system.physmem.busUtil 2.94 # Data bus utilization in percentage
+system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 6.07 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 26.23 # Average write queue length when enqueuing
+system.physmem.readRowHits 14503444 # Number of row buffer hits during reads
+system.physmem.writeRowHits 85277 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.90 # Row buffer hit rate for writes
+system.physmem.avgGap 162719.50 # Average gap between requests
+system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 2316371594000 # Time in different power states
+system.physmem.memoryStateTime::REF 88773100000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 200188472000 # Time in different power states
+system.physmem.memoryStateTime::ACT 253353834750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 61688542 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 7506218 # Transaction distribution
-system.membus.trans_dist::ReadResp 7506218 # Transaction distribution
-system.membus.trans_dist::WriteReq 767823 # Transaction distribution
-system.membus.trans_dist::WriteResp 767823 # Transaction distribution
-system.membus.trans_dist::Writeback 66893 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 33061 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 17229 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 12284 # Transaction distribution
-system.membus.trans_dist::ReadExReq 137868 # Transaction distribution
-system.membus.trans_dist::ReadExResp 137512 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382652 # Packet count per connected master and slave (bytes)
+system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 256 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 4 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 96 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 169 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 265 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 96 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 169 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 265 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 96 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 169 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 265 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 16692425 # Transaction distribution
+system.membus.trans_dist::ReadResp 16692425 # Transaction distribution
+system.membus.trans_dist::WriteReq 768873 # Transaction distribution
+system.membus.trans_dist::WriteResp 768873 # Transaction distribution
+system.membus.trans_dist::Writeback 67794 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 55379 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 22285 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 15707 # Transaction distribution
+system.membus.trans_dist::ReadExReq 15268 # Transaction distribution
+system.membus.trans_dist::ReadExResp 8420 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384472 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11272 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 12568 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 874 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1975193 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4370017 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12582912 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 12582912 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 16952929 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389988 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 22544 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1748 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17917892 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total 20332884 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 50331648 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 50331648 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 70664532 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 70664532 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1775897999 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 16500 # Layer occupancy (ticks)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2090 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2037445 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 4436601 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 35107449 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392888 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 25136 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4180 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18718660 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 21141576 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 143824968 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 68805 # Total snoops (count)
+system.membus.snoop_fanout::samples 327203 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 327203 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 327203 # Request fanout histogram
+system.membus.reqLayer0.occupancy 1769123496 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 12000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 10198500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 10983499 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 781000 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 1597500 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer6.occupancy 8866177000 # Layer occupancy (ticks)
-system.membus.reqLayer6.utilization 0.8 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4931588399 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
-system.membus.respLayer2.occupancy 15569082998 # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy 17876588998 # Layer occupancy (ticks)
+system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
+system.membus.respLayer1.occupancy 5004631688 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.membus.respLayer2.occupancy 37937018429 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.4 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 73238 # number of replacements
-system.l2c.tags.tagsinuse 53823.910561 # Cycle average of tags in use
-system.l2c.tags.total_refs 2398257 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 138408 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 17.327445 # Average number of references to valid blocks.
+system.l2c.tags.replacements 92212 # number of replacements
+system.l2c.tags.tagsinuse 55213.567741 # Cycle average of tags in use
+system.l2c.tags.total_refs 396364 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 156868 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 2.526736 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 38958.946929 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.880846 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001294 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 8788.881914 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.740937 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 6066.458640 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.594466 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000029 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.134108 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000118 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.092567 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.821288 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024 65164 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 2438 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 8664 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 53947 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024 0.994324 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 23040420 # Number of tag accesses
-system.l2c.tags.data_accesses 23040420 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker 22272 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 6564 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 949144 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 22723 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 5189 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 959680 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1965572 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 575172 # number of Writeback hits
-system.l2c.Writeback_hits::total 575172 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.inst 954 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.inst 1026 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 1980 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.inst 203 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.inst 94 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 297 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.inst 58656 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.inst 50708 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 109364 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 22272 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 6564 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 1007800 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 22723 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 5189 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 1010388 # number of demand (read+write) hits
-system.l2c.demand_hits::total 2074936 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 22272 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 6564 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 1007800 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 22723 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 5189 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 1010388 # number of overall hits
-system.l2c.overall_hits::total 2074936 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker 6 # number of ReadReq misses
+system.l2c.tags.occ_blocks::writebacks 8088.192516 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.706191 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker 1.029154 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 2502.443827 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29448.913538 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.609197 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker 0.004438 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 2039.532288 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13124.136592 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.123416 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000057 # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::total 0.842492 # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022 53217 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024 11430 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2 151 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3 4758 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4 48307 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2 265 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3 1757 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4 9394 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022 0.812027 # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id
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system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles
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-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10979297747 # number of ReadReq MSHR uncacheable cycles
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-system.l2c.WriteReq_mshr_uncacheable_latency::total 16779233830 # number of WriteReq MSHR uncacheable cycles
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-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 26394184094 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 184207561064 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000269 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000305 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016636 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000396 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010088 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.012983 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.836448 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.798349 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.818698 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.773942 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.761421 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770124 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.611822 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.483194 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.561182 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000269 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000305 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097198 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000396 # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::total 0.073956 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000269 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000305 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097198 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000396 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.053569 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.073956 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667 # average ReadReq mshr miss latency
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+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 155062093246 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 167634442242 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 1125655500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 15721437217 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 16847092717 # number of WriteReq MSHR uncacheable cycles
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+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 170783530463 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 184481534959 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.026596 # mshr miss rate for ReadReq accesses
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+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.263909 # mshr miss rate for demand accesses
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+system.l2c.demand_mshr_miss_rate::total 0.461727 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.026596 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.051282 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.319578 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470674 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.041152 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.263909 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.514316 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.461727 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57884.169884 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62303.885481 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 59566.167086 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10018.723099 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10015.890202 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10017.436081 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10062.861871 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10007.663333 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10046.219095 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 56549.376777 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 58549.292491 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 57227.311883 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 65232.134350 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78194.936321 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66625 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 130500 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68533.903482 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96561.277668 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 86576.788866 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10070.786168 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10076.575404 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10073.186142 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10146.641834 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10021.960802 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10082.847481 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 58574.829899 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61446.364353 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 60109.204282 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56746.911592 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59191.361374 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 57592.222128 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61992.213622 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78194.936321 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66625 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64405.757684 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96561.277668 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 85284.289292 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56746.911592 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59191.361374 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 57592.222128 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61992.213622 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78194.936321 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66625 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64405.757684 # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::total 85284.289292 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.toL2Bus.throughput 163445997 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 3265310 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 3265309 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 767823 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 767823 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 575172 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 32693 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 17526 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 50219 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 260531 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 260531 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1555911 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3285118 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 16087 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52607 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1583939 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2567940 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 13476 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 53641 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 9128719 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 49766528 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 43750900 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26264 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 89112 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 50661248 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 38001760 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20756 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 90928 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 182407496 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 182407496 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 4820708 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 5144551012 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 3505001405 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 2792622052 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 9525491 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 30330496 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 3566573438 # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 1934335367 # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer8.occupancy 8290992 # Layer occupancy (ticks)
-system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer9.occupancy 30912744 # Layer occupancy (ticks)
-system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.throughput 46024799 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 7474816 # Transaction distribution
-system.iobus.trans_dist::ReadResp 7474816 # Transaction distribution
-system.iobus.trans_dist::WriteReq 7966 # Transaction distribution
-system.iobus.trans_dist::WriteResp 7966 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30566 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8038 # Packet count per connected master and slave (bytes)
+system.toL2Bus.trans_dist::ReadReq 1655769 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 1655769 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 768873 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 768873 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 215065 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 60425 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 22592 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 83017 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 22828 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 22828 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 802487 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4302639 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 5105126 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 20032432 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 23601176 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 43633608 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 171019 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 786212 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 786212 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 786212 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 2618569936 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 1234710374 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 2607103376 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 16519576 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16519576 # Transaction distribution
+system.iobus.trans_dist::WriteReq 8084 # Transaction distribution
+system.iobus.trans_dist::WriteResp 8084 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8928 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 732 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 498 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 738 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2382652 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12582912 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total 12582912 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 14965564 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40335 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16076 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1464 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 273 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 2389988 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 50331648 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::total 50331648 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 52721636 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 52721636 # Total data (bytes)
-system.iobus.reqLayer0.occupancy 21429000 # Layer occupancy (ticks)
+system.iobus.pkt_count_system.bridge.master::total 2384472 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 33055320 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17856 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 393 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 2392888 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 125076280 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 4025000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 4470000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 372000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 299000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy 441000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 6291456000 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2374686000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.2 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 15862213002 # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization 1.4 # Layer utilization (%)
-system.cpu0.branchPred.lookups 6670288 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 4756995 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 639495 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 4605007 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 3289427 # Number of BTB hits
+system.iobus.reqLayer26.occupancy 15335424000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 2376388000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.iobus.respLayer1.occupancy 38667942571 # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
+system.cpu0.branchPred.lookups 7247667 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 5145194 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 425040 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 4677323 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 3357189 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 71.431531 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 870926 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 69312 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 71.775864 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 942424 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 64273 # Number of incorrect RAS predictions.
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 7193152 # DTB read hits
-system.cpu0.dtb.read_misses 17493 # DTB read misses
-system.cpu0.dtb.write_hits 6058571 # DTB write hits
-system.cpu0.dtb.write_misses 1416 # DTB write misses
+system.cpu0.dtb.read_hits 6449421 # DTB read hits
+system.cpu0.dtb.read_misses 22629 # DTB read misses
+system.cpu0.dtb.write_hits 5803237 # DTB write hits
+system.cpu0.dtb.write_misses 1880 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 1942 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1486 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 207 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 1731 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1649 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 155 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 320 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 7210645 # DTB read accesses
-system.cpu0.dtb.write_accesses 6059987 # DTB write accesses
+system.cpu0.dtb.perms_faults 268 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 6472050 # DTB read accesses
+system.cpu0.dtb.write_accesses 5805117 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 13251723 # DTB hits
-system.cpu0.dtb.misses 18909 # DTB misses
-system.cpu0.dtb.accesses 13270632 # DTB accesses
+system.cpu0.dtb.hits 12252658 # DTB hits
+system.cpu0.dtb.misses 24509 # DTB misses
+system.cpu0.dtb.accesses 12277167 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 12268451 # ITB inst hits
-system.cpu0.itb.inst_misses 4809 # ITB inst misses
+system.cpu0.itb.inst_hits 13306402 # ITB inst hits
+system.cpu0.itb.inst_misses 3981 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1294 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1196 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 2809 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 3606 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 12273260 # ITB inst accesses
-system.cpu0.itb.hits 12268451 # DTB hits
-system.cpu0.itb.misses 4809 # DTB misses
-system.cpu0.itb.accesses 12273260 # DTB accesses
-system.cpu0.numCycles 431172708 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 13310383 # ITB inst accesses
+system.cpu0.itb.hits 13306402 # DTB hits
+system.cpu0.itb.misses 3981 # DTB misses
+system.cpu0.itb.accesses 13310383 # DTB accesses
+system.cpu0.numCycles 86779776 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 29878954 # Number of instructions committed
-system.cpu0.committedOps 36403873 # Number of ops (including micro ops) committed
-system.cpu0.discardedOps 1704985 # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends 39450 # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles 1859905219 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
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-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053041 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.046176 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046176 # miss rate for StoreCondReq accesses
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-system.cpu0.dcache.demand_miss_rate::total 0.048646 # miss rate for demand accesses
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-system.cpu0.dcache.overall_miss_rate::total 0.048646 # miss rate for overall accesses
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-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15024.455547 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 49222.599227 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 49222.599227 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 10429.369443 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10429.369443 # average LoadLockedReq miss latency
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-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6367.951069 # average StoreCondReq miss latency
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-system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 33836.766666 # average overall miss latency
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+system.cpu0.toL2Bus.snoops 663093 # Total snoops (count)
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+system.cpu0.toL2Bus.snoop_fanout::stdev 0.455949 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
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+system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
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+system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
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+system.cpu0.toL2Bus.reqLayer0.occupancy 1042501632 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
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+system.cpu0.l2cache.tags.avg_refs 6.002562 # Average number of references to valid blocks.
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+system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.910708 # miss rate for UpgradeReq accesses
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+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 26888.402857 # average ReadReq miss latency
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+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 16529.886177 # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 16529.886177 # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19831.976186 # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19831.976186 # average SCUpgradeReq miss latency
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+system.cpu0.dcache.overall_miss_rate::total 0.050278 # miss rate for overall accesses
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+system.cpu0.dcache.ReadReq_avg_miss_latency::total 11955.328076 # average ReadReq miss latency
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+system.cpu0.dcache.WriteReq_avg_miss_latency::total 15140.583677 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16392.161782 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16392.161782 # average LoadLockedReq miss latency
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+system.cpu0.dcache.demand_avg_miss_latency::total 13459.308511 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13459.308511 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 13459.308511 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 307170 # number of writebacks
-system.cpu0.dcache.writebacks::total 307170 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 50178 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 50178 # number of ReadReq MSHR hits
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-system.cpu0.dcache.WriteReq_mshr_hits::total 144238 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 22 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.inst 194416 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 194416 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.inst 194416 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 194416 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 204937 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 204937 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 167692 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 167692 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 8526 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8526 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 7439 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 7439 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.inst 372629 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 372629 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.inst 372629 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 372629 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2523643558 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2523643558 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 7293302576 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7293302576 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 71695750 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 71695750 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 32490812 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32490812 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9816946134 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 9816946134 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9816946134 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 9816946134 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 170796523752 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 170796523752 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1513122000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1513122000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 172309645752 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 172309645752 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.035073 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035073 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.028846 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028846 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.052905 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.052905 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.046176 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.046176 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.031968 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.031968 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.031968 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.031968 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12314.240757 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12314.240757 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 43492.251127 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43492.251127 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 8409.072250 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8409.072250 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 4367.631671 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4367.631671 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 26345.094273 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26345.094273 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 26345.094273 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26345.094273 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 277395 # number of writebacks
+system.cpu0.dcache.writebacks::total 277395 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 54934 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 54934 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 124546 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 124546 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 74 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 74 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.inst 179480 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 179480 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.inst 179480 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 179480 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 254665 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 254665 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 152405 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 152405 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 10094 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 10094 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 10891 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 10891 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.inst 407070 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 407070 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.inst 407070 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 407070 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2527058296 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2527058296 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 2131958823 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2131958823 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 145779499 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145779499 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 231881036 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 231881036 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 1299500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1299500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 4659017119 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 4659017119 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 4659017119 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 4659017119 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 14650509239 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14650509239 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1394876998 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1394876998 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 16045386237 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 16045386237 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.041653 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041653 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.027450 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027450 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.064036 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064036 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.069147 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.069147 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.034893 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.034893 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.034893 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.034893 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9923.068722 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 9923.068722 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 13988.772173 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13988.772173 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14442.193283 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14442.193283 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 21291.069323 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21291.069323 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11445.248038 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11445.248038 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11445.248038 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11445.248038 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 6159330 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 4534606 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 426160 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 3924244 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 3043762 # Number of BTB hits
+system.cpu1.branchPred.lookups 7015971 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 5101339 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 682515 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 5021553 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 3808301 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 77.563016 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 713205 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 64399 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 75.839108 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 855690 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 72942 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 6763605 # DTB read hits
-system.cpu1.dtb.read_misses 17087 # DTB read misses
-system.cpu1.dtb.write_hits 5563764 # DTB write hits
-system.cpu1.dtb.write_misses 2456 # DTB write misses
+system.cpu1.dtb.read_hits 7897430 # DTB read hits
+system.cpu1.dtb.read_misses 21135 # DTB read misses
+system.cpu1.dtb.write_hits 6047519 # DTB write hits
+system.cpu1.dtb.write_misses 2176 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1713 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 1918 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 230 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 1928 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 3376 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 148 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 260 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 6780692 # DTB read accesses
-system.cpu1.dtb.write_accesses 5566220 # DTB write accesses
+system.cpu1.dtb.perms_faults 328 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 7918565 # DTB read accesses
+system.cpu1.dtb.write_accesses 6049695 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 12327369 # DTB hits
-system.cpu1.dtb.misses 19543 # DTB misses
-system.cpu1.dtb.accesses 12346912 # DTB accesses
+system.cpu1.dtb.hits 13944949 # DTB hits
+system.cpu1.dtb.misses 23311 # DTB misses
+system.cpu1.dtb.accesses 13968260 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 11206823 # ITB inst hits
-system.cpu1.itb.inst_misses 4156 # ITB inst misses
+system.cpu1.itb.inst_hits 14225149 # ITB inst hits
+system.cpu1.itb.inst_misses 5020 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1190 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1294 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 2956 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 3363 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 11210979 # ITB inst accesses
-system.cpu1.itb.hits 11206823 # DTB hits
-system.cpu1.itb.misses 4156 # DTB misses
-system.cpu1.itb.accesses 11210979 # DTB accesses
-system.cpu1.numCycles 147611080 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 14230169 # ITB inst accesses
+system.cpu1.itb.hits 14225149 # DTB hits
+system.cpu1.itb.misses 5020 # DTB misses
+system.cpu1.itb.accesses 14230169 # DTB accesses
+system.cpu1.numCycles 502333604 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 31966977 # Number of instructions committed
-system.cpu1.committedOps 38077351 # Number of ops (including micro ops) committed
-system.cpu1.discardedOps 1608279 # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends 39953 # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles 2144312243 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi 4.617611 # CPI: cycles per instruction
-system.cpu1.ipc 0.216562 # IPC: instructions per cycle
+system.cpu1.committedInsts 33559332 # Number of instructions committed
+system.cpu1.committedOps 40204034 # Number of ops (including micro ops) committed
+system.cpu1.discardedOps 2027525 # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends 40422 # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles 4816582490 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi 14.968522 # CPI: cycles per instruction
+system.cpu1.ipc 0.066807 # IPC: instructions per cycle
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 40481 # number of quiesce instructions executed
-system.cpu1.tickCycles 117794272 # Number of cycles that the object actually ticked
-system.cpu1.idleCycles 29816808 # Total number of cycles that the object has spent stopped
-system.cpu1.icache.tags.replacements 791766 # number of replacements
-system.cpu1.icache.tags.tagsinuse 480.612166 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 10411414 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 792278 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 13.141112 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 82581306250 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.612166 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938696 # Average percentage of cache occupancy
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-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8382.930233 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 4984.415485 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 4984.415485 # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 26584.559766 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 26584.559766 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 26584.559766 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 26584.559766 # average overall miss latency
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+system.cpu1.toL2Bus.trans_dist::UpgradeReq 52848 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 23732 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 50462 # Transaction distribution
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+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution
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+system.cpu1.toL2Bus.trans_dist::ReadExResp 137938 # Transaction distribution
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+system.cpu1.toL2Bus.pkt_size::total 94394240 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 607829 # Total snoops (count)
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+system.cpu1.toL2Bus.snoop_fanout::mean 5.277710 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.447870 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
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+system.cpu1.toL2Bus.snoop_fanout::6 556287 27.77% 100.00% # Request fanout histogram
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+system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 46353997 # Layer occupancy (ticks)
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+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2015 # number of hwpf removed because MSHR allocated
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+system.cpu1.l2cache.tags.avg_refs 6.131765 # Average number of references to valid blocks.
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+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29712.661280 # average overall miss latency
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+system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
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+system.cpu1.dcache.demand_avg_miss_latency::total 14719.911707 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14719.911707 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 14719.911707 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 268002 # number of writebacks
-system.cpu1.dcache.writebacks::total 268002 # number of writebacks
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-system.cpu1.dcache.ReadReq_mshr_hits::total 36395 # number of ReadReq MSHR hits
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-system.cpu1.dcache.ReadReq_mshr_misses::total 204925 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 125526 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 125526 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 10716 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 10716 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 10087 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 10087 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.inst 330451 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 330451 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.inst 330451 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 330451 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2412502275 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2412502275 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 4153602004 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4153602004 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 68123500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 68123500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 30103201 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30103201 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 6566104279 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 6566104279 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 6566104279 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 6566104279 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11993503000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11993503000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 24672579152 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 24672579152 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 36666082152 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 36666082152 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.031385 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.031385 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.027020 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027020 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.120144 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120144 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.113157 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113157 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.029570 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.029570 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.029570 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.029570 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11772.610833 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11772.610833 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 33089.575100 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33089.575100 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 6357.176185 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6357.176185 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 2984.356201 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 2984.356201 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 19870.129850 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19870.129850 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 19870.129850 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19870.129850 # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 242023 # number of writebacks
+system.cpu1.dcache.writebacks::total 242023 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 36547 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 36547 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 129246 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 129246 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 45 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.inst 165793 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 165793 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.inst 165793 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 165793 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 197976 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 197976 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 156757 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 156757 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 11798 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11798 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 13643 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 13643 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.inst 354733 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 354733 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.inst 354733 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 354733 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2204262298 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2204262298 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2289972148 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2289972148 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 187457749 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 187457749 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 286173083 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 286173083 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 767000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 767000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4494234446 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 4494234446 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4494234446 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 4494234446 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 183748244745 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183748244745 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 34481816713 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34481816713 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 218230061458 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 218230061458 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.029952 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029952 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.030695 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030695 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.123814 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.123814 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.143277 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.143277 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.030276 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.030276 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.030276 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.030276 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11133.987443 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11133.987443 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14608.420345 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14608.420345 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 15888.942956 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15888.942956 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 20975.817855 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20975.817855 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12669.344115 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12669.344115 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12669.344115 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12669.344115 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 722335941002 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 722335941002 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 722335941002 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 722335941002 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1759208062571 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1759208062571 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1759208062571 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1759208062571 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 2.566439 # Number of seconds simulated
-sim_ticks 2566439177500 # Number of ticks simulated
-final_tick 2566439177500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.566404 # Number of seconds simulated
+sim_ticks 2566404096500 # Number of ticks simulated
+final_tick 2566404096500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 109798 # Simulator instruction rate (inst/s)
-host_op_rate 132178 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4650508258 # Simulator tick rate (ticks/s)
-host_mem_usage 408644 # Number of bytes of host memory used
-host_seconds 551.86 # Real time elapsed on the host
-sim_insts 60593470 # Number of instructions simulated
-sim_ops 72944147 # Number of ops (including micro ops) simulated
+host_inst_rate 108919 # Simulator instruction rate (inst/s)
+host_op_rate 131120 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4613194748 # Simulator tick rate (ticks/s)
+host_mem_usage 411228 # Number of bytes of host memory used
+host_seconds 556.32 # Real time elapsed on the host
+sim_insts 60593541 # Number of instructions simulated
+sim_ops 72944224 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.realview.nvmem.bytes_read::cpu.inst 256 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu.inst 100 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 100 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 1664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 10079960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 131191960 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1001344 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1001344 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3811328 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 10080024 # Number of bytes read from this memory
+system.physmem.bytes_read::total 131192344 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1001408 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1001408 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3810496 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.inst 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6827400 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6826568 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 26 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 157525 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15296364 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59552 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 157526 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15296370 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59539 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.inst 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813570 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47190103 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 524 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 813557 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47190748 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 648 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 3927605 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51118281 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 390169 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 390169 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1485065 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.inst 1175197 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2660262 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1485065 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47190103 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 524 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 3927684 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51119130 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 390199 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 390199 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1484761 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.inst 1175213 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2659974 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1484761 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47190748 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 648 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 5102802 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53778543 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15296364 # Number of read requests accepted
-system.physmem.writeReqs 813570 # Number of write requests accepted
-system.physmem.readBursts 15296364 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 813570 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 978868736 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 98560 # Total number of bytes read from write queue
-system.physmem.bytesWritten 6836224 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 131191960 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 6827400 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 1540 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 706728 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 4670 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 955903 # Per bank write bursts
-system.physmem.perBankRdBursts::1 955584 # Per bank write bursts
+system.physmem.bw_total::cpu.inst 5102897 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53779104 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15296370 # Number of read requests accepted
+system.physmem.writeReqs 813557 # Number of write requests accepted
+system.physmem.readBursts 15296370 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 813557 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 978862336 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 105344 # Total number of bytes read from write queue
+system.physmem.bytesWritten 6837568 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 131192344 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 6826568 # Total written bytes from the system interface side
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+system.physmem.mergedWrBursts 706692 # Number of DRAM write bursts merged with an existing one
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system.physmem.perBankRdBursts::2 955711 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2566437420000 # Total gap between requests
+system.physmem.totGap 2566402308000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 18 # Read request sizes (log2)
system.physmem.readPktSize::3 15138826 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 157520 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 754018 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1014534 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 971.583959 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 905.812030 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 204.103928 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 21965 2.17% 2.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 22634 2.23% 4.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 8771 0.86% 5.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2477 0.24% 5.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2600 0.26% 5.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1707 0.17% 5.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 8766 0.86% 6.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1031 0.10% 6.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 944583 93.11% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1014534 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6199 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 2467.302629 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 115861.516346 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-524287 6194 99.92% 99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6199 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6199 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.231166 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.203067 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.975146 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 2381 38.41% 38.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 18 0.29% 38.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 3787 61.09% 99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 12 0.19% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6199 # Writes before turning the bus around for reads
-system.physmem.totQLat 394563558000 # Total ticks spent queuing
-system.physmem.totMemAccLat 681341508000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 76474120000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 25797.20 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 1014578 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 971.536840 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 905.616961 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 204.240777 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 22129 2.18% 2.18% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::384-511 2465 0.24% 5.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2547 0.25% 5.76% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1024-1151 944659 93.11% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1014578 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6201 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 2466.490405 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 89690.748368 # Reads before turning the bus around for writes
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+system.physmem.rdPerTurnAround::786432-1.04858e+06 2 0.03% 99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06 1 0.02% 99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2.62144e+06-2.88358e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::6.02931e+06-6.29146e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 6201 # Reads before turning the bus around for writes
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+system.physmem.wrPerTurnAround::mean 17.228995 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.200624 # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::18 3771 60.81% 99.68% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::22 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6201 # Writes before turning the bus around for reads
+system.physmem.totQLat 395011426750 # Total ticks spent queuing
+system.physmem.totMemAccLat 681787501750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 76473620000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 25826.65 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44547.20 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 44576.65 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 381.41 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.66 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 51.12 # Average system read bandwidth in MiByte/s
system.physmem.busUtil 3.00 # Data bus utilization in percentage
system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 6.61 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 26.40 # Average write queue length when enqueuing
-system.physmem.readRowHits 14297661 # Number of row buffer hits during reads
-system.physmem.writeRowHits 89445 # Number of row buffer hits during writes
+system.physmem.avgRdQLen 6.27 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.27 # Average write queue length when enqueuing
+system.physmem.readRowHits 14297539 # Number of row buffer hits during reads
+system.physmem.writeRowHits 89444 # Number of row buffer hits during writes
system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 83.72 # Row buffer hit rate for writes
-system.physmem.avgGap 159307.76 # Average gap between requests
+system.physmem.writeRowHitRate 83.70 # Row buffer hit rate for writes
+system.physmem.avgGap 159305.64 # Average gap between requests
system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2209628504250 # Time in different power states
-system.physmem.memoryStateTime::REF 85698860000 # Time in different power states
+system.physmem.memoryStateTime::IDLE 2209544766500 # Time in different power states
+system.physmem.memoryStateTime::REF 85697820000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 271106544500 # Time in different power states
+system.physmem.memoryStateTime::ACT 271160177250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 54713053 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 16348871 # Transaction distribution
-system.membus.trans_dist::ReadResp 16348871 # Transaction distribution
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+system.membus.trans_dist::ReadResp 16348869 # Transaction distribution
system.membus.trans_dist::WriteReq 763365 # Transaction distribution
system.membus.trans_dist::WriteResp 763365 # Transaction distribution
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-system.membus.trans_dist::UpgradeResp 4670 # Transaction distribution
-system.membus.trans_dist::ReadExReq 131585 # Transaction distribution
-system.membus.trans_dist::ReadExResp 131585 # Transaction distribution
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+system.membus.trans_dist::Writeback 59539 # Transaction distribution
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+system.membus.trans_dist::UpgradeResp 4678 # Transaction distribution
+system.membus.trans_dist::ReadExReq 131592 # Transaction distribution
+system.membus.trans_dist::ReadExResp 131592 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 8 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3800 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1892024 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4278902 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1892039 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4278915 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 34556534 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390502 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 256 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7600 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16908832 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19307194 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 140417722 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 140417722 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1781248000 # Layer occupancy (ticks)
+system.membus.pkt_count::total 34556547 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390498 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 256 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7600 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16908384 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19306742 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 140417270 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 219423 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 219423 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 219423 # Request fanout histogram
+system.membus.reqLayer0.occupancy 1783264500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3519500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 3414000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer6.occupancy 17618629000 # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy 17618330500 # Layer occupancy (ticks)
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4827707725 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 4827152764 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 37448813750 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 37437958000 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.iobus.throughput 48121550 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 16322172 # Transaction distribution
-system.iobus.trans_dist::ReadResp 16322172 # Transaction distribution
+system.iobus.trans_dist::ReadReq 16322171 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16322171 # Transaction distribution
system.iobus.trans_dist::WriteReq 8178 # Transaction distribution
system.iobus.trans_dist::WriteResp 8178 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 524 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2383068 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2383066 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 32660700 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1048 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 2390502 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 123501030 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 123501030 # Total data (bytes)
+system.iobus.pkt_count::total 32660698 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1048 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 2390498 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 123501026 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 524000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2374890000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 2374888000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 38181688250 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 38185527000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 12541574 # Number of BP lookups
-system.cpu.branchPred.condPredicted 9090690 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1061681 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 8536244 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 6183587 # Number of BTB hits
+system.cpu.branchPred.lookups 12550628 # Number of BP lookups
+system.cpu.branchPred.condPredicted 9093116 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1061685 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 8575859 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 6183324 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 72.439202 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1558068 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 139509 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 72.101512 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1560078 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 139853 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 13629654 # DTB read hits
-system.cpu.dtb.read_misses 33608 # DTB read misses
-system.cpu.dtb.write_hits 11376786 # DTB write hits
-system.cpu.dtb.write_misses 3775 # DTB write misses
+system.cpu.dtb.read_hits 13629467 # DTB read hits
+system.cpu.dtb.read_misses 33605 # DTB read misses
+system.cpu.dtb.write_hits 11376627 # DTB write hits
+system.cpu.dtb.write_misses 3703 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 3449 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 1586 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 251 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 3447 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 1539 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 593 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 13663262 # DTB read accesses
-system.cpu.dtb.write_accesses 11380561 # DTB write accesses
+system.cpu.dtb.read_accesses 13663072 # DTB read accesses
+system.cpu.dtb.write_accesses 11380330 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 25006440 # DTB hits
-system.cpu.dtb.misses 37383 # DTB misses
-system.cpu.dtb.accesses 25043823 # DTB accesses
+system.cpu.dtb.hits 25006094 # DTB hits
+system.cpu.dtb.misses 37308 # DTB misses
+system.cpu.dtb.accesses 25043402 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.inst_hits 22903214 # ITB inst hits
-system.cpu.itb.inst_misses 9061 # ITB inst misses
+system.cpu.itb.inst_hits 22908933 # ITB inst hits
+system.cpu.itb.inst_misses 9079 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2388 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2384 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 5760 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 5702 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 22912275 # ITB inst accesses
-system.cpu.itb.hits 22903214 # DTB hits
-system.cpu.itb.misses 9061 # DTB misses
-system.cpu.itb.accesses 22912275 # DTB accesses
-system.cpu.numCycles 572663270 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 22918012 # ITB inst accesses
+system.cpu.itb.hits 22908933 # DTB hits
+system.cpu.itb.misses 9079 # DTB misses
+system.cpu.itb.accesses 22918012 # DTB accesses
+system.cpu.numCycles 572551547 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 60593470 # Number of instructions committed
-system.cpu.committedOps 72944147 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 3225433 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.committedInsts 60593541 # Number of instructions committed
+system.cpu.committedOps 72944224 # Number of ops (including micro ops) committed
+system.cpu.discardedOps 3228444 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 77492 # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles 4562060973 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi 9.450907 # CPI: cycles per instruction
-system.cpu.ipc 0.105810 # IPC: instructions per cycle
+system.cpu.quiesceCycles 4562038068 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi 9.449052 # CPI: cycles per instruction
+system.cpu.ipc 0.105831 # IPC: instructions per cycle
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 82978 # number of quiesce instructions executed
-system.cpu.tickCycles 466702382 # Number of cycles that the object actually ticked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 71285625 # Throughput (bytes/s)
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-system.cpu.toL2Bus.trans_dist::ReadResp 3182018 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::WriteReq 763365 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 763365 # Transaction distribution
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-system.cpu.toL2Bus.trans_dist::ReadExResp 247467 # Transaction distribution
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+system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
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system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
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+system.cpu.toL2Bus.respLayer2.occupancy 18027487 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
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-system.cpu.l2cache.tags.warmup_cycle 2524856942500 # Cycle when the warmup percentage was hit.
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+system.cpu.l2cache.tags.tagsinuse 51567.943403 # Cycle average of tags in use
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-system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.046623 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.046623 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.043899 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043899 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst 0.041987 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.041987 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst 0.041987 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.041987 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15135.571388 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15135.571388 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 46644.860424 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 46644.860424 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13968.261270 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13968.261270 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 31191.414129 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31191.414129 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 31191.414129 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31191.414129 # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.inst 22276744 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 22276744 # number of demand (read+write) accesses
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+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043818 # miss rate for LoadLockedReq accesses
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+system.cpu.dcache.demand_miss_rate::total 0.041986 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst 0.041986 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.041986 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15147.785129 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15147.785129 # average ReadReq miss latency
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+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13990.368664 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 31199.000816 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31199.000816 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 31199.000816 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31199.000816 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 600964 # number of writebacks
-system.cpu.dcache.writebacks::total 600964 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 80923 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 80923 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 226176 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 226176 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 72 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 72 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst 307099 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 307099 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst 307099 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 307099 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 377809 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 377809 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 250438 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 250438 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 10798 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 10798 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst 628247 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 628247 # number of demand (read+write) MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total 628247 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4823958811 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4823958811 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10813361832 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 10813361832 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 129211000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 129211000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 15637320643 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 15637320643 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 15637320643 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 15637320643 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182632094750 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182632094750 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 26058171145 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26058171145 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208690265895 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 208690265895 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.031343 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031343 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks 600919 # number of writebacks
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+system.cpu.dcache.LoadLockedReq_mshr_hits::total 71 # number of LoadLockedReq MSHR hits
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+system.cpu.dcache.overall_mshr_hits::total 307161 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 377720 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 377720 # number of ReadReq MSHR misses
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+system.cpu.dcache.overall_mshr_misses::total 628159 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4824316311 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4824316311 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10814527330 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 10814527330 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 129220000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 129220000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 15638843641 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 15638843641 # number of demand (read+write) MSHR miss cycles
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+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182633838500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182633838500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 26058035692 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26058035692 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208691874192 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 208691874192 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.031335 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031335 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.024498 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024498 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.043608 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.043608 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.028202 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.028202 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.028202 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.028202 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12768.247477 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12768.247477 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 43177.799823 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43177.799823 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11966.197444 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11966.197444 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24890.402410 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 24890.402410 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24890.402410 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24890.402410 # average overall mshr miss latency
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.043531 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.043531 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.028198 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.028198 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.028198 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.028198 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12772.202454 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12772.202454 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 43182.281234 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43182.281234 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11988.125058 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11988.125058 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24896.313897 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24896.313897 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24896.313897 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24896.313897 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736623648250 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1736623648250 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736623648250 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1736623648250 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1737063641000 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1737063641000 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1737063641000 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1737063641000 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 2.542203 # Number of seconds simulated
-sim_ticks 2542202956000 # Number of ticks simulated
-final_tick 2542202956000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.542157 # Number of seconds simulated
+sim_ticks 2542156879500 # Number of ticks simulated
+final_tick 2542156879500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 40853 # Simulator instruction rate (inst/s)
-host_op_rate 49218 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1721973071 # Simulator tick rate (ticks/s)
-host_mem_usage 411692 # Number of bytes of host memory used
-host_seconds 1476.33 # Real time elapsed on the host
-sim_insts 60311945 # Number of instructions simulated
-sim_ops 72661478 # Number of ops (including micro ops) simulated
+host_inst_rate 45011 # Simulator instruction rate (inst/s)
+host_op_rate 54228 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1897222602 # Simulator tick rate (ticks/s)
+host_mem_usage 464684 # Number of bytes of host memory used
+host_seconds 1339.94 # Real time elapsed on the host
+sim_insts 60311972 # Number of instructions simulated
+sim_ops 72661518 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.realview.nvmem.bytes_read::cpu.inst 48 # Number of bytes read from this memory
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 640 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 798576 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9072728 # Number of bytes read from this memory
-system.physmem.bytes_read::total 130982664 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 798576 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 798576 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 798448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9072920 # Number of bytes read from this memory
+system.physmem.bytes_read::total 130982728 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 798448 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 798448 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3743232 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
system.physmem.bytes_written::total 6759304 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 10 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 14991 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 141787 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15295607 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 14989 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 141790 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15295608 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 58488 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47639992 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.clcd 47640855 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 252 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 314128 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3568845 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51523292 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 314128 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 314128 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1472436 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1186401 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2658837 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1472436 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47639992 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 314083 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3568985 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51524251 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 314083 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 314083 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1472463 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1186422 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2658885 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1472463 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47640855 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 314128 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4755246 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54182129 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15295607 # Number of read requests accepted
+system.physmem.bw_total::cpu.inst 314083 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4755408 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 54183136 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15295608 # Number of read requests accepted
system.physmem.writeReqs 812506 # Number of write requests accepted
-system.physmem.readBursts 15295607 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 15295608 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 812506 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 976934144 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 1984704 # Total number of bytes read from write queue
-system.physmem.bytesWritten 6778304 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 130982664 # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM 977064192 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 1854720 # Total number of bytes read from write queue
+system.physmem.bytesWritten 6781120 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 130982728 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 6759304 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 31011 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 706576 # Number of DRAM write bursts merged with an existing one
+system.physmem.servicedByWrQ 28980 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 706520 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 4612 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 955786 # Per bank write bursts
+system.physmem.perBankRdBursts::0 955787 # Per bank write bursts
system.physmem.perBankRdBursts::1 955478 # Per bank write bursts
-system.physmem.perBankRdBursts::2 953003 # Per bank write bursts
-system.physmem.perBankRdBursts::3 951059 # Per bank write bursts
-system.physmem.perBankRdBursts::4 958601 # Per bank write bursts
-system.physmem.perBankRdBursts::5 955602 # Per bank write bursts
-system.physmem.perBankRdBursts::6 952653 # Per bank write bursts
-system.physmem.perBankRdBursts::7 950407 # Per bank write bursts
-system.physmem.perBankRdBursts::8 956154 # Per bank write bursts
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system.physmem.perBankRdBursts::9 955874 # Per bank write bursts
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+system.physmem.perBankRdBursts::11 950200 # Per bank write bursts
system.physmem.perBankRdBursts::12 956166 # Per bank write bursts
system.physmem.perBankRdBursts::13 955918 # Per bank write bursts
-system.physmem.perBankRdBursts::14 953918 # Per bank write bursts
-system.physmem.perBankRdBursts::15 950940 # Per bank write bursts
-system.physmem.perBankWrBursts::0 6546 # Per bank write bursts
-system.physmem.perBankWrBursts::1 6352 # Per bank write bursts
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-system.physmem.perBankWrBursts::4 6421 # Per bank write bursts
-system.physmem.perBankWrBursts::5 6701 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6665 # Per bank write bursts
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-system.physmem.perBankWrBursts::8 6966 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6759 # Per bank write bursts
-system.physmem.perBankWrBursts::10 6421 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6055 # Per bank write bursts
-system.physmem.perBankWrBursts::12 7037 # Per bank write bursts
-system.physmem.perBankWrBursts::13 6645 # Per bank write bursts
-system.physmem.perBankWrBursts::14 6920 # Per bank write bursts
-system.physmem.perBankWrBursts::15 6806 # Per bank write bursts
+system.physmem.perBankRdBursts::14 953812 # Per bank write bursts
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+system.physmem.perBankWrBursts::10 6424 # Per bank write bursts
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+system.physmem.perBankWrBursts::14 6915 # Per bank write bursts
+system.physmem.perBankWrBursts::15 6799 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2542201638000 # Total gap between requests
+system.physmem.totGap 2542155562500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 18 # Read request sizes (log2)
system.physmem.readPktSize::3 15138826 # Read request sizes (log2)
system.physmem.readPktSize::4 3351 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 153412 # Read request sizes (log2)
+system.physmem.readPktSize::6 153413 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 754018 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 58488 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1110293 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1010606 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 973.388688 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 909.020446 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 200.819397 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 22711 2.25% 2.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 19828 1.96% 4.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 8563 0.85% 5.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2249 0.22% 5.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2594 0.26% 5.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1688 0.17% 5.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 8931 0.88% 6.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 959 0.09% 6.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 943083 93.32% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1010606 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6196 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 2463.620239 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 113702.310017 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-524287 6191 99.92% 99.92% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 1010646 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 973.481627 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 909.246732 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 200.676766 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 22575 2.23% 2.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 19975 1.98% 4.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 8601 0.85% 5.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2200 0.22% 5.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2445 0.24% 5.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1700 0.17% 5.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 8928 0.88% 6.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 928 0.09% 6.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 943294 93.34% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1010646 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6195 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 2464.343987 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 113708.986245 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287 6190 99.92% 99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6196 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6196 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.093447 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.042337 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.354685 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 3441 55.54% 55.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 45 0.73% 56.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 1714 27.66% 83.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 868 14.01% 97.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 47 0.76% 98.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 22 0.36% 99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 27 0.44% 99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 21 0.34% 99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 10 0.16% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6196 # Writes before turning the bus around for reads
-system.physmem.totQLat 395449280750 # Total ticks spent queuing
-system.physmem.totMemAccLat 681660455750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 76322980000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 25906.31 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 6195 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6195 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.103309 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.049475 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.400786 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 3455 55.77% 55.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 44 0.71% 56.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 1683 27.17% 83.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 856 13.82% 97.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 62 1.00% 98.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 32 0.52% 98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 30 0.48% 99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 14 0.23% 99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 13 0.21% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 3 0.05% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 1 0.02% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6195 # Writes before turning the bus around for reads
+system.physmem.totQLat 395458190750 # Total ticks spent queuing
+system.physmem.totMemAccLat 681707465750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 76333140000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 25903.44 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44656.31 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 384.29 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 44653.44 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 384.34 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 51.52 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s
system.physmem.busUtil 3.02 # Data bus utilization in percentage
system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 6.20 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.61 # Average write queue length when enqueuing
-system.physmem.readRowHits 14269193 # Number of row buffer hits during reads
-system.physmem.writeRowHits 90708 # Number of row buffer hits during writes
+system.physmem.avgRdQLen 7.09 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing
+system.physmem.readRowHits 14271218 # Number of row buffer hits during reads
+system.physmem.writeRowHits 90719 # Number of row buffer hits during writes
system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 85.63 # Row buffer hit rate for writes
-system.physmem.avgGap 157821.19 # Average gap between requests
-system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2194513894000 # Time in different power states
-system.physmem.memoryStateTime::REF 84889480000 # Time in different power states
+system.physmem.writeRowHitRate 85.60 # Row buffer hit rate for writes
+system.physmem.avgGap 157818.32 # Average gap between requests
+system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 2194559119750 # Time in different power states
+system.physmem.memoryStateTime::REF 84888180000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 262799464750 # Time in different power states
+system.physmem.memoryStateTime::ACT 262709081500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 55125441 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 16348039 # Transaction distribution
-system.membus.trans_dist::ReadResp 16348039 # Transaction distribution
+system.membus.trans_dist::ReadReq 16348037 # Transaction distribution
+system.membus.trans_dist::ReadResp 16348037 # Transaction distribution
system.membus.trans_dist::WriteReq 763357 # Transaction distribution
system.membus.trans_dist::WriteResp 763357 # Transaction distribution
system.membus.trans_dist::Writeback 58488 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4612 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4612 # Transaction distribution
-system.membus.trans_dist::ReadExReq 131651 # Transaction distribution
-system.membus.trans_dist::ReadExResp 131651 # Transaction distribution
+system.membus.trans_dist::ReadExReq 131654 # Transaction distribution
+system.membus.trans_dist::ReadExResp 131654 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 6 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889330 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276174 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889332 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276176 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 34553806 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631440 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19029530 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 140140058 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 140140058 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1558440500 # Layer occupancy (ticks)
+system.membus.pkt_count::total 34553808 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631504 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19029594 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 140140122 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 216513 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 216513 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 216513 # Request fanout histogram
+system.membus.reqLayer0.occupancy 1556318500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer1.occupancy 3500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3512000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 3760500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer6.occupancy 17513415500 # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy 17512345000 # Layer occupancy (ticks)
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4726913870 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 4726136292 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 37423565460 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 37419189712 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.iobus.throughput 48580309 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution
system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution
system.iobus.trans_dist::WriteReq 8176 # Transaction distribution
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 123501006 # Total data (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 38173420540 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 38173439288 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 13201290 # Number of BP lookups
-system.cpu.branchPred.condPredicted 9675974 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 704139 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 8377301 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 6024680 # Number of BTB hits
+system.cpu.branchPred.lookups 13200672 # Number of BP lookups
+system.cpu.branchPred.condPredicted 9675464 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 704019 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 8378152 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 6024616 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 71.916719 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1435837 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 30801 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 71.908650 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1435808 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 30777 # Number of incorrect RAS predictions.
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 13156743 # DTB read hits
-system.cpu.checker.dtb.read_misses 7321 # DTB read misses
-system.cpu.checker.dtb.write_hits 11227340 # DTB write hits
+system.cpu.checker.dtb.read_hits 13156766 # DTB read hits
+system.cpu.checker.dtb.read_misses 7319 # DTB read misses
+system.cpu.checker.dtb.write_hits 11227349 # DTB write hits
system.cpu.checker.dtb.write_misses 2193 # DTB write misses
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries 3404 # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_entries 3403 # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dtb.prefetch_faults 180 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 13164064 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 11229533 # DTB write accesses
+system.cpu.checker.dtb.read_accesses 13164085 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 11229542 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 24384083 # DTB hits
-system.cpu.checker.dtb.misses 9514 # DTB misses
-system.cpu.checker.dtb.accesses 24393597 # DTB accesses
+system.cpu.checker.dtb.hits 24384115 # DTB hits
+system.cpu.checker.dtb.misses 9512 # DTB misses
+system.cpu.checker.dtb.accesses 24393627 # DTB accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.checker.itb.inst_hits 61486079 # ITB inst hits
+system.cpu.checker.itb.inst_hits 61486106 # ITB inst hits
system.cpu.checker.itb.inst_misses 4473 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 61490552 # ITB inst accesses
-system.cpu.checker.itb.hits 61486079 # DTB hits
+system.cpu.checker.itb.inst_accesses 61490579 # ITB inst accesses
+system.cpu.checker.itb.hits 61486106 # DTB hits
system.cpu.checker.itb.misses 4473 # DTB misses
-system.cpu.checker.itb.accesses 61490552 # DTB accesses
-system.cpu.checker.numCycles 72947431 # number of cpu cycles simulated
+system.cpu.checker.itb.accesses 61490579 # DTB accesses
+system.cpu.checker.numCycles 72947471 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 31642294 # DTB read hits
-system.cpu.dtb.read_misses 39524 # DTB read misses
-system.cpu.dtb.write_hits 11381361 # DTB write hits
-system.cpu.dtb.write_misses 10135 # DTB write misses
+system.cpu.dtb.read_hits 31644036 # DTB read hits
+system.cpu.dtb.read_misses 39518 # DTB read misses
+system.cpu.dtb.write_hits 11381434 # DTB write hits
+system.cpu.dtb.write_misses 10146 # DTB write misses
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 3437 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.flush_entries 3436 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 314 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 1342 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 31681818 # DTB read accesses
-system.cpu.dtb.write_accesses 11391496 # DTB write accesses
+system.cpu.dtb.read_accesses 31683554 # DTB read accesses
+system.cpu.dtb.write_accesses 11391580 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 43023655 # DTB hits
-system.cpu.dtb.misses 49659 # DTB misses
-system.cpu.dtb.accesses 43073314 # DTB accesses
+system.cpu.dtb.hits 43025470 # DTB hits
+system.cpu.dtb.misses 49664 # DTB misses
+system.cpu.dtb.accesses 43075134 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.inst_hits 24159481 # ITB inst hits
-system.cpu.itb.inst_misses 10516 # ITB inst misses
+system.cpu.itb.inst_hits 24158829 # ITB inst hits
+system.cpu.itb.inst_misses 10513 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2464 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2463 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 4176 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 4177 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 24169997 # ITB inst accesses
-system.cpu.itb.hits 24159481 # DTB hits
-system.cpu.itb.misses 10516 # DTB misses
-system.cpu.itb.accesses 24169997 # DTB accesses
-system.cpu.numCycles 499350041 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 24169342 # ITB inst accesses
+system.cpu.itb.hits 24158829 # DTB hits
+system.cpu.itb.misses 10513 # DTB misses
+system.cpu.itb.accesses 24169342 # DTB accesses
+system.cpu.numCycles 499362415 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 43030629 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 74131140 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 13201290 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 7460517 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 448266810 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1858598 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 133224 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 12550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 145871 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 3032125 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 24158180 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 404816 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 4527 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 495550550 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.179793 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 0.652924 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 43030394 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 74128653 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 13200672 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 7460424 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 448275105 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1858360 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 133126 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 12568 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 145919 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 3031035 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 24157528 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 404783 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 4525 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 495557370 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.179785 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 0.652906 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 454644690 91.75% 91.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 13614673 2.75% 94.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 6391682 1.29% 95.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 20899505 4.22% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 454652495 91.75% 91.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 13614115 2.75% 94.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 6392828 1.29% 95.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 20897932 4.22% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 495550550 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.026437 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.148455 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 35577628 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 424964763 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 30286365 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 4037656 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 684138 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1691487 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 250438 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 80256354 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2078563 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 684138 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 38799814 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 217885603 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 28702319 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 30653900 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 178824776 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 78213523 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 597412 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 61147213 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 42400387 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 160465829 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 14695892 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 82092463 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 364185184 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 97017359 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 495557370 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.026435 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.148447 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 35569711 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 424983346 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 30281377 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 4038894 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 684042 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1691471 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 250415 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 80255110 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 2078434 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 684042 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 38792488 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 217877928 # Number of cycles rename is blocking
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+system.cpu.rename.UnblockCycles 178850866 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 78212678 # Number of instructions processed by rename
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+system.cpu.rename.ROBFullEvents 61152111 # Number of times rename has blocked due to ROB full
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+system.cpu.rename.LQFullEvents 160465834 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 14716938 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 82091302 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 364181024 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 97016550 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 9816 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 75931181 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6161276 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1134052 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 964724 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 8995770 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 14558741 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 12101093 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 791110 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1256144 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 75819284 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1655722 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 93902738 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 178739 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 4397586 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 8688962 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 172255 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 495550550 # Number of insts issued each cycle
+system.cpu.rename.CommittedMaps 75931219 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 6160077 # Number of HB maps that are undone due to squashing
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+system.cpu.rename.tempSerializingInsts 964709 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 9001428 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 14558433 # Number of loads inserted to the mem dependence unit.
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+system.cpu.memDep0.conflictingLoads 791096 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1255692 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 75818942 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1655707 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 93904368 # Number of instructions issued
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+system.cpu.iq.iqSquashedInstsExamined 4397117 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 8687724 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 172240 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::mean 0.189492 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::1 42998311 8.68% 95.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 15714626 3.17% 98.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5641325 1.14% 99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 637755 0.13% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 430560734 86.88% 86.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 43002673 8.68% 95.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 15716973 3.17% 98.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5640247 1.14% 99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 636707 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 495550550 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 495557370 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 4849757 15.79% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 148 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 20356138 66.26% 82.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 5517293 17.96% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 4845097 15.77% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 148 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 20357888 66.27% 82.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 5517607 17.96% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 28518 0.03% 0.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 49538159 52.75% 52.79% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 91859 0.10% 52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 49538039 52.75% 52.78% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 91860 0.10% 52.88% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 52.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 32267131 34.36% 87.25% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 11974960 12.75% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 32268758 34.36% 87.25% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 11975082 12.75% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 93902738 # Type of FU issued
-system.cpu.iq.rate 0.188050 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 30723336 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.327183 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 714225557 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 81867089 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 74968821 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 93904368 # Type of FU issued
+system.cpu.iq.rate 0.188049 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 30720740 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.327149 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 714233003 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 81866264 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 74968812 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 32544 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 12124 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10212 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 124576093 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 124575127 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 21463 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 210027 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 210020 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1045815 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 542 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 6661 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 369450 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1045495 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 540 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 6662 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 369586 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 17074256 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1003626 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 17074158 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1006174 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 684138 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 94162664 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 98281305 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 77651016 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 684042 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 94158200 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 98278744 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 77650660 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 14558741 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 12101093 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1114432 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 20278 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 98196726 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 6661 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 210280 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 275497 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 485777 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 93247730 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 32000327 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 605564 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts 14558433 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 12101238 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1114427 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 20284 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 98194153 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 6662 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 210239 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 275440 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 485679 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 93249449 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 32002025 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 605470 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 176010 # number of nop insts executed
-system.cpu.iew.exec_refs 43889216 # number of memory reference insts executed
-system.cpu.iew.exec_branches 10791342 # Number of branches executed
-system.cpu.iew.exec_stores 11888889 # Number of stores executed
-system.cpu.iew.exec_rate 0.186738 # Inst execution rate
-system.cpu.iew.wb_sent 92183788 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 74979033 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 35465784 # num instructions producing a value
-system.cpu.iew.wb_consumers 52709939 # num instructions consuming a value
+system.cpu.iew.exec_nop 176011 # number of nop insts executed
+system.cpu.iew.exec_refs 43890987 # number of memory reference insts executed
+system.cpu.iew.exec_branches 10791373 # Number of branches executed
+system.cpu.iew.exec_stores 11888962 # Number of stores executed
+system.cpu.iew.exec_rate 0.186737 # Inst execution rate
+system.cpu.iew.wb_sent 92183769 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 74979024 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 35461894 # num instructions producing a value
+system.cpu.iew.wb_consumers 52697256 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.150153 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.672848 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.150150 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.672936 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 3942514 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 3942249 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1483467 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 458978 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 494644570 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.147200 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 0.699335 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 458881 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 494573774 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.147222 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 0.699394 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 457921524 92.58% 92.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 22157230 4.48% 97.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 6973464 1.41% 98.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2402706 0.49% 98.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1803578 0.36% 99.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1042786 0.21% 99.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 592301 0.12% 99.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 490313 0.10% 99.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 1260668 0.25% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 457850390 92.57% 92.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 22155471 4.48% 97.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 6977487 1.41% 98.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2402189 0.49% 98.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1803487 0.36% 99.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1041949 0.21% 99.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 590384 0.12% 99.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 490446 0.10% 99.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 1261971 0.26% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 494644570 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60462326 # Number of instructions committed
-system.cpu.commit.committedOps 72811859 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 494573774 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60462353 # Number of instructions committed
+system.cpu.commit.committedOps 72811899 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 25244569 # Number of memory references committed
-system.cpu.commit.loads 13512926 # Number of loads committed
+system.cpu.commit.refs 25244590 # Number of memory references committed
+system.cpu.commit.loads 13512938 # Number of loads committed
system.cpu.commit.membars 403660 # Number of memory barriers committed
-system.cpu.commit.branches 10308073 # Number of branches committed
+system.cpu.commit.branches 10308077 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 64250122 # Number of committed integer instructions.
+system.cpu.commit.int_insts 64250158 # Number of committed integer instructions.
system.cpu.commit.function_calls 991634 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 47477289 65.21% 65.21% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 87890 0.12% 65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 47477309 65.21% 65.21% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 87889 0.12% 65.33% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.33% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.33% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.33% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.33% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.33% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 13512926 18.56% 83.89% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 11731643 16.11% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 13512938 18.56% 83.89% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 11731652 16.11% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 72811859 # Class of committed instruction
-system.cpu.commit.bw_lim_events 1260668 # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total 72811899 # Class of committed instruction
+system.cpu.commit.bw_lim_events 1261971 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 568287463 # The number of ROB reads
-system.cpu.rob.rob_writes 154414560 # The number of ROB writes
-system.cpu.timesIdled 544007 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 3799491 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4584972685 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60311945 # Number of Instructions Simulated
-system.cpu.committedOps 72661478 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 8.279455 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 8.279455 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.120781 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.120781 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 109116898 # number of integer regfile reads
-system.cpu.int_regfile_writes 47012348 # number of integer regfile writes
+system.cpu.rob.rob_reads 568215140 # The number of ROB reads
+system.cpu.rob.rob_writes 154414029 # The number of ROB writes
+system.cpu.timesIdled 543953 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 3805045 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 4584951345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 60311972 # Number of Instructions Simulated
+system.cpu.committedOps 72661518 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 8.279657 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 8.279657 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.120778 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.120778 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 109116744 # number of integer regfile reads
+system.cpu.int_regfile_writes 47012213 # number of integer regfile writes
system.cpu.fp_regfile_reads 8305 # number of floating regfile reads
system.cpu.fp_regfile_writes 2780 # number of floating regfile writes
-system.cpu.cc_regfile_reads 320404209 # number of cc regfile reads
-system.cpu.cc_regfile_writes 30332896 # number of cc regfile writes
-system.cpu.misc_regfile_reads 605539146 # number of misc regfile reads
-system.cpu.misc_regfile_writes 1173999 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 57498963 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 2604292 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2604292 # Transaction distribution
+system.cpu.cc_regfile_reads 320409321 # number of cc regfile reads
+system.cpu.cc_regfile_writes 30332935 # number of cc regfile writes
+system.cpu.misc_regfile_reads 605119297 # number of misc regfile reads
+system.cpu.misc_regfile_writes 1173998 # number of misc regfile writes
+system.cpu.toL2Bus.trans_dist::ReadReq 2604204 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2604204 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 599976 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 599947 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2952 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 246570 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 246570 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926546 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768452 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27160 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85384 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 7807542 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61456864 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84377274 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37916 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135596 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 146007650 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 146007650 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 166384 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 3090458553 # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::ReadExReq 246567 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 246567 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926460 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768361 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27152 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85364 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 7807337 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61454112 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84373434 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37904 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135564 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 146001014 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 26770 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 2266210 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
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system.cpu.dcache.StoreCondReq_accesses::total 247596 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_miss_rate::total 0.294708 # miss rate for WriteReq accesses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 599976 # number of writebacks
-system.cpu.dcache.writebacks::total 599976 # number of writebacks
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system.cpu.dcache.LoadLockedReq_mshr_hits::total 1233 # number of LoadLockedReq MSHR hits
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-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1231283000 # number of SoftPFReq MSHR miss cycles
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-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140188500 # number of LoadLockedReq MSHR miss cycles
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+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 139261250 # number of LoadLockedReq MSHR miss cycles
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-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182408022250 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26599942575 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26599942575 # number of WriteReq MSHR uncacheable cycles
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-system.cpu.dcache.overall_mshr_uncacheable_latency::total 209007964825 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025370 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025370 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14360895397 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 14360895397 # number of demand (read+write) MSHR miss cycles
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+system.cpu.dcache.overall_mshr_miss_latency::total 15591808647 # number of overall MSHR miss cycles
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+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182406065750 # number of ReadReq MSHR uncacheable cycles
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+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26598901323 # number of WriteReq MSHR uncacheable cycles
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+system.cpu.dcache.overall_mshr_uncacheable_latency::total 209004967073 # number of overall MSHR uncacheable cycles
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+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025368 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024395 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024395 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395812 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395812 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047127 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047127 # mshr miss rate for LoadLockedReq accesses
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+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047128 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047128 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024919 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.024919 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028035 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.028035 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11839.835950 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11839.835950 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43245.360492 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43245.360492 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16606.419853 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16606.419853 # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11925.861336 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11925.861336 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024918 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.024918 # mshr miss rate for demand accesses
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+system.cpu.dcache.overall_mshr_miss_rate::total 0.028034 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11840.179242 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11840.179242 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43275.838319 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43275.838319 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16601.656911 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16601.656911 # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11847.987919 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11847.987919 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26056.301561 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26056.301561 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24935.271892 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24935.271892 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26070.806868 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26070.806868 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24947.452658 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24947.452658 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1736929447540 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1736929447540 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1736978742288 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1736978742288 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 83187 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 83186 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 2.621647 # Number of seconds simulated
-sim_ticks 2621647051000 # Number of ticks simulated
-final_tick 2621647051000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.607932 # Number of seconds simulated
+sim_ticks 2607931908500 # Number of ticks simulated
+final_tick 2607931908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 56801 # Simulator instruction rate (inst/s)
-host_op_rate 68443 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2377539464 # Simulator tick rate (ticks/s)
-host_mem_usage 411700 # Number of bytes of host memory used
-host_seconds 1102.67 # Real time elapsed on the host
-sim_insts 62632896 # Number of instructions simulated
-sim_ops 75470296 # Number of ops (including micro ops) simulated
+host_inst_rate 43892 # Simulator instruction rate (inst/s)
+host_op_rate 52863 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1823841209 # Simulator tick rate (ticks/s)
+host_mem_usage 431084 # Number of bytes of host memory used
+host_seconds 1429.91 # Real time elapsed on the host
+sim_insts 62761278 # Number of instructions simulated
+sim_ops 75589768 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.realview.nvmem.bytes_read::cpu0.inst 48 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 128 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 176 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 48 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 128 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 176 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 3 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 8 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 18 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 49 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 67 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 18 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 49 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 67 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 18 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 49 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 67 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 516048 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 6568572 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 301968 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 2981560 # Number of bytes read from this memory
-system.physmem.bytes_read::total 131479316 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 516048 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 301968 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 818016 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4189696 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 3029096 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7218832 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 122112 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 457724 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 4608960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 71568 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 618744 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 5382208 # Number of bytes read from this memory
+system.physmem.bytes_read::total 132372740 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 122112 # Number of instructions bytes read from this memory
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+system.physmem.bytes_inst_read::total 193680 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4391552 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 10590 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 102693 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 4761 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 46605 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15303475 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 65464 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 757274 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 822748 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 46196351 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 171 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 196841 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 2505513 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 115183 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1137285 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 50151418 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 196841 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 115183 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 312024 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1598116 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 1155417 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2753548 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1598116 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 46196351 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 171 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 196841 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3660931 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 115183 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 1137300 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 52904966 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15303475 # Number of read requests accepted
-system.physmem.writeReqs 822748 # Number of write requests accepted
-system.physmem.readBursts 15303475 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 822748 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 977402304 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 2020096 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7239040 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 131479316 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 7218832 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 31564 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 709609 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 12033 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 956536 # Per bank write bursts
-system.physmem.perBankRdBursts::1 956505 # Per bank write bursts
-system.physmem.perBankRdBursts::2 953083 # Per bank write bursts
-system.physmem.perBankRdBursts::3 951219 # Per bank write bursts
-system.physmem.perBankRdBursts::4 959451 # Per bank write bursts
-system.physmem.perBankRdBursts::5 955886 # Per bank write bursts
-system.physmem.perBankRdBursts::6 953593 # Per bank write bursts
-system.physmem.perBankRdBursts::7 950807 # Per bank write bursts
-system.physmem.perBankRdBursts::8 956024 # Per bank write bursts
-system.physmem.perBankRdBursts::9 956507 # Per bank write bursts
-system.physmem.perBankRdBursts::10 953309 # Per bank write bursts
-system.physmem.perBankRdBursts::11 950948 # Per bank write bursts
-system.physmem.perBankRdBursts::12 956403 # Per bank write bursts
-system.physmem.perBankRdBursts::13 956390 # Per bank write bursts
-system.physmem.perBankRdBursts::14 954120 # Per bank write bursts
-system.physmem.perBankRdBursts::15 951130 # Per bank write bursts
-system.physmem.perBankWrBursts::0 7301 # Per bank write bursts
-system.physmem.perBankWrBursts::1 7301 # Per bank write bursts
-system.physmem.perBankWrBursts::2 6635 # Per bank write bursts
-system.physmem.perBankWrBursts::3 6826 # Per bank write bursts
-system.physmem.perBankWrBursts::4 7245 # Per bank write bursts
-system.physmem.perBankWrBursts::5 6961 # Per bank write bursts
-system.physmem.perBankWrBursts::6 7187 # Per bank write bursts
-system.physmem.perBankWrBursts::7 6869 # Per bank write bursts
-system.physmem.perBankWrBursts::8 6823 # Per bank write bursts
-system.physmem.perBankWrBursts::9 7301 # Per bank write bursts
-system.physmem.perBankWrBursts::10 6956 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6738 # Per bank write bursts
-system.physmem.perBankWrBursts::12 7232 # Per bank write bursts
-system.physmem.perBankWrBursts::13 7102 # Per bank write bursts
-system.physmem.perBankWrBursts::14 7378 # Per bank write bursts
-system.physmem.perBankWrBursts::15 7255 # Per bank write bursts
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+system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
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+system.physmem.num_writes::total 825902 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 46439298 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 74 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 74 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 46823 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_read::total 50757744 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 46823 # Instruction read bandwidth from this memory (bytes/s)
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+system.physmem.bw_total::cpu0.dtb.walker 74 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 74 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::cpu1.data 1392245 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::total 53603174 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15317443 # Number of read requests accepted
+system.physmem.writeReqs 825902 # Number of write requests accepted
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+system.physmem.writeBursts 825902 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 976329024 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 3987328 # Total number of bytes read from write queue
+system.physmem.bytesWritten 7443968 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 132372740 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 7420688 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 62302 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 709563 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 16003 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 957415 # Per bank write bursts
+system.physmem.perBankRdBursts::1 954356 # Per bank write bursts
+system.physmem.perBankRdBursts::2 951532 # Per bank write bursts
+system.physmem.perBankRdBursts::3 951095 # Per bank write bursts
+system.physmem.perBankRdBursts::4 960453 # Per bank write bursts
+system.physmem.perBankRdBursts::5 954333 # Per bank write bursts
+system.physmem.perBankRdBursts::6 950562 # Per bank write bursts
+system.physmem.perBankRdBursts::7 950350 # Per bank write bursts
+system.physmem.perBankRdBursts::8 957423 # Per bank write bursts
+system.physmem.perBankRdBursts::9 955252 # Per bank write bursts
+system.physmem.perBankRdBursts::10 950399 # Per bank write bursts
+system.physmem.perBankRdBursts::11 949996 # Per bank write bursts
+system.physmem.perBankRdBursts::12 957025 # Per bank write bursts
+system.physmem.perBankRdBursts::13 954231 # Per bank write bursts
+system.physmem.perBankRdBursts::14 950565 # Per bank write bursts
+system.physmem.perBankRdBursts::15 950154 # Per bank write bursts
+system.physmem.perBankWrBursts::0 7537 # Per bank write bursts
+system.physmem.perBankWrBursts::1 7271 # Per bank write bursts
+system.physmem.perBankWrBursts::2 7519 # Per bank write bursts
+system.physmem.perBankWrBursts::3 7339 # Per bank write bursts
+system.physmem.perBankWrBursts::4 7525 # Per bank write bursts
+system.physmem.perBankWrBursts::5 7506 # Per bank write bursts
+system.physmem.perBankWrBursts::6 7304 # Per bank write bursts
+system.physmem.perBankWrBursts::7 7173 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7520 # Per bank write bursts
+system.physmem.perBankWrBursts::9 7613 # Per bank write bursts
+system.physmem.perBankWrBursts::10 6934 # Per bank write bursts
+system.physmem.perBankWrBursts::11 6533 # Per bank write bursts
+system.physmem.perBankWrBursts::12 7225 # Per bank write bursts
+system.physmem.perBankWrBursts::13 7011 # Per bank write bursts
+system.physmem.perBankWrBursts::14 7249 # Per bank write bursts
+system.physmem.perBankWrBursts::15 7053 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2621645657000 # Total gap between requests
+system.physmem.totGap 2607930021000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 59 # Read request sizes (log2)
system.physmem.readPktSize::3 15138841 # Read request sizes (log2)
-system.physmem.readPktSize::4 3426 # Read request sizes (log2)
+system.physmem.readPktSize::4 3437 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 161149 # Read request sizes (log2)
+system.physmem.readPktSize::6 175106 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 757284 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 65464 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1118217 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 965108 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 965171 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1074431 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 973448 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1034951 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2682221 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 2590422 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 3372339 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 127125 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 110466 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 101918 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 97549 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 20170 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 19294 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 19015 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 55 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 68618 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 1022635 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 1020084 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 981701 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 1092290 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 979402 # What read queue length does an incoming req see
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-system.physmem.rdPerTurnAround::mean 2307.281009 # Reads before turning the bus around for writes
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44628.10 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 372.82 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.76 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 50.15 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.75 # Average system write bandwidth in MiByte/s
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+system.physmem.avgRdBW 374.37 # Average DRAM read bandwidth in MiByte/s
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+system.physmem.avgWrBWSys 2.85 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 2.93 # Data bus utilization in percentage
-system.physmem.busUtilRead 2.91 # Data bus utilization in percentage for reads
+system.physmem.busUtil 2.95 # Data bus utilization in percentage
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system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 5.85 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 27.60 # Average write queue length when enqueuing
-system.physmem.readRowHits 14274861 # Number of row buffer hits during reads
-system.physmem.writeRowHits 95334 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 93.47 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 84.26 # Row buffer hit rate for writes
-system.physmem.avgGap 162570.35 # Average gap between requests
-system.physmem.pageHitRate 93.40 # Row buffer hit rate, read and write combined
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-system.physmem.memoryStateTime::REF 87542520000 # Time in different power states
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+system.physmem.writeRowHits 87526 # Number of row buffer hits during writes
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system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 262759227500 # Time in different power states
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system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.realview.nvmem.bytes_read::cpu0.inst 48 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 192 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 48 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 192 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 3 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 12 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 18 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 55 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 73 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 18 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 55 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 73 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 18 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 55 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 73 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 53827614 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 16353736 # Transaction distribution
-system.membus.trans_dist::ReadResp 16353736 # Transaction distribution
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-system.membus.trans_dist::WriteResp 768463 # Transaction distribution
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-system.membus.trans_dist::UpgradeReq 28363 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 16887 # Transaction distribution
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-system.membus.trans_dist::ReadExResp 137251 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384346 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
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system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
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system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
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system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
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system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
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system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
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system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
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system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
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system.membus.respLayer2.utilization 1.4 # Layer utilization (%)
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system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.toL2Bus.throughput 57560286 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 2682607 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2682607 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 768463 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 768463 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 583269 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 27558 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 17275 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 44833 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 1 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 261997 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 261997 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1115277 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2956767 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 14518 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50368 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 879187 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2909426 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 12099 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 38611 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 7976253 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 35510400 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53724619 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21456 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83524 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 28114656 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 29015778 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 17296 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 62840 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 146550569 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 146550569 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 4352184 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 4888594820 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 2503079453 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 2482730980 # Layer occupancy (ticks)
+system.toL2Bus.trans_dist::ReadReq 1650974 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 1650974 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 769202 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 769202 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 213987 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 63464 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 24002 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 87466 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 23286 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 23286 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 760669 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4337396 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 5098065 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 18146443 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 24785598 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 42932041 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 177868 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 783993 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 783993 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 783993 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 2614417508 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 1150691896 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 2659939258 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 9171959 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 29595779 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 1980581418 # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 2244583247 # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer8.occupancy 7797450 # Layer occupancy (ticks)
-system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer9.occupancy 22968355 # Layer occupancy (ticks)
-system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.throughput 47108999 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 16322906 # Transaction distribution
-system.iobus.trans_dist::ReadResp 16322906 # Transaction distribution
-system.iobus.trans_dist::WriteReq 8083 # Transaction distribution
-system.iobus.trans_dist::WriteResp 8083 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30944 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8814 # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq 16322916 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16322916 # Transaction distribution
+system.iobus.trans_dist::WriteReq 8084 # Transaction distribution
+system.iobus.trans_dist::WriteResp 8084 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8832 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1034 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 740 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2384346 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2384368 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 32661978 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40713 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17628 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2068 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 2392641 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 123503169 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 123503169 # Total data (bytes)
-system.iobus.reqLayer0.occupancy 21713000 # Layer occupancy (ticks)
+system.iobus.pkt_count::total 32662000 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17664 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 394 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 2392677 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 123503205 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 4413000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 4422000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 523000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 522000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 440000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy 442000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2376263000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 2376284000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 38168032303 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 38188943909 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
-system.cpu0.branchPred.lookups 8682194 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 6490987 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 415813 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 5217710 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 4131218 # Number of BTB hits
+system.cpu0.branchPred.lookups 6445077 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 4515785 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 302094 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 3732049 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 2838132 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 79.176842 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 908190 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 19748 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 76.047555 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 777958 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 15130 # Number of incorrect RAS predictions.
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 10917771 # DTB read hits
-system.cpu0.dtb.read_misses 23643 # DTB read misses
-system.cpu0.dtb.write_hits 7767808 # DTB write hits
-system.cpu0.dtb.write_misses 8146 # DTB write misses
+system.cpu0.dtb.read_hits 6738270 # DTB read hits
+system.cpu0.dtb.read_misses 20792 # DTB read misses
+system.cpu0.dtb.write_hits 5108254 # DTB write hits
+system.cpu0.dtb.write_misses 4938 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 1721 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 163 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 270 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 1733 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 361 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 598 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 10941414 # DTB read accesses
-system.cpu0.dtb.write_accesses 7775954 # DTB write accesses
+system.cpu0.dtb.perms_faults 640 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 6759062 # DTB read accesses
+system.cpu0.dtb.write_accesses 5113192 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 18685579 # DTB hits
-system.cpu0.dtb.misses 31789 # DTB misses
-system.cpu0.dtb.accesses 18717368 # DTB accesses
+system.cpu0.dtb.hits 11846524 # DTB hits
+system.cpu0.dtb.misses 25730 # DTB misses
+system.cpu0.dtb.accesses 11872254 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 16449037 # ITB inst hits
-system.cpu0.itb.inst_misses 5743 # ITB inst misses
+system.cpu0.itb.inst_hits 11251934 # ITB inst hits
+system.cpu0.itb.inst_misses 5844 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1206 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1215 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 2114 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 2392 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 16454780 # ITB inst accesses
-system.cpu0.itb.hits 16449037 # DTB hits
-system.cpu0.itb.misses 5743 # DTB misses
-system.cpu0.itb.accesses 16454780 # DTB accesses
-system.cpu0.numCycles 110984158 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 11257778 # ITB inst accesses
+system.cpu0.itb.hits 11251934 # DTB hits
+system.cpu0.itb.misses 5844 # DTB misses
+system.cpu0.itb.accesses 11257778 # DTB accesses
+system.cpu0.numCycles 70547986 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 29010417 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 51007104 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 8682194 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 5039408 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 76702951 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1090474 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 80643 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles 23949 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 71996 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 1961272 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 16450117 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 242573 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 2510 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 108396478 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.561251 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 1.057421 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 4766943 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 34365037 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 6445077 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 3616090 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 61724532 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 827468 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 75473 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles 31308 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 103372 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 2299403 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 9118 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 11252710 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 69213 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 1641 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 69423883 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.597378 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 1.081788 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 80471532 74.24% 74.24% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 9354408 8.63% 82.87% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 4228353 3.90% 86.77% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 14342185 13.23% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 50336190 72.51% 72.51% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 6591848 9.50% 82.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 2607109 3.76% 85.76% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 9888736 14.24% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 108396478 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.078229 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.459589 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 24273364 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 59696324 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 21865637 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 2148424 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 412729 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 1100967 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 134603 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 56048449 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 1161275 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 412729 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 26181144 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 23163659 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 11818847 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 22001270 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 24818829 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 54863842 # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts 371818 # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents 4330145 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 2622839 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents 9842391 # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents 13156385 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands 58083982 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 254404471 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 69151408 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 3820 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 54276662 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 3807314 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 540800 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 442723 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 4591136 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 9492850 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 8297955 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 506397 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 589876 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 53569882 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 859573 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 55433156 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 105167 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 2762956 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 5503873 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 84823 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 108396478 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.511393 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 0.864824 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 69423883 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.091357 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.487116 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 6423281 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 48508889 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 12244404 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 1928072 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 319237 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 872011 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 96101 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 34918059 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 1200237 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 319237 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 8391286 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 22294228 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 11033133 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 12128468 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 15257531 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 33562016 # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts 347139 # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents 4725852 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 2951017 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 10590659 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 2752771 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands 34856617 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 154488080 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 39935090 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 3818 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 30135138 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 4721470 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 454498 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 374192 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 4720858 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 6116778 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 5560819 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 585791 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 708239 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 32317524 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 796272 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 32794597 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 169276 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 3620256 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 7615411 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 145849 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 69423883 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.472382 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 0.871380 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 74367725 68.61% 68.61% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 17769290 16.39% 85.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 11558620 10.66% 95.66% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 4256755 3.93% 99.59% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 444079 0.41% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 50273243 72.41% 72.41% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 9200980 13.25% 85.67% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 6622047 9.54% 95.21% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2961360 4.27% 99.47% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 365822 0.53% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 431 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 108396478 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 69423883 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 3788078 33.87% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 172 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 3595287 32.14% 66.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 3801407 33.99% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 2899348 33.55% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 364 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 2954493 34.19% 67.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 2788370 32.26% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 14948 0.03% 0.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 35826739 64.63% 64.66% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 64782 0.12% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 64.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 722 0.00% 64.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 64.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 64.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 64.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 11302035 20.39% 85.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 8223930 14.84% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 14544 0.04% 0.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 20241553 61.72% 61.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 42703 0.13% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 684 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 7058068 21.52% 83.42% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5437045 16.58% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 55433156 # Type of FU issued
-system.cpu0.iq.rate 0.499469 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 11184944 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.201774 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 230540772 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 57191232 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 52885161 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 12129 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 4604 # Number of floating instruction queue writes
+system.cpu0.iq.FU_type_0::total 32794597 # Type of FU issued
+system.cpu0.iq.rate 0.464855 # Inst issue rate
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+system.cpu0.iq.fu_busy_rate 0.263537 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 143812961 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 36735702 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 31078347 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 11966 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 4590 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 3838 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 66595213 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 7939 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 146965 # Number of loads that had data forwarded from stores
+system.cpu0.iq.int_alu_accesses 41415013 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 7615 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 165813 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 634189 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 503 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 3442 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 242149 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 774144 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 762 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 6359 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 332945 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 1082260 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 1003693 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 1087991 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 169554 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 412729 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 7302695 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 6441595 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 54523303 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles 319237 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 7637691 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 6668537 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 33216242 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 9492850 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 8297955 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 524870 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 12318 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 6420937 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 3442 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 134210 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 165432 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 299642 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 55026621 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 11133456 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 374843 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts 6116778 # Number of dispatched load instructions
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+system.cpu0.iew.iewIQFullEvents 10796 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 6648479 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 6359 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 101328 # Number of branches that were predicted taken incorrectly
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+system.cpu0.iew.branchMispredicts 229743 # Number of branch mispredicts detected at execute
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system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 93848 # number of nop insts executed
-system.cpu0.iew.exec_refs 19301977 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 7332190 # Number of branches executed
-system.cpu0.iew.exec_stores 8168521 # Number of stores executed
-system.cpu0.iew.exec_rate 0.495806 # Inst execution rate
-system.cpu0.iew.wb_sent 54039254 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 52888999 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 25110485 # num instructions producing a value
-system.cpu0.iew.wb_consumers 37735585 # num instructions consuming a value
+system.cpu0.iew.exec_nop 102446 # number of nop insts executed
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+system.cpu0.iew.exec_stores 5379801 # Number of stores executed
+system.cpu0.iew.exec_rate 0.459648 # Inst execution rate
+system.cpu0.iew.wb_sent 32232102 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 31082185 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 15739944 # num instructions producing a value
+system.cpu0.iew.wb_consumers 27168343 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.476545 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.665433 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.440582 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.579349 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 2480238 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 774750 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 283305 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 107840192 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.477624 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.224539 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 3250105 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 650423 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 207597 # The number of times a branch was mispredicted
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+system.cpu0.commit.committed_per_cycle::mean 0.427377 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.179796 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 82912194 76.88% 76.88% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 14339479 13.30% 90.18% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 5152045 4.78% 94.96% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 1572745 1.46% 96.42% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 1370622 1.27% 97.69% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 690625 0.64% 98.33% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 401555 0.37% 98.70% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 407085 0.38% 99.08% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 993842 0.92% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 54880088 79.78% 79.78% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 7965099 11.58% 91.36% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 2563469 3.73% 95.09% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 1116854 1.62% 96.71% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 779155 1.13% 97.84% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 426783 0.62% 98.46% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 259327 0.38% 98.84% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 232321 0.34% 99.18% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 565408 0.82% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 107840192 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 43173906 # Number of instructions committed
-system.cpu0.commit.committedOps 51507078 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 68788504 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 24068410 # Number of instructions committed
+system.cpu0.commit.committedOps 29398607 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 16914467 # Number of memory references committed
-system.cpu0.commit.loads 8858661 # Number of loads committed
-system.cpu0.commit.membars 263890 # Number of memory barriers committed
-system.cpu0.commit.branches 7043091 # Number of branches committed
+system.cpu0.commit.refs 10570507 # Number of memory references committed
+system.cpu0.commit.loads 5342633 # Number of loads committed
+system.cpu0.commit.membars 231974 # Number of memory barriers committed
+system.cpu0.commit.branches 4351471 # Number of branches committed
system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 45505753 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 666034 # Number of function calls committed.
+system.cpu0.commit.int_insts 25743783 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 499778 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 34530023 67.04% 67.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 61866 0.12% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 722 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 8858661 17.20% 84.36% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 8055806 15.64% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 18787662 63.91% 63.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult 39754 0.14% 64.04% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.04% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.04% # Class of committed instruction
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system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu0.quiesceCycles 5132257518 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
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-system.cpu0.committedOps 51426336 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 2.575447 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.575447 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.388282 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.388282 # IPC: Total IPC of All Threads
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+system.cpu0.cpi_total 2.941011 # CPI: Total CPI of All Threads
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system.cpu0.fp_regfile_writes 840 # number of floating regfile writes
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-system.cpu0.misc_regfile_writes 593502 # number of misc regfile writes
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-system.cpu0.icache.tags.warmup_cycle 18806389250 # Cycle when the warmup percentage was hit.
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+system.cpu0.toL2Bus.snoops 640729 # Total snoops (count)
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-system.cpu0.icache.ReadReq_avg_miss_latency::total 13849.772824 # average ReadReq miss latency
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+system.cpu0.dcache.tags.tagsinuse 469.059398 # Cycle average of tags in use
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+system.cpu0.dcache.tags.avg_refs 30.315796 # Average number of references to valid blocks.
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system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 63030887 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 63030887 # Number of data accesses
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-system.cpu0.dcache.ReadReq_misses::total 406720 # number of ReadReq misses
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-system.cpu0.dcache.SoftPFReq_misses::total 92142 # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10979 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 10979 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7659 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 7659 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 2627970 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 2627970 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 2720112 # number of overall misses
-system.cpu0.dcache.overall_misses::total 2720112 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5668958645 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 5668958645 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 107130503686 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 107130503686 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 114563996 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 114563996 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44413016 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 44413016 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 112799462331 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 112799462331 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 112799462331 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 112799462331 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 8444174 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 8444174 # number of ReadReq accesses(hits+misses)
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-system.cpu0.dcache.WriteReq_accesses::total 6730517 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 138231 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 138231 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 167950 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 167950 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166738 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 166738 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 15174691 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 15174691 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 15312922 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 15312922 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.048166 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.048166 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330027 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.330027 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.666580 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.666580 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065371 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065371 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.045934 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.045934 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.173181 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.173181 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.177635 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.177635 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13938.234277 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 13938.234277 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48229.827208 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 48229.827208 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10434.829766 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10434.829766 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5798.800888 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5798.800888 # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 42922.659821 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 42922.659821 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41468.683029 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 41468.683029 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 14275 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 1041 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.712776 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.dcache.tags.tag_accesses 20887113 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 20887113 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 4736171 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 4736171 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 3900194 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 3900194 # number of WriteReq hits
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+system.cpu0.dcache.SoftPFReq_hits::total 45240 # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135351 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 135351 # number of LoadLockedReq hits
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+system.cpu0.dcache.StoreCondReq_hits::total 133505 # number of StoreCondReq hits
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+system.cpu0.dcache.ReadReq_misses::total 322447 # number of ReadReq misses
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+system.cpu0.dcache.WriteReq_misses::total 906986 # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data 75027 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total 75027 # number of SoftPFReq misses
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+system.cpu0.dcache.LoadLockedReq_misses::total 10798 # number of LoadLockedReq misses
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+system.cpu0.dcache.StoreCondReq_misses::total 11479 # number of StoreCondReq misses
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+system.cpu0.dcache.demand_misses::total 1229433 # number of demand (read+write) misses
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+system.cpu0.dcache.ReadReq_miss_latency::total 3662752641 # number of ReadReq miss cycles
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+system.cpu0.dcache.WriteReq_miss_latency::total 13080008270 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 182730500 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 182730500 # number of LoadLockedReq miss cycles
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+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 660000 # number of StoreCondFailReq miss cycles
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+system.cpu0.dcache.demand_miss_latency::total 16742760911 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 16742760911 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 16742760911 # number of overall miss cycles
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+system.cpu0.dcache.SoftPFReq_accesses::total 120267 # number of SoftPFReq accesses(hits+misses)
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+system.cpu0.dcache.LoadLockedReq_accesses::total 146149 # number of LoadLockedReq accesses(hits+misses)
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+system.cpu0.dcache.demand_accesses::total 9865798 # number of demand (read+write) accesses
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+system.cpu0.dcache.ReadReq_miss_rate::total 0.063742 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.188673 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.188673 # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.623837 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.623837 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.073884 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.073884 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.079174 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.079174 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.124616 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.124616 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.130628 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.130628 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 11359.239320 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 11359.239320 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14421.400408 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 14421.400408 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16922.624560 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16922.624560 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23823.263699 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23823.263699 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
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+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13618.278435 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 13618.278435 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12835.012887 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 12835.012887 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 1895359 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 9 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 100025 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 18.948853 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 375988 # number of writebacks
-system.cpu0.dcache.writebacks::total 375988 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 193747 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 193747 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 2045363 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 2045363 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 1054 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1054 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 2239110 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 2239110 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 2239110 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 2239110 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 212973 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 212973 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175887 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 175887 # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 54623 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 54623 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9925 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9925 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7659 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 7659 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 388860 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 388860 # number of demand (read+write) MSHR misses
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-system.cpu0.dcache.overall_mshr_misses::total 443483 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2487825853 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2487825853 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7369362883 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7369362883 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1035896777 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1035896777 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 82981003 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 82981003 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29093984 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29093984 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9857188736 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 9857188736 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10893085513 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 10893085513 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13737621002 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13737621002 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 26275689041 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26275689041 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 40013310043 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 40013310043 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025221 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.025221 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026133 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026133 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.395157 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.395157 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059095 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059095 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.045934 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.045934 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025626 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.025626 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028961 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.028961 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11681.414325 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11681.414325 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41898.280618 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41898.280618 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18964.479743 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18964.479743 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8360.806348 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8360.806348 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3798.666144 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3798.666144 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25348.939814 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25348.939814 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24562.577400 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24562.577400 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 228050 # number of writebacks
+system.cpu0.dcache.writebacks::total 228050 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 162419 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 162419 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 762846 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 762846 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 1187 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1187 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 925265 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 925265 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 925265 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 925265 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 160028 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 160028 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 144140 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 144140 # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 44124 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total 44124 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9611 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9611 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 11479 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 11479 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 304168 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 304168 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 348292 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 348292 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1657269084 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1657269084 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 2153079279 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2153079279 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 708295495 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 708295495 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 147083500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147083500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 249287756 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 249287756 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 626000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 626000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 3810348363 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 3810348363 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 4518643858 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 4518643858 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 14541407491 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14541407491 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1345528496 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1345528496 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 15886935987 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 15886935987 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031635 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031635 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029984 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029984 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.366884 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.366884 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065762 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065762 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.079174 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.079174 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030831 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.030831 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.034878 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.034878 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10356.119454 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10356.119454 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14937.416949 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14937.416949 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16052.386343 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16052.386343 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15303.662470 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15303.662470 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21716.853036 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21716.853036 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12527.117787 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12527.117787 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12973.722790 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12973.722790 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 5001209 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 3530067 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 291977 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 3184313 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 2141032 # Number of BTB hits
+system.cpu1.branchPred.lookups 9149866 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 6786400 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 422129 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 5825788 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 4286605 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 67.236858 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 582225 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 13211 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 73.579832 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 927303 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 19424 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 21293354 # DTB read hits
-system.cpu1.dtb.read_misses 17527 # DTB read misses
-system.cpu1.dtb.write_hits 4063342 # DTB write hits
-system.cpu1.dtb.write_misses 3266 # DTB write misses
+system.cpu1.dtb.read_hits 25102636 # DTB read hits
+system.cpu1.dtb.read_misses 30137 # DTB read misses
+system.cpu1.dtb.write_hits 6841685 # DTB write hits
+system.cpu1.dtb.write_misses 6769 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1908 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 789 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 274 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 1912 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 1186 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 694 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 21310881 # DTB read accesses
-system.cpu1.dtb.write_accesses 4066608 # DTB write accesses
+system.cpu1.dtb.perms_faults 731 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 25132773 # DTB read accesses
+system.cpu1.dtb.write_accesses 6848454 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 25356696 # DTB hits
-system.cpu1.dtb.misses 20793 # DTB misses
-system.cpu1.dtb.accesses 25377489 # DTB accesses
+system.cpu1.dtb.hits 31944321 # DTB hits
+system.cpu1.dtb.misses 36906 # DTB misses
+system.cpu1.dtb.accesses 31981227 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 8626509 # ITB inst hits
-system.cpu1.itb.inst_misses 4363 # ITB inst misses
+system.cpu1.itb.inst_hits 16803682 # ITB inst hits
+system.cpu1.itb.inst_misses 6173 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1319 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 2055 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 2309 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 8630872 # ITB inst accesses
-system.cpu1.itb.hits 8626509 # DTB hits
-system.cpu1.itb.misses 4363 # DTB misses
-system.cpu1.itb.accesses 8630872 # DTB accesses
-system.cpu1.numCycles 396849081 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 16809855 # ITB inst accesses
+system.cpu1.itb.hits 16803682 # DTB hits
+system.cpu1.itb.misses 6173 # DTB misses
+system.cpu1.itb.accesses 16809855 # DTB accesses
+system.cpu1.numCycles 436917069 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 18444788 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 25760845 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 5001209 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 2723257 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 375027882 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 802688 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 60706 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles 28139 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 75697 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 1303305 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.CacheLines 8624270 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 181619 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 1774 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 395341861 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.079415 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 0.442124 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 7779761 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 51586006 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 9149866 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 5213908 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 424935366 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 1119898 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 77514 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles 41827 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 113975 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 2395843 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 15405 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 16801187 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 110293 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 1839 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 435919640 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.141195 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 0.582401 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 380851246 96.33% 96.33% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 4867429 1.23% 97.57% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 2340779 0.59% 98.16% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 7282407 1.84% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 407581344 93.50% 93.50% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 9416514 2.16% 95.66% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 4632400 1.06% 96.72% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 14289382 3.28% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 395341861 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.012602 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.064913 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 15111141 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 368322319 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 9619404 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 1988623 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 300374 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 680085 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 102949 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 27336312 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 828595 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 300374 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 16508550 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 196017158 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 17889321 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 9851688 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 154774770 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 26427025 # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts 243114 # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents 56891125 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 39780893 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 150628157 # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents 2138867 # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands 27113530 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 124075273 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 31437770 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 6241 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 24483458 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 2630072 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 642693 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 559165 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 4862604 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 5657845 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 4330093 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 343073 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 498131 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 25260320 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 861912 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 41442639 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 78274 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 1902061 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 3789747 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 92749 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 395341861 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.104827 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 0.383209 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 435919640 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.020942 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.118068 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 9900868 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 404219752 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 17609153 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 3776585 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 413282 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 1053225 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 148821 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 53082842 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 1693858 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 413282 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 13042184 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 210392870 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 23473030 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 17900158 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 170698116 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 51361658 # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts 445811 # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents 60462789 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 44486963 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 161544271 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 5689953 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands 54453588 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 239756743 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 64654520 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 6270 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 48767925 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 5685663 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 754764 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 650155 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 9515727 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 9671211 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 7398216 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 539915 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 877439 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 49754499 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1063600 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 65146152 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 226823 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 4308815 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 9268536 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 164257 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 435919640 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.149445 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 0.502702 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 362283147 91.64% 91.64% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 26570133 6.72% 98.36% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 4792582 1.21% 99.57% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 1496663 0.38% 99.95% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 199327 0.05% 100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 391740283 89.87% 89.87% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 28930464 6.64% 96.50% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 10221316 2.34% 98.85% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 4337467 1.00% 99.84% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 689895 0.16% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 215 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 395341861 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 435919640 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 1195141 5.96% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 685 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 16909984 84.32% 90.29% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 1947822 9.71% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 4426779 17.51% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 691 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 17.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 17782110 70.33% 87.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 3074512 12.16% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 13868 0.03% 0.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 15563362 37.55% 37.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 33954 0.08% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 1648 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 21553207 52.01% 89.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 4276600 10.32% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 14260 0.02% 0.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 32351105 49.66% 49.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 60186 0.09% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 1702 0.00% 49.78% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.78% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.78% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.78% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 25491005 39.13% 88.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 7227894 11.09% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 41442639 # Type of FU issued
-system.cpu1.iq.rate 0.104429 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 20053632 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.483889 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 498337881 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 28019357 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 25018416 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 21164 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 7936 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 6759 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 61468547 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 13856 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 72058 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 65146152 # Type of FU issued
+system.cpu1.iq.rate 0.149104 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 25284092 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.388113 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 591701467 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 55128847 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 48339304 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 21392 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 7974 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 6777 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 90402329 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 13655 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 164874 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 455146 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 306 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 3014 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 163146 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 922858 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 700 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 9957 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 405915 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 15996057 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 1487 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 16016509 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 155340 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 300374 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 87167513 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 92299631 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 26204459 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles 413282 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 90103879 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 101302025 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 50907640 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 5657845 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 4330093 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 630570 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 9334 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 92232105 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 3014 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 83298 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 118271 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 201569 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 41178523 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 21441390 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 243431 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts 9671211 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 7398216 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 775761 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 15322 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 101224655 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 9957 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 133208 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 167801 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 301009 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 64655254 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 25297716 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 454169 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 82227 # number of nop insts executed
-system.cpu1.iew.exec_refs 25682989 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 3899404 # Number of branches executed
-system.cpu1.iew.exec_stores 4241599 # Number of stores executed
-system.cpu1.iew.exec_rate 0.103764 # Inst execution rate
-system.cpu1.iew.wb_sent 41086324 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 25025175 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 11348419 # num instructions producing a value
-system.cpu1.iew.wb_consumers 16538487 # num instructions consuming a value
+system.cpu1.iew.exec_nop 89541 # number of nop insts executed
+system.cpu1.iew.exec_refs 32443779 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 6846575 # Number of branches executed
+system.cpu1.iew.exec_stores 7146063 # Number of stores executed
+system.cpu1.iew.exec_rate 0.147981 # Inst execution rate
+system.cpu1.iew.wb_sent 64439493 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 48346081 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 25811466 # num instructions producing a value
+system.cpu1.iew.wb_consumers 39458467 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.063060 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.686182 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.110653 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.654143 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 1702265 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 769163 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 191007 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 394940200 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.061056 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 0.422241 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 3859068 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 899343 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 275462 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 435139005 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.106498 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 0.626723 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 381244473 96.53% 96.53% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 9114140 2.31% 98.84% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 2236589 0.57% 99.41% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 955406 0.24% 99.65% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 446570 0.11% 99.76% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 403381 0.10% 99.86% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 181575 0.05% 99.91% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 97100 0.02% 99.93% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 260966 0.07% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 413392451 95.00% 95.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 12955608 2.98% 97.98% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 3521257 0.81% 98.79% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1360882 0.31% 99.10% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1313314 0.30% 99.40% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 777449 0.18% 99.58% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 559175 0.13% 99.71% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 305729 0.07% 99.78% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 953140 0.22% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 394940200 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 19609371 # Number of instructions committed
-system.cpu1.commit.committedOps 24113599 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 435139005 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 38843249 # Number of instructions committed
+system.cpu1.commit.committedOps 46341542 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 9369646 # Number of memory references committed
-system.cpu1.commit.loads 5202699 # Number of loads committed
-system.cpu1.commit.membars 162322 # Number of memory barriers committed
-system.cpu1.commit.branches 3698878 # Number of branches committed
+system.cpu1.commit.refs 15740654 # Number of memory references committed
+system.cpu1.commit.loads 8748353 # Number of loads committed
+system.cpu1.commit.membars 195273 # Number of memory barriers committed
+system.cpu1.commit.branches 6419002 # Number of branches committed
system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 21204966 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 385194 # Number of function calls committed.
+system.cpu1.commit.int_insts 41058956 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 553431 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 14709151 61.00% 61.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 33154 0.14% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 1648 0.01% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 5202699 21.58% 82.72% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 4166947 17.28% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 30541068 65.90% 65.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 58118 0.13% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc 1702 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead 8748353 18.88% 84.91% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite 6992301 15.09% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 24113599 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 260966 # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total 46341542 # Class of committed instruction
+system.cpu1.commit.bw_lim_events 953140 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 419589246 # The number of ROB reads
-system.cpu1.rob.rob_writes 52032512 # The number of ROB writes
-system.cpu1.timesIdled 248745 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 1507220 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 4845699469 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 19539732 # Number of Instructions Simulated
-system.cpu1.committedOps 24043960 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 20.309853 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 20.309853 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.049237 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.049237 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 45343306 # number of integer regfile reads
-system.cpu1.int_regfile_writes 15599183 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 5046 # number of floating regfile reads
+system.cpu1.rob.rob_reads 483317632 # The number of ROB reads
+system.cpu1.rob.rob_writes 101136219 # The number of ROB writes
+system.cpu1.timesIdled 117466 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 997429 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 4778390126 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 38773610 # Number of Instructions Simulated
+system.cpu1.committedOps 46271903 # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi 11.268413 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 11.268413 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.088744 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.088744 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 76047297 # number of integer regfile reads
+system.cpu1.int_regfile_writes 30995697 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 4960 # number of floating regfile reads
system.cpu1.fp_regfile_writes 2260 # number of floating regfile writes
-system.cpu1.cc_regfile_reads 139131439 # number of cc regfile reads
-system.cpu1.cc_regfile_writes 9348976 # number of cc regfile writes
-system.cpu1.misc_regfile_reads 454367618 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 623445 # number of misc regfile writes
-system.cpu1.icache.tags.replacements 439266 # number of replacements
-system.cpu1.icache.tags.tagsinuse 497.815366 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 8166304 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 439778 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 18.569151 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 119618152250 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 497.815366 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.972296 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.972296 # Average percentage of cache occupancy
+system.cpu1.cc_regfile_reads 220730482 # number of cc regfile reads
+system.cpu1.cc_regfile_writes 19377985 # number of cc regfile writes
+system.cpu1.misc_regfile_reads 520419201 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 723683 # number of misc regfile writes
+system.cpu1.toL2Bus.trans_dist::ReadReq 2172606 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 1978157 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 758384 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 758384 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 291033 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 272197 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 56199 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 25233 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 54439 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 157045 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 149477 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1093505 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4944143 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17380 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 65233 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 6120261 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 34983760 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 51460526 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 28972 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 118552 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 86591810 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 595717 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 1871452 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 5.290652 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.454063 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5 1327511 70.93% 70.93% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6 543941 29.07% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 1871452 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 2995139487 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 46865000 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer0.occupancy 820984463 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer1.occupancy 2122961296 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer2.occupancy 10148477 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer3.occupancy 36069550 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.cpu1.icache.tags.replacements 546235 # number of replacements
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+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16740.137799 # average UpgradeReq mshr miss latency
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+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average overall mshr miss latency
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+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
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+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu1.dcache.tags.tagsinuse 481.780956 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 12332117 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 381992 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 32.283705 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 70951149500 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.780956 # Average occupied blocks per requestor
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+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 331 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 0.646484 # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses 27770563 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 27770563 # Number of data accesses
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+system.cpu1.dcache.StoreCondReq_hits::total 93451 # number of StoreCondReq hits
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+system.cpu1.dcache.SoftPFReq_misses::total 47536 # number of SoftPFReq misses
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+system.cpu1.dcache.LoadLockedReq_misses::total 14955 # number of LoadLockedReq misses
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+system.cpu1.dcache.StoreCondReq_misses::total 14395 # number of StoreCondReq misses
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+system.cpu1.dcache.demand_misses::total 1329573 # number of demand (read+write) misses
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+system.cpu1.dcache.ReadReq_miss_latency::total 4296873688 # number of ReadReq miss cycles
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+system.cpu1.dcache.WriteReq_miss_latency::total 15627489636 # number of WriteReq miss cycles
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+system.cpu1.dcache.LoadLockedReq_miss_latency::total 254785499 # number of LoadLockedReq miss cycles
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+system.cpu1.dcache.StoreCondReq_miss_latency::total 332075324 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1276000 # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1276000 # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 19924363324 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 19924363324 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 19924363324 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 19924363324 # number of overall miss cycles
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+system.cpu1.dcache.ReadReq_accesses::total 7567904 # number of ReadReq accesses(hits+misses)
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+system.cpu1.dcache.SoftPFReq_accesses::total 72038 # number of SoftPFReq accesses(hits+misses)
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+system.cpu1.dcache.LoadLockedReq_accesses::total 109072 # number of LoadLockedReq accesses(hits+misses)
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+system.cpu1.dcache.StoreCondReq_accesses::total 107846 # number of StoreCondReq accesses(hits+misses)
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+system.cpu1.dcache.demand_accesses::total 13393424 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 13465462 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 13465462 # number of overall (read+write) accesses
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+system.cpu1.dcache.ReadReq_miss_rate::total 0.047870 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.166045 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.166045 # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.659874 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.659874 # miss rate for SoftPFReq accesses
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+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137111 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.133477 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.133477 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.099271 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.099271 # miss rate for demand accesses
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+system.cpu1.dcache.overall_miss_rate::total 0.102270 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11860.806536 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 11860.806536 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16155.817169 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 16155.817169 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17036.810364 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17036.810364 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23068.796388 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23068.796388 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30395.171411 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 30395.171411 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29177.922037 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 29177.922037 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 723 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 6.190871 # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14985.535449 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 14985.535449 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14468.254382 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 14468.254382 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 4991 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 2160220 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 228 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 94010 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 21.890351 # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets 22.978619 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 207281 # number of writebacks
-system.cpu1.dcache.writebacks::total 207281 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 70540 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 70540 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 693700 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 693700 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 500 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 500 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 764240 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 764240 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 764240 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 764240 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116882 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 116882 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 113241 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 113241 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23891 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 23891 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9914 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9914 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9617 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 9617 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 230123 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 230123 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 254014 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 254014 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1203808322 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1203808322 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3988299754 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3988299754 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 341716536 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 341716536 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 60834504 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 60834504 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 33974875 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 33974875 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 12000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 12000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5192108076 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 5192108076 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5533824612 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 5533824612 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168973544758 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168973544758 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 522517625 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 522517625 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 169496062383 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 169496062383 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029366 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029366 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029025 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029025 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.429354 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.429354 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.115231 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.115231 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112836 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112836 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029197 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.029197 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032002 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.032002 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10299.347393 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10299.347393 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35219.573776 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35219.573776 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14303.149136 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 14303.149136 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6136.221908 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6136.221908 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3532.793491 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3532.793491 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 291033 # number of writebacks
+system.cpu1.dcache.writebacks::total 291033 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148293 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 148293 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 797245 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 797245 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1426 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1426 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 945538 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 945538 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 945538 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 945538 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 213982 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 213982 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 170053 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 170053 # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 30328 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total 30328 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13529 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13529 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 14395 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 14395 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 384035 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 384035 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 414363 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 414363 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2231950081 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2231950081 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2569103752 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2569103752 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 638180745 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 638180745 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 208910751 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 208910751 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 302166676 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 302166676 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1220000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1220000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4801053833 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 4801053833 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5439234578 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 5439234578 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 183653885735 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183653885735 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 50893842775 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 50893842775 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 234547728510 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 234547728510 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028275 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.028275 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029191 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029191 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.421000 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.421000 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.124037 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124037 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.133477 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.133477 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028673 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.028673 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030772 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.030772 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10430.550612 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10430.550612 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15107.664975 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15107.664975 # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21042.625462 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21042.625462 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15441.699387 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15441.699387 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20991.085516 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20991.085516 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22562.317004 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22562.317004 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21785.510295 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21785.510295 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12501.604888 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12501.604888 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13126.738097 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13126.738097 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736665659303 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1736665659303 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736665659303 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1736665659303 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736182068909 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1736182068909 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736182068909 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1736182068909 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 52427 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 42962 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 40685 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 50554 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 2.542203 # Number of seconds simulated
-sim_ticks 2542202956000 # Number of ticks simulated
-final_tick 2542202956000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.542157 # Number of seconds simulated
+sim_ticks 2542156879500 # Number of ticks simulated
+final_tick 2542156879500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 47189 # Simulator instruction rate (inst/s)
-host_op_rate 56852 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1989066585 # Simulator tick rate (ticks/s)
-host_mem_usage 412724 # Number of bytes of host memory used
-host_seconds 1278.09 # Real time elapsed on the host
-sim_insts 60311945 # Number of instructions simulated
-sim_ops 72661478 # Number of ops (including micro ops) simulated
+host_inst_rate 53622 # Simulator instruction rate (inst/s)
+host_op_rate 64601 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2260157205 # Simulator tick rate (ticks/s)
+host_mem_usage 463148 # Number of bytes of host memory used
+host_seconds 1124.77 # Real time elapsed on the host
+sim_insts 60311972 # Number of instructions simulated
+sim_ops 72661518 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 640 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
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-system.physmem.bytes_read::cpu.data 9072728 # Number of bytes read from this memory
-system.physmem.bytes_read::total 130982664 # Number of bytes read from this memory
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-system.physmem.bytes_inst_read::total 798576 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 3743232 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
system.physmem.bytes_written::total 6759304 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 10 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
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-system.physmem.num_reads::cpu.data 141787 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 58488 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_inst_read::total 314128 # Instruction read bandwidth from this memory (bytes/s)
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-system.physmem.bw_write::cpu.data 1186401 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2658837 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1472436 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47639992 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 314128 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4755246 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54182129 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15295607 # Number of read requests accepted
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system.physmem.writeReqs 812506 # Number of write requests accepted
-system.physmem.readBursts 15295607 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 812506 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 976934144 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 1984704 # Total number of bytes read from write queue
-system.physmem.bytesWritten 6778304 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 130982664 # Total read bytes from the system interface side
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+system.physmem.bytesReadWrQ 1854720 # Total number of bytes read from write queue
+system.physmem.bytesWritten 6781120 # Total number of bytes written to DRAM
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system.physmem.bytesWrittenSys 6759304 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 31011 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 706576 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 4612 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 955786 # Per bank write bursts
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system.physmem.perBankRdBursts::1 955478 # Per bank write bursts
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system.physmem.perBankRdBursts::9 955874 # Per bank write bursts
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system.physmem.perBankRdBursts::12 956166 # Per bank write bursts
system.physmem.perBankRdBursts::13 955918 # Per bank write bursts
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-system.physmem.perBankWrBursts::15 6806 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2542201638000 # Total gap between requests
+system.physmem.totGap 2542155562500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 18 # Read request sizes (log2)
system.physmem.readPktSize::3 15138826 # Read request sizes (log2)
system.physmem.readPktSize::4 3351 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 153412 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 754018 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 58488 # Write request sizes (log2)
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1010606 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 973.388688 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 909.020446 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 200.819397 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 22711 2.25% 2.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 19828 1.96% 4.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 8563 0.85% 5.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2249 0.22% 5.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2594 0.26% 5.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1688 0.17% 5.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 8931 0.88% 6.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 959 0.09% 6.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 943083 93.32% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1010606 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6196 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 2463.620239 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 113702.310017 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-524287 6191 99.92% 99.92% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 1010646 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 973.481627 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 909.246732 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 200.676766 # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::128-255 19975 1.98% 4.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 8601 0.85% 5.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2200 0.22% 5.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2445 0.24% 5.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1700 0.17% 5.69% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1024-1151 943294 93.34% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1010646 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6195 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 2464.343987 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 113708.986245 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287 6190 99.92% 99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6196 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6196 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.093447 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.042337 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.354685 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 3441 55.54% 55.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 45 0.73% 56.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 1714 27.66% 83.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 868 14.01% 97.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 47 0.76% 98.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 22 0.36% 99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 27 0.44% 99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 21 0.34% 99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 10 0.16% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6196 # Writes before turning the bus around for reads
-system.physmem.totQLat 395449280750 # Total ticks spent queuing
-system.physmem.totMemAccLat 681660455750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 76322980000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 25906.31 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 6195 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6195 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.103309 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.049475 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.400786 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 3455 55.77% 55.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 44 0.71% 56.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 1683 27.17% 83.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 856 13.82% 97.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 62 1.00% 98.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 32 0.52% 98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 30 0.48% 99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 14 0.23% 99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 13 0.21% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 3 0.05% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 1 0.02% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6195 # Writes before turning the bus around for reads
+system.physmem.totQLat 395458190750 # Total ticks spent queuing
+system.physmem.totMemAccLat 681707465750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 76333140000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 25903.44 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44656.31 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 384.29 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 44653.44 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 384.34 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 51.52 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s
system.physmem.busUtil 3.02 # Data bus utilization in percentage
system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 6.20 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.61 # Average write queue length when enqueuing
-system.physmem.readRowHits 14269193 # Number of row buffer hits during reads
-system.physmem.writeRowHits 90708 # Number of row buffer hits during writes
+system.physmem.avgRdQLen 7.09 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing
+system.physmem.readRowHits 14271218 # Number of row buffer hits during reads
+system.physmem.writeRowHits 90719 # Number of row buffer hits during writes
system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 85.63 # Row buffer hit rate for writes
-system.physmem.avgGap 157821.19 # Average gap between requests
-system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2194513894000 # Time in different power states
-system.physmem.memoryStateTime::REF 84889480000 # Time in different power states
+system.physmem.writeRowHitRate 85.60 # Row buffer hit rate for writes
+system.physmem.avgGap 157818.32 # Average gap between requests
+system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 2194559119750 # Time in different power states
+system.physmem.memoryStateTime::REF 84888180000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 262799464750 # Time in different power states
+system.physmem.memoryStateTime::ACT 262709081500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 48 # Number of bytes read from this memory
system.realview.nvmem.bw_inst_read::total 19 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 19 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 19 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 55125441 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 16348039 # Transaction distribution
-system.membus.trans_dist::ReadResp 16348039 # Transaction distribution
+system.membus.trans_dist::ReadReq 16348037 # Transaction distribution
+system.membus.trans_dist::ReadResp 16348037 # Transaction distribution
system.membus.trans_dist::WriteReq 763357 # Transaction distribution
system.membus.trans_dist::WriteResp 763357 # Transaction distribution
system.membus.trans_dist::Writeback 58488 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4612 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4612 # Transaction distribution
-system.membus.trans_dist::ReadExReq 131651 # Transaction distribution
-system.membus.trans_dist::ReadExResp 131651 # Transaction distribution
+system.membus.trans_dist::ReadExReq 131654 # Transaction distribution
+system.membus.trans_dist::ReadExResp 131654 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 6 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889330 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276174 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889332 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276176 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 34553806 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631440 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19029530 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 140140058 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 140140058 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1558440500 # Layer occupancy (ticks)
+system.membus.pkt_count::total 34553808 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631504 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19029594 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 140140122 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 216513 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 216513 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 216513 # Request fanout histogram
+system.membus.reqLayer0.occupancy 1556318500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer1.occupancy 3500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3512000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 3760500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer6.occupancy 17513415500 # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy 17512345000 # Layer occupancy (ticks)
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4726913870 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 4726136292 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 37423565460 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 37419189712 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.iobus.throughput 48580309 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution
system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution
system.iobus.trans_dist::WriteReq 8176 # Transaction distribution
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 123501006 # Total data (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 38173420540 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 38173439288 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 13201290 # Number of BP lookups
-system.cpu.branchPred.condPredicted 9675974 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 704139 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 8377301 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 6024680 # Number of BTB hits
+system.cpu.branchPred.lookups 13200672 # Number of BP lookups
+system.cpu.branchPred.condPredicted 9675464 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 704019 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 8378152 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 6024616 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 71.916719 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1435837 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 30801 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 71.908650 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1435808 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 30777 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 31642294 # DTB read hits
-system.cpu.dtb.read_misses 39524 # DTB read misses
-system.cpu.dtb.write_hits 11381361 # DTB write hits
-system.cpu.dtb.write_misses 10135 # DTB write misses
+system.cpu.dtb.read_hits 31644036 # DTB read hits
+system.cpu.dtb.read_misses 39518 # DTB read misses
+system.cpu.dtb.write_hits 11381434 # DTB write hits
+system.cpu.dtb.write_misses 10146 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 3437 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.flush_entries 3436 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 314 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 1342 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 31681818 # DTB read accesses
-system.cpu.dtb.write_accesses 11391496 # DTB write accesses
+system.cpu.dtb.read_accesses 31683554 # DTB read accesses
+system.cpu.dtb.write_accesses 11391580 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 43023655 # DTB hits
-system.cpu.dtb.misses 49659 # DTB misses
-system.cpu.dtb.accesses 43073314 # DTB accesses
+system.cpu.dtb.hits 43025470 # DTB hits
+system.cpu.dtb.misses 49664 # DTB misses
+system.cpu.dtb.accesses 43075134 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.inst_hits 24159481 # ITB inst hits
-system.cpu.itb.inst_misses 10516 # ITB inst misses
+system.cpu.itb.inst_hits 24158829 # ITB inst hits
+system.cpu.itb.inst_misses 10513 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2464 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2463 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 4176 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 4177 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 24169997 # ITB inst accesses
-system.cpu.itb.hits 24159481 # DTB hits
-system.cpu.itb.misses 10516 # DTB misses
-system.cpu.itb.accesses 24169997 # DTB accesses
-system.cpu.numCycles 499350041 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 24169342 # ITB inst accesses
+system.cpu.itb.hits 24158829 # DTB hits
+system.cpu.itb.misses 10513 # DTB misses
+system.cpu.itb.accesses 24169342 # DTB accesses
+system.cpu.numCycles 499362415 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 43030629 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 74131140 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 13201290 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 7460517 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 448266810 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1858598 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 133224 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 12550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 145871 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 3032125 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 24158180 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 404816 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 4527 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 495550550 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.179793 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 0.652924 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 43030394 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 74128653 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 13200672 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 7460424 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 448275105 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1858360 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 133126 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 12568 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 145919 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 3031035 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 24157528 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 404783 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 4525 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 495557370 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.179785 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 0.652906 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 454644690 91.75% 91.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 13614673 2.75% 94.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 6391682 1.29% 95.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 20899505 4.22% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 454652495 91.75% 91.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 13614115 2.75% 94.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 6392828 1.29% 95.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 20897932 4.22% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 495550550 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.026437 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.148455 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 35577628 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 424964763 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 30286365 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 4037656 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 684138 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1691487 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 250438 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 80256354 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2078563 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 684138 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 38799814 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 217885603 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 28702319 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 30653900 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 178824776 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 78213523 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 597412 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 61147213 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 42400387 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 160465829 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 14695892 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 82092463 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 364185184 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 97017359 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 495557370 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.026435 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.148447 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 35569711 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 424983346 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 30281377 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 4038894 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 684042 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1691471 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 250415 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 80255110 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 2078434 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 684042 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 38792488 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 217877928 # Number of cycles rename is blocking
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+system.cpu.rename.UnblockCycles 178850866 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 78212678 # Number of instructions processed by rename
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+system.cpu.rename.ROBFullEvents 61152111 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 42400388 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 160465834 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 14716938 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 82091302 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 364181024 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 97016550 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 9816 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 75931181 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6161276 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1134052 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 964724 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 8995770 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 14558741 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 12101093 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 791110 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1256144 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 75819284 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1655722 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 93902738 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 178739 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 4397586 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 8688962 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 172255 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 495550550 # Number of insts issued each cycle
+system.cpu.rename.CommittedMaps 75931219 # Number of HB maps that are committed
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+system.cpu.rename.serializingInsts 1133996 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 964709 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 9001428 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 14558433 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 12101238 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 791096 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1255692 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 75818942 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1655707 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 93904368 # Number of instructions issued
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+system.cpu.iq.iqSquashedInstsExamined 4397117 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 8687724 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 172240 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::mean 0.189492 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::1 42998311 8.68% 95.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 15714626 3.17% 98.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5641325 1.14% 99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 637755 0.13% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 430560734 86.88% 86.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 43002673 8.68% 95.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 15716973 3.17% 98.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5640247 1.14% 99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 636707 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 495550550 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 495557370 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 4849757 15.79% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 148 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 20356138 66.26% 82.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 5517293 17.96% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 4845097 15.77% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 148 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 20357888 66.27% 82.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 5517607 17.96% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 28518 0.03% 0.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 49538159 52.75% 52.79% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 91859 0.10% 52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 49538039 52.75% 52.78% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 91860 0.10% 52.88% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 52.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 32267131 34.36% 87.25% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 11974960 12.75% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 32268758 34.36% 87.25% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 11975082 12.75% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 93902738 # Type of FU issued
-system.cpu.iq.rate 0.188050 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 30723336 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.327183 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 714225557 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 81867089 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 74968821 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 93904368 # Type of FU issued
+system.cpu.iq.rate 0.188049 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 30720740 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.327149 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 714233003 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 81866264 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 74968812 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 32544 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 12124 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10212 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 124576093 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 124575127 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 21463 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 210027 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 210020 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1045815 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 542 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 6661 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 369450 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1045495 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 540 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 6662 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 369586 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 17074256 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1003626 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 17074158 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1006174 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 684138 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 94162664 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 98281305 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 77651016 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 684042 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 94158200 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 98278744 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 77650660 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 14558741 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 12101093 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1114432 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 20278 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 98196726 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 6661 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 210280 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 275497 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 485777 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 93247730 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 32000327 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 605564 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts 14558433 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 12101238 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1114427 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 20284 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 98194153 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 6662 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 210239 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 275440 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 485679 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 93249449 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 32002025 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 605470 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 176010 # number of nop insts executed
-system.cpu.iew.exec_refs 43889216 # number of memory reference insts executed
-system.cpu.iew.exec_branches 10791342 # Number of branches executed
-system.cpu.iew.exec_stores 11888889 # Number of stores executed
-system.cpu.iew.exec_rate 0.186738 # Inst execution rate
-system.cpu.iew.wb_sent 92183788 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 74979033 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 35465784 # num instructions producing a value
-system.cpu.iew.wb_consumers 52709939 # num instructions consuming a value
+system.cpu.iew.exec_nop 176011 # number of nop insts executed
+system.cpu.iew.exec_refs 43890987 # number of memory reference insts executed
+system.cpu.iew.exec_branches 10791373 # Number of branches executed
+system.cpu.iew.exec_stores 11888962 # Number of stores executed
+system.cpu.iew.exec_rate 0.186737 # Inst execution rate
+system.cpu.iew.wb_sent 92183769 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 74979024 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 35461894 # num instructions producing a value
+system.cpu.iew.wb_consumers 52697256 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.150153 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.672848 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.150150 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.672936 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 3942514 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 3942249 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1483467 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 458978 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 494644570 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.147200 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 0.699335 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 458881 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 494573774 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.147222 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 0.699394 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 457921524 92.58% 92.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 22157230 4.48% 97.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 6973464 1.41% 98.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2402706 0.49% 98.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1803578 0.36% 99.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1042786 0.21% 99.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 592301 0.12% 99.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 490313 0.10% 99.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 1260668 0.25% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 457850390 92.57% 92.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 22155471 4.48% 97.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 6977487 1.41% 98.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2402189 0.49% 98.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1803487 0.36% 99.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1041949 0.21% 99.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 590384 0.12% 99.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 490446 0.10% 99.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 1261971 0.26% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 494644570 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60462326 # Number of instructions committed
-system.cpu.commit.committedOps 72811859 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 494573774 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60462353 # Number of instructions committed
+system.cpu.commit.committedOps 72811899 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 25244569 # Number of memory references committed
-system.cpu.commit.loads 13512926 # Number of loads committed
+system.cpu.commit.refs 25244590 # Number of memory references committed
+system.cpu.commit.loads 13512938 # Number of loads committed
system.cpu.commit.membars 403660 # Number of memory barriers committed
-system.cpu.commit.branches 10308073 # Number of branches committed
+system.cpu.commit.branches 10308077 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 64250122 # Number of committed integer instructions.
+system.cpu.commit.int_insts 64250158 # Number of committed integer instructions.
system.cpu.commit.function_calls 991634 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 47477289 65.21% 65.21% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 87890 0.12% 65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 47477309 65.21% 65.21% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 87889 0.12% 65.33% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.33% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.33% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.33% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.33% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.33% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.33% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 13512926 18.56% 83.89% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 11731643 16.11% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 13512938 18.56% 83.89% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 11731652 16.11% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 72811859 # Class of committed instruction
-system.cpu.commit.bw_lim_events 1260668 # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total 72811899 # Class of committed instruction
+system.cpu.commit.bw_lim_events 1261971 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 568287463 # The number of ROB reads
-system.cpu.rob.rob_writes 154414560 # The number of ROB writes
-system.cpu.timesIdled 544007 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 3799491 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4584972685 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60311945 # Number of Instructions Simulated
-system.cpu.committedOps 72661478 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 8.279455 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 8.279455 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.120781 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.120781 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 109116898 # number of integer regfile reads
-system.cpu.int_regfile_writes 47012340 # number of integer regfile writes
+system.cpu.rob.rob_reads 568215140 # The number of ROB reads
+system.cpu.rob.rob_writes 154414029 # The number of ROB writes
+system.cpu.timesIdled 543953 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 3805045 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 4584951345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 60311972 # Number of Instructions Simulated
+system.cpu.committedOps 72661518 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 8.279657 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 8.279657 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.120778 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.120778 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 109116744 # number of integer regfile reads
+system.cpu.int_regfile_writes 47012206 # number of integer regfile writes
system.cpu.fp_regfile_reads 8305 # number of floating regfile reads
system.cpu.fp_regfile_writes 2780 # number of floating regfile writes
-system.cpu.cc_regfile_reads 320404185 # number of cc regfile reads
-system.cpu.cc_regfile_writes 30332896 # number of cc regfile writes
-system.cpu.misc_regfile_reads 605539146 # number of misc regfile reads
-system.cpu.misc_regfile_writes 1173999 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 57498963 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 2604292 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2604292 # Transaction distribution
+system.cpu.cc_regfile_reads 320409300 # number of cc regfile reads
+system.cpu.cc_regfile_writes 30332935 # number of cc regfile writes
+system.cpu.misc_regfile_reads 605119297 # number of misc regfile reads
+system.cpu.misc_regfile_writes 1173998 # number of misc regfile writes
+system.cpu.toL2Bus.trans_dist::ReadReq 2604204 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2604204 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 599976 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 599947 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2952 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 246570 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 246570 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926546 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768452 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27160 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85384 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 7807542 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61456864 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84377274 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37916 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135596 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 146007650 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 146007650 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 166384 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 3090458553 # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::ReadExReq 246567 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 246567 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926460 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768361 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27152 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85364 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 7807337 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61454112 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84373434 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37904 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135564 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 146001014 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 26770 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 2266210 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
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+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 249406 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 249406 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247596 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 247596 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 22106443 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 22106443 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 22293767 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 22293767 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.048236 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.048236 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 22106458 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 22106458 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 22293785 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 22293785 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.048234 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.048234 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.294708 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.294708 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.675306 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.675306 # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052070 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052070 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.675284 # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.675284 # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052072 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052072 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000008 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.162204 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.162204 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.166515 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.166515 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12588.259390 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 12588.259390 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41831.429499 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 41831.429499 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13719.240838 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13719.240838 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.162203 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.162203 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.166514 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.166514 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12600.762532 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 12600.762532 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41873.463543 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 41873.463543 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13647.994148 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13647.994148 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 37156.259084 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 37156.259084 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 35890.097324 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 35890.097324 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 18826 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1227 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.343113 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37193.701936 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37193.701936 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 35926.279165 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 35926.279165 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 17394 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 459 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 1226 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.187602 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 459 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 599976 # number of writebacks
-system.cpu.dcache.writebacks::total 599976 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 271755 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 271755 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2763119 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2763119 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 599947 # number of writebacks
+system.cpu.dcache.writebacks::total 599947 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 271762 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 271762 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2763128 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2763128 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1233 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 1233 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3034874 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3034874 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3034874 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3034874 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 301506 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 301506 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249365 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 249365 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 74145 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 74145 # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11755 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 11755 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data 3034890 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3034890 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3034890 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3034890 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 301481 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 301481 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249361 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 249361 # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 74144 # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total 74144 # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11754 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 11754 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 550871 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 550871 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 625016 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 625016 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3569781578 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 3569781578 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10783879319 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 10783879319 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1231283000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1231283000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140188500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140188500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data 550842 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 550842 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 624986 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 624986 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3569589078 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 3569589078 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10791306319 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 10791306319 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1230913250 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1230913250 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 139261250 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 139261250 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14353660897 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 14353660897 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15584943897 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 15584943897 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182408022250 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182408022250 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26599942575 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26599942575 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209007964825 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 209007964825 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025370 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025370 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14360895397 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 14360895397 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15591808647 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 15591808647 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182406065750 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182406065750 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26598901323 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26598901323 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209004967073 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 209004967073 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025368 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025368 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024395 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024395 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395812 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395812 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047127 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047127 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395800 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395800 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047128 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047128 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024919 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.024919 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028035 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.028035 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11839.835950 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11839.835950 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43245.360492 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43245.360492 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16606.419853 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16606.419853 # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11925.861336 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11925.861336 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024918 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.024918 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028034 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.028034 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11840.179242 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11840.179242 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43275.838319 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43275.838319 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16601.656911 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16601.656911 # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11847.987919 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11847.987919 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26056.301561 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26056.301561 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24935.271892 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24935.271892 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26070.806868 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26070.806868 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24947.452658 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24947.452658 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1736929447540 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1736929447540 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1736978742288 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1736978742288 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 83187 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 83186 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 2.400983 # Number of seconds simulated
-sim_ticks 2400982506000 # Number of ticks simulated
-final_tick 2400982506000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.400978 # Number of seconds simulated
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sim_freq 1000000000000 # Frequency of simulated ticks
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-host_op_rate 135898 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4496473277 # Simulator tick rate (ticks/s)
-host_mem_usage 411684 # Number of bytes of host memory used
-host_seconds 533.97 # Real time elapsed on the host
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+host_inst_rate 184738 # Simulator instruction rate (inst/s)
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system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
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system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 66333 # Write bandwidth from this memory (bytes/s)
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.neitherReadNorWriteReqs 2870 # Number of requests that are neither read nor write
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-system.physmem.perBankRdBursts::6 838426 # Per bank write bursts
-system.physmem.perBankRdBursts::7 839444 # Per bank write bursts
-system.physmem.perBankRdBursts::8 841128 # Per bank write bursts
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-system.physmem.perBankRdBursts::11 843721 # Per bank write bursts
-system.physmem.perBankRdBursts::12 845312 # Per bank write bursts
-system.physmem.perBankRdBursts::13 845603 # Per bank write bursts
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-system.physmem.perBankWrBursts::12 3817 # Per bank write bursts
-system.physmem.perBankWrBursts::13 3843 # Per bank write bursts
-system.physmem.perBankWrBursts::14 3141 # Per bank write bursts
-system.physmem.perBankWrBursts::15 2511 # Per bank write bursts
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+system.physmem.perBankRdBursts::6 838590 # Per bank write bursts
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+system.physmem.perBankRdBursts::10 843775 # Per bank write bursts
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+system.physmem.perBankRdBursts::12 845212 # Per bank write bursts
+system.physmem.perBankRdBursts::13 845578 # Per bank write bursts
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+system.physmem.perBankWrBursts::2 2845 # Per bank write bursts
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+system.physmem.perBankWrBursts::6 2950 # Per bank write bursts
+system.physmem.perBankWrBursts::7 2539 # Per bank write bursts
+system.physmem.perBankWrBursts::8 2638 # Per bank write bursts
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+system.physmem.perBankWrBursts::10 2391 # Per bank write bursts
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+system.physmem.perBankWrBursts::12 3740 # Per bank write bursts
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+system.physmem.perBankWrBursts::14 3267 # Per bank write bursts
+system.physmem.perBankWrBursts::15 2529 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2398981428000 # Total gap between requests
+system.physmem.totGap 2398976781000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 13409008 # Read request sizes (log2)
+system.physmem.readPktSize::3 13407440 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 39311 # Read request sizes (log2)
+system.physmem.readPktSize::6 39346 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 467913 # Write request sizes (log2)
+system.physmem.writePktSize::2 467914 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 17734 # Write request sizes (log2)
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-system.physmem.rdQLenPdf::16 39 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 17777 # Write request sizes (log2)
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+system.physmem.rdQLenPdf::16 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 99 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 96 # What write queue length does an incoming req see
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-system.physmem.bytesPerActivate::samples 866402 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 996.895132 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 964.187701 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 145.697526 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 8320 0.96% 0.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 8911 1.03% 1.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6111 0.71% 2.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 785 0.09% 2.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 956 0.11% 2.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 773 0.09% 2.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 7768 0.90% 3.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 290 0.03% 3.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 832488 96.09% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 866402 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 2583 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 5206.469222 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 249565.705681 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-524287 2582 99.96% 99.96% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 866162 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 997.062961 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 964.716097 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 145.162362 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 8098 0.93% 0.93% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::256-383 6105 0.70% 2.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 860 0.10% 2.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 965 0.11% 2.89% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1024-1151 832451 96.11% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 866162 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 2588 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 5195.817620 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07 1 0.04% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 2583 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 2583 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 18.265583 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.091885 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 2.157240 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1 3 0.12% 0.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2 1 0.04% 0.15% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::4 2 0.08% 0.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::5 1 0.04% 0.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::6 1 0.04% 0.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8 2 0.08% 0.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::9 1 0.04% 0.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::13 3 0.12% 0.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::15 4 0.15% 0.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 537 20.79% 21.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 7 0.27% 21.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 754 29.19% 51.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 1050 40.65% 91.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 100 3.87% 95.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 31 1.20% 96.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 20 0.77% 97.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 15 0.58% 98.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 9 0.35% 98.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 3 0.12% 98.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 7 0.27% 98.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 5 0.19% 99.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28 5 0.19% 99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29 5 0.19% 99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30 6 0.23% 99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31 4 0.15% 99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32 5 0.19% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 2583 # Writes before turning the bus around for reads
-system.physmem.totQLat 346447958000 # Total ticks spent queuing
-system.physmem.totMemAccLat 598603939250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 67241595000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 25761.43 # Average queueing delay per DRAM burst
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+system.physmem.totQLat 347055171000 # Total ticks spent queuing
+system.physmem.totMemAccLat 599182408500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 67233930000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 25809.53 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44511.43 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 358.48 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 44559.53 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 358.43 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.26 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 45.73 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 45.72 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.25 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 2.81 # Data bus utilization in percentage
system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 7.91 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 2.57 # Average write queue length when enqueuing
-system.physmem.readRowHits 12588353 # Number of row buffer hits during reads
-system.physmem.writeRowHits 40744 # Number of row buffer hits during writes
+system.physmem.avgRdQLen 7.23 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 2.52 # Average write queue length when enqueuing
+system.physmem.readRowHits 12587076 # Number of row buffer hits during reads
+system.physmem.writeRowHits 40794 # Number of row buffer hits during writes
system.physmem.readRowHitRate 93.61 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 86.32 # Row buffer hit rate for writes
-system.physmem.avgGap 172167.88 # Average gap between requests
+system.physmem.writeRowHitRate 86.30 # Row buffer hit rate for writes
+system.physmem.avgGap 172185.95 # Average gap between requests
system.physmem.pageHitRate 93.58 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2165142880250 # Time in different power states
+system.physmem.memoryStateTime::IDLE 2165163855000 # Time in different power states
system.physmem.memoryStateTime::REF 80173860000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 155659356000 # Time in different power states
+system.physmem.memoryStateTime::ACT 155638381250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 55731244 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 13775425 # Transaction distribution
-system.membus.trans_dist::ReadResp 13775425 # Transaction distribution
-system.membus.trans_dist::WriteReq 471057 # Transaction distribution
-system.membus.trans_dist::WriteResp 471057 # Transaction distribution
-system.membus.trans_dist::Writeback 17734 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 2870 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 2870 # Transaction distribution
-system.membus.trans_dist::ReadExReq 31339 # Transaction distribution
-system.membus.trans_dist::ReadExResp 31339 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 722736 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 440 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq 15564561 # Transaction distribution
+system.membus.trans_dist::ReadResp 15564561 # Transaction distribution
+system.membus.trans_dist::WriteReq 763190 # Transaction distribution
+system.membus.trans_dist::WriteResp 763190 # Transaction distribution
+system.membus.trans_dist::Writeback 58459 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4572 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4572 # Transaction distribution
+system.membus.trans_dist::ReadExReq 131741 # Transaction distribution
+system.membus.trans_dist::ReadExResp 131741 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1037922 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 1761100 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26818016 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 26818016 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 28579116 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 726717 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 880 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5522532 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total 6250133 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107272064 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 107272064 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 113522197 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 133809743 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 411651000 # Layer occupancy (ticks)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1895349 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 4281819 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 28704768 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 28704768 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 32986587 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2390317 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
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-system.l2c.ReadReq_avg_mshr_miss_latency::total 62612.580908 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58039.611964 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63245.251858 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 86843.750000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 60776.651907 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 65302.659517 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 62229.853073 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10011.104042 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10008.429279 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58581.967387 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60826.070124 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 60027.346351 # average ReadExReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10005.112939 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.028084 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58243.129952 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61615.600882 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 60414.790530 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59294.703390 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58977.786213 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 65000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 61827.275815 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61283.928781 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 60537.937221 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58039.611964 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58718.382551 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 86843.750000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 60776.651907 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62025.745314 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 60774.388564 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59294.703390 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58977.786213 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 65000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 61827.275815 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61283.928781 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 60537.937221 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58039.611964 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58718.382551 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 86843.750000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 60776.651907 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62025.745314 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 60774.388564 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.toL2Bus.throughput 59108244 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 1059674 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 1059674 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 471057 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 471057 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 275568 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 1835 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 1835 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 93577 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 93577 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 911138 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2522746 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20145 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55378 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 3509407 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29133952 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 38939733 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 27844 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87712 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 68189241 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 141801951 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 115908 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 2288858155 # Layer occupancy (ticks)
+system.toL2Bus.trans_dist::ReadReq 2539315 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2539315 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 763190 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 763190 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 598065 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 2933 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 2933 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 246953 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 246953 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1813392 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5760169 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 30385 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 80672 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 7684618 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 57608092 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 84067517 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 48464 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 138604 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 141862677 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 18229 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 2196613 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 2196613 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 2196613 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 2287106157 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 2052757055 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 2054352798 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 1915102818 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 1912625851 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 13212439 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 13149443 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 33686507 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 33486737 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.throughput 48817267 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 13767391 # Transaction distribution
-system.iobus.trans_dist::ReadResp 13767391 # Transaction distribution
-system.iobus.trans_dist::WriteReq 2985 # Transaction distribution
-system.iobus.trans_dist::WriteResp 2985 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 12256 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3140 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 288 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 706746 # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq 15535704 # Transaction distribution
+system.iobus.trans_dist::ReadResp 15535704 # Transaction distribution
+system.iobus.trans_dist::WriteReq 8154 # Transaction distribution
+system.iobus.trans_dist::WriteResp 8154 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30010 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 492 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1000 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 732 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 722736 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26818016 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total 26818016 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 27540752 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 16027 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6280 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 576 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 703222 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 726717 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107272064 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107272064 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 107998781 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 117209403 # Total data (bytes)
-system.iobus.reqLayer0.occupancy 8657000 # Layer occupancy (ticks)
+system.iobus.pkt_count_system.bridge.master::total 2382948 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 28704768 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total 28704768 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 31087716 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39305 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 984 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2000 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 390 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
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system.iobus.respLayer1.utilization 1.4 # Layer utilization (%)
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system.cpu0.dtb.flush_tlb 554 # Number of times complete TLB was flushed
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system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 162 # Number of TLB faults due to permissions restrictions
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system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 554 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
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-system.cpu0.itb.misses 2986 # DTB misses
-system.cpu0.itb.accesses 30122397 # DTB accesses
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu0.num_fp_insts 4289 # number of float instructions
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system.cpu0.num_fp_register_reads 3327 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 964 # number of times the floating registers were written
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-system.cpu0.idle_fraction 0.978946 # Percentage of idle cycles
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system.cpu0.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction
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system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction
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system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
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system.cpu0.kern.inst.arm 0 # number of arm instructions executed
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-system.cpu0.icache.tags.avg_refs 45.821829 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 7765042250 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 495.273634 # Average occupied blocks per requestor
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+system.cpu0.icache.tags.occ_blocks::cpu0.inst 495.394938 # Average occupied blocks per requestor
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system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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-system.cpu0.icache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id
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+system.cpu0.icache.tags.age_task_id_blocks_1024::1 216 # Occupied blocks per task id
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-system.cpu0.icache.ReadReq_avg_miss_latency::total 7025.960758 # average ReadReq miss latency
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-system.cpu0.icache.overall_avg_miss_latency::total 7025.960758 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 3564 # number of cycles access was blocked
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system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
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-system.cpu0.icache.ReadReq_mshr_hits::total 27790 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst 27790 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 27790 # number of demand (read+write) MSHR hits
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-system.cpu0.icache.overall_mshr_hits::total 27790 # number of overall MSHR hits
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-system.cpu0.icache.ReadReq_mshr_misses::total 455920 # number of ReadReq MSHR misses
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-system.cpu0.icache.demand_mshr_misses::total 455920 # number of demand (read+write) MSHR misses
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-system.cpu0.icache.overall_mshr_misses::total 455920 # number of overall MSHR misses
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-system.cpu0.icache.ReadReq_mshr_miss_latency::total 5359119420 # number of ReadReq MSHR miss cycles
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-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3957248170 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 5359119420 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1401871250 # number of overall MSHR miss cycles
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-system.cpu0.icache.overall_mshr_miss_latency::total 5359119420 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015103 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.082809 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010816 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015103 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.082809 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.010816 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015103 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.082809 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.010816 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11630.215204 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11799.191283 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11754.517064 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11630.215204 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11799.191283 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11754.517064 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11630.215204 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11799.191283 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11754.517064 # average overall mshr miss latency
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+system.cpu0.icache.ReadReq_mshr_misses::total 456271 # number of ReadReq MSHR misses
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+system.cpu0.icache.overall_mshr_misses::total 456271 # number of overall MSHR misses
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+system.cpu0.icache.demand_mshr_miss_latency::total 5362036684 # number of demand (read+write) MSHR miss cycles
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+system.cpu0.icache.overall_mshr_miss_latency::total 5362036684 # number of overall MSHR miss cycles
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+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11751.868263 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements 630291 # number of replacements
+system.cpu0.dcache.tags.replacements 630395 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.997117 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 21342473 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 630803 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 33.833817 # Average number of references to valid blocks.
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system.cpu0.dcache.tags.warmup_cycle 21757000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.608321 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data 7.871908 # Average occupied blocks per requestor
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system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id
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-system.cpu0.dcache.tags.tag_accesses 92219903 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 92219903 # Number of data accesses
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-system.cpu0.dcache.SoftPFReq_misses::total 96293 # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6071 # number of LoadLockedReq misses
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-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 65741241 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 85200741 # number of LoadLockedReq miss cycles
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-system.cpu0.dcache.overall_accesses::total 22399428 # number of overall (read+write) accesses
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-system.cpu0.dcache.overall_miss_rate::total 0.069012 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13503.307189 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14031.217273 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 9490.532076 # average ReadReq miss latency
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-system.cpu0.dcache.blocked_cycles::no_targets 6212 # number of cycles access was blocked
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 1746639 # DTB read hits
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system.cpu1.dtb.write_misses 367 # DTB write misses
system.cpu1.dtb.flush_tlb 552 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 251 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 10 # Number of times TLB was flushed by ASID
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system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 77 # Number of TLB faults due to permissions restrictions
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system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
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+system.cpu1.dtb.hits 3104553 # DTB hits
+system.cpu1.dtb.misses 2256 # DTB misses
+system.cpu1.dtb.accesses 3106809 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 7981130 # ITB inst hits
-system.cpu1.itb.inst_misses 1058 # ITB inst misses
+system.cpu1.itb.inst_hits 7924396 # ITB inst hits
+system.cpu1.itb.inst_misses 1030 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 552 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 251 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 10 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 834 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 248 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 806 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 7982188 # ITB inst accesses
-system.cpu1.itb.hits 7981130 # DTB hits
-system.cpu1.itb.misses 1058 # DTB misses
-system.cpu1.itb.accesses 7982188 # DTB accesses
-system.cpu1.numCycles 582833153 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 7925426 # ITB inst accesses
+system.cpu1.itb.hits 7924396 # DTB hits
+system.cpu1.itb.misses 1030 # DTB misses
+system.cpu1.itb.accesses 7925426 # DTB accesses
+system.cpu1.numCycles 582686408 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 7797141 # Number of instructions committed
-system.cpu1.committedOps 9191219 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 8219243 # Number of integer alu accesses
+system.cpu1.committedInsts 7745878 # Number of instructions committed
+system.cpu1.committedOps 9129746 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 8166989 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 1689 # Number of float alu accesses
-system.cpu1.num_func_calls 289029 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 993030 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 8219243 # number of integer instructions
+system.cpu1.num_func_calls 287006 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 983778 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 8166989 # number of integer instructions
system.cpu1.num_fp_insts 1689 # number of float instructions
-system.cpu1.num_int_register_reads 14554839 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 5500250 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 14466592 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 5466665 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 1177 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 512 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 33218155 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 3793046 # number of times the CC registers were written
-system.cpu1.num_mem_refs 3251661 # number of memory refs
-system.cpu1.num_load_insts 1804549 # Number of load instructions
-system.cpu1.num_store_insts 1447112 # Number of store instructions
-system.cpu1.num_idle_cycles 548698663.963538 # Number of idle cycles
-system.cpu1.num_busy_cycles 34134489.036462 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.058566 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.941434 # Percentage of idle cycles
-system.cpu1.Branches 1360376 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 4595 0.05% 0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu 6078995 65.05% 65.10% # Class of executed instruction
-system.cpu1.op_class::IntMult 10163 0.11% 65.20% # Class of executed instruction
+system.cpu1.num_cc_register_reads 32997995 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 3759402 # number of times the CC registers were written
+system.cpu1.num_mem_refs 3229777 # number of memory refs
+system.cpu1.num_load_insts 1791377 # Number of load instructions
+system.cpu1.num_store_insts 1438400 # Number of store instructions
+system.cpu1.num_idle_cycles 548052403.807954 # Number of idle cycles
+system.cpu1.num_busy_cycles 34634004.192046 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.059438 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.940562 # Percentage of idle cycles
+system.cpu1.Branches 1348409 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 4600 0.05% 0.05% # Class of executed instruction
+system.cpu1.op_class::IntAlu 6037827 65.04% 65.09% # Class of executed instruction
+system.cpu1.op_class::IntMult 10088 0.11% 65.20% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 65.20% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 65.20% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 65.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.20% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 281 0.00% 65.21% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 273 0.00% 65.21% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 65.21% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.21% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.21% # Class of executed instruction
-system.cpu1.op_class::MemRead 1804549 19.31% 84.52% # Class of executed instruction
-system.cpu1.op_class::MemWrite 1447112 15.48% 100.00% # Class of executed instruction
+system.cpu1.op_class::MemRead 1791377 19.30% 84.50% # Class of executed instruction
+system.cpu1.op_class::MemWrite 1438400 15.50% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 9345695 # Class of executed instruction
+system.cpu1.op_class::total 9282565 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.branchPred.lookups 5844133 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 4389690 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 248799 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 3701982 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 2861782 # Number of BTB hits
+system.cpu2.branchPred.lookups 5846326 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 4388844 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 249586 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 3633950 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 2855743 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 77.304050 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 588875 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 15609 # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct 78.585093 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 589622 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 15464 # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
-system.cpu2.dtb.read_hits 13926534 # DTB read hits
-system.cpu2.dtb.read_misses 28241 # DTB read misses
-system.cpu2.dtb.write_hits 3979346 # DTB write hits
-system.cpu2.dtb.write_misses 9743 # DTB write misses
+system.cpu2.dtb.read_hits 13911313 # DTB read hits
+system.cpu2.dtb.read_misses 27890 # DTB read misses
+system.cpu2.dtb.write_hits 3983127 # DTB write hits
+system.cpu2.dtb.write_misses 9793 # DTB write misses
system.cpu2.dtb.flush_tlb 550 # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries 2739 # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults 445 # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults 255 # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_entries 2737 # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults 484 # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults 262 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults 656 # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses 13954775 # DTB read accesses
-system.cpu2.dtb.write_accesses 3989089 # DTB write accesses
+system.cpu2.dtb.perms_faults 640 # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses 13939203 # DTB read accesses
+system.cpu2.dtb.write_accesses 3992920 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu2.dtb.hits 17905880 # DTB hits
-system.cpu2.dtb.misses 37984 # DTB misses
-system.cpu2.dtb.accesses 17943864 # DTB accesses
+system.cpu2.dtb.hits 17894440 # DTB hits
+system.cpu2.dtb.misses 37683 # DTB misses
+system.cpu2.dtb.accesses 17932123 # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu2.itb.inst_hits 4053038 # ITB inst hits
-system.cpu2.itb.inst_misses 6578 # ITB inst misses
+system.cpu2.itb.inst_hits 4060759 # ITB inst hits
+system.cpu2.itb.inst_misses 6577 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries 2058 # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_entries 2055 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults 2441 # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults 2376 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
-system.cpu2.itb.inst_accesses 4059616 # ITB inst accesses
-system.cpu2.itb.hits 4053038 # DTB hits
-system.cpu2.itb.misses 6578 # DTB misses
-system.cpu2.itb.accesses 4059616 # DTB accesses
-system.cpu2.numCycles 88208146 # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses 4067336 # ITB inst accesses
+system.cpu2.itb.hits 4060759 # DTB hits
+system.cpu2.itb.misses 6577 # DTB misses
+system.cpu2.itb.accesses 4067336 # DTB accesses
+system.cpu2.numCycles 88050542 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 10487397 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 32911643 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 5844133 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 3450657 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 74966701 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 679472 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles 80302 # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles 630 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 972 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 72243 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 1263867 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 410 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 4050067 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 153217 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes 2804 # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples 87212188 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 0.443226 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 1.629212 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles 10519234 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 32939379 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 5846326 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 3445365 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 74770225 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 681136 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles 80231 # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles 505 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 954 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 72091 # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles 1265694 # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles 337 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 4057838 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 153485 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes 2814 # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples 87049769 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 0.444404 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 1.631683 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 79899565 91.62% 91.62% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 625094 0.72% 92.33% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 698013 0.80% 93.13% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 764181 0.88% 94.01% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 868461 1.00% 95.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 574503 0.66% 95.66% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 981504 1.13% 96.79% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 301305 0.35% 97.13% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 2499562 2.87% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 79735168 91.60% 91.60% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 627849 0.72% 92.32% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 697488 0.80% 93.12% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 764418 0.88% 94.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 855506 0.98% 94.98% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 578096 0.66% 95.64% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 986877 1.13% 96.78% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 299514 0.34% 97.12% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 2504853 2.88% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 87212188 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.066254 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 0.373113 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 8569138 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 72587758 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 4831209 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 941079 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 281926 # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved 736866 # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred 58789 # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts 34844703 # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts 196626 # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles 281926 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 9031224 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 19204705 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 13140033 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 5253439 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 40299841 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 33794581 # Number of instructions processed by rename
+system.cpu2.fetch.rateDist::total 87049769 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.066397 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 0.374096 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 8593092 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 72401111 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 4830102 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 941679 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 282689 # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved 738219 # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred 58888 # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts 34839136 # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts 197306 # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles 282689 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 9053752 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 19270728 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 13147343 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 5254066 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 40040151 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 33787886 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 74120 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 29618551 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents 37683898 # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents 1100267 # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands 36626919 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 154339316 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 41664821 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 4127 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 28795876 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 7831027 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 344066 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 286541 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 5082070 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 6089915 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 4400227 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 719431 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 1142118 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 32029170 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 669683 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 38616590 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 44993 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 5567256 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 12099893 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 238978 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 87212188 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 0.442789 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.239118 # Number of insts issued each cycle
+system.cpu2.rename.IQFullEvents 29496747 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents 37523489 # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents 1004110 # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands 36611560 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 154353600 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 41662755 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 4122 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 28819307 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 7792237 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 344984 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 287406 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 5085187 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 6095255 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 4404078 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 715172 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 1132058 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 32032092 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 661150 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 38610720 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 45237 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 5536917 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 12037471 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 230168 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 87049769 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 0.443548 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.240485 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 73763195 84.58% 84.58% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 4095516 4.70% 89.28% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 2328743 2.67% 91.95% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 2051674 2.35% 94.30% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 2976748 3.41% 97.71% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 798764 0.92% 98.63% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 739781 0.85% 99.48% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 293068 0.34% 99.81% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 164699 0.19% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 73601742 84.55% 84.55% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 4103417 4.71% 89.27% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 2329810 2.68% 91.94% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 2044829 2.35% 94.29% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 2965004 3.41% 97.70% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 800473 0.92% 98.62% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 744836 0.86% 99.47% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 295465 0.34% 99.81% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 164193 0.19% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 87212188 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 87049769 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 122993 5.40% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 1 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 1970586 86.46% 91.85% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 185678 8.15% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 123164 5.43% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 2 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.43% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 1963174 86.51% 91.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 182867 8.06% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass 12081 0.03% 0.03% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 20207276 52.33% 52.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 34218 0.09% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 404 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.45% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 14176555 36.71% 89.16% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 4186056 10.84% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass 12079 0.03% 0.03% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 20212271 52.35% 52.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 34343 0.09% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 410 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 14161220 36.68% 89.15% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 4190397 10.85% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 38616590 # Type of FU issued
-system.cpu2.iq.rate 0.437789 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 2279258 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.059023 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 166760031 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 38278238 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 29588244 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 9588 # Number of floating instruction queue reads
+system.cpu2.iq.FU_type_0::total 38610720 # Type of FU issued
+system.cpu2.iq.rate 0.438506 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 2269207 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.058771 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 166576049 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 38242231 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 29605417 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 9604 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 5150 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 4304 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 40878658 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 5109 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 176007 # Number of loads that had data forwarded from stores
+system.cpu2.iq.int_alu_accesses 40862730 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 5118 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 177793 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 1107424 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 2018 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 18033 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 469449 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 1108149 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 2013 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 17977 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 469749 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 5207867 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 3518142 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads 5186465 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 3515984 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 281926 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 17856855 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 716566 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 32817404 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 57776 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 6089915 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 4400227 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 491578 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 63121 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 616282 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 18033 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 121106 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 106258 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 227364 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 38297957 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 14051286 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 280797 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles 282689 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 17818885 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 827114 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 32812972 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 58820 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 6095255 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 4404078 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 482366 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 63304 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 726253 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 17977 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 122015 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 106758 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 228773 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 38292590 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 14036165 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 280577 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 118551 # number of nop insts executed
-system.cpu2.iew.exec_refs 18186993 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 4220297 # Number of branches executed
-system.cpu2.iew.exec_stores 4135707 # Number of stores executed
-system.cpu2.iew.exec_rate 0.434177 # Inst execution rate
-system.cpu2.iew.wb_sent 34852514 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 29592548 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 17266310 # num instructions producing a value
-system.cpu2.iew.wb_consumers 30698955 # num instructions consuming a value
+system.cpu2.iew.exec_nop 119730 # number of nop insts executed
+system.cpu2.iew.exec_refs 18176329 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 4221740 # Number of branches executed
+system.cpu2.iew.exec_stores 4140164 # Number of stores executed
+system.cpu2.iew.exec_rate 0.434893 # Inst execution rate
+system.cpu2.iew.wb_sent 34848706 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 29609721 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 17270580 # num instructions producing a value
+system.cpu2.iew.wb_consumers 30711387 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 0.335485 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.562440 # average fanout of values written-back
+system.cpu2.iew.wb_rate 0.336281 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.562351 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 5479640 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 430705 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 190919 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 86342246 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 0.312843 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.237203 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 5477647 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 430982 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 191637 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 86152512 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 0.313795 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 1.238508 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 77364915 89.60% 89.60% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 4177735 4.84% 94.44% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1290086 1.49% 95.94% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 753837 0.87% 96.81% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 490440 0.57% 97.38% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 381562 0.44% 97.82% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 374801 0.43% 98.25% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 197147 0.23% 98.48% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 1311723 1.52% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 77159399 89.56% 89.56% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 4186602 4.86% 94.42% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1295333 1.50% 95.92% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 754876 0.88% 96.80% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 491618 0.57% 97.37% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 381305 0.44% 97.81% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 375733 0.44% 98.25% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 196216 0.23% 98.48% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 1311430 1.52% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 86342246 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 22875674 # Number of instructions committed
-system.cpu2.commit.committedOps 27011607 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 86152512 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 22893469 # Number of instructions committed
+system.cpu2.commit.committedOps 27034243 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 8913269 # Number of memory references committed
-system.cpu2.commit.loads 4982491 # Number of loads committed
-system.cpu2.commit.membars 117220 # Number of memory barriers committed
-system.cpu2.commit.branches 3644555 # Number of branches committed
+system.cpu2.commit.refs 8921435 # Number of memory references committed
+system.cpu2.commit.loads 4987106 # Number of loads committed
+system.cpu2.commit.membars 117312 # Number of memory barriers committed
+system.cpu2.commit.branches 3648396 # Number of branches committed
system.cpu2.commit.fp_insts 4270 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 23908542 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 341319 # Number of function calls committed.
+system.cpu2.commit.int_insts 23927319 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 341825 # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu 18065773 66.88% 66.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult 32161 0.12% 67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu 18080099 66.88% 66.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult 32299 0.12% 67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv 0 0.00% 67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc 404 0.00% 67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc 410 0.00% 67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead 4982491 18.45% 85.45% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite 3930778 14.55% 100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead 4987106 18.45% 85.45% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite 3934329 14.55% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total 27011607 # Class of committed instruction
-system.cpu2.commit.bw_lim_events 1311723 # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total 27034243 # Class of committed instruction
+system.cpu2.commit.bw_lim_events 1311430 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 116854146 # The number of ROB reads
-system.cpu2.rob.rob_writes 65855440 # The number of ROB writes
-system.cpu2.timesIdled 179134 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 995958 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 3544369510 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 22801865 # Number of Instructions Simulated
-system.cpu2.committedOps 26937798 # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi 3.868462 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 3.868462 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.258501 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.258501 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 45014030 # number of integer regfile reads
-system.cpu2.int_regfile_writes 19144459 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 47113 # number of floating regfile reads
+system.cpu2.rob.rob_reads 116684345 # The number of ROB reads
+system.cpu2.rob.rob_writes 65897015 # The number of ROB writes
+system.cpu2.timesIdled 179321 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 1000773 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 3544672545 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 22819105 # Number of Instructions Simulated
+system.cpu2.committedOps 26959879 # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi 3.858633 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 3.858633 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.259159 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.259159 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 45005013 # number of integer regfile reads
+system.cpu2.int_regfile_writes 19153075 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 47120 # number of floating regfile reads
system.cpu2.fp_regfile_writes 45464 # number of floating regfile writes
-system.cpu2.cc_regfile_reads 130800569 # number of cc regfile reads
-system.cpu2.cc_regfile_writes 12559359 # number of cc regfile writes
-system.cpu2.misc_regfile_reads 124603397 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 350092 # number of misc regfile writes
+system.cpu2.cc_regfile_reads 130804455 # number of cc regfile reads
+system.cpu2.cc_regfile_writes 12559622 # number of cc regfile writes
+system.cpu2.misc_regfile_reads 122469878 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 350259 # number of misc regfile writes
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1536004079250 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1536004079250 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1536004079250 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1536004079250 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1536462300750 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1536462300750 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1536462300750 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1536462300750 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 2.539697 # Number of seconds simulated
-sim_ticks 2539696838000 # Number of ticks simulated
-final_tick 2539696838000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.539695 # Number of seconds simulated
+sim_ticks 2539695141000 # Number of ticks simulated
+final_tick 2539695141000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 33216 # Simulator instruction rate (inst/s)
-host_op_rate 40018 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1398403355 # Simulator tick rate (ticks/s)
-host_mem_usage 411672 # Number of bytes of host memory used
-host_seconds 1816.14 # Real time elapsed on the host
-sim_insts 60325607 # Number of instructions simulated
-sim_ops 72677421 # Number of ops (including micro ops) simulated
+host_inst_rate 55026 # Simulator instruction rate (inst/s)
+host_op_rate 66292 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2316696588 # Simulator tick rate (ticks/s)
+host_mem_usage 466732 # Number of bytes of host memory used
+host_seconds 1096.26 # Real time elapsed on the host
+sim_insts 60322278 # Number of instructions simulated
+sim_ops 72673006 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 469568 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 3933400 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 314240 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 5155776 # Number of bytes read from this memory
-system.physmem.bytes_read::total 130985112 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 469568 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 314240 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 783808 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3774400 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1328880 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 1687192 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6790472 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.inst 471296 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 3922776 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 576 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 314048 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 5167104 # Number of bytes read from this memory
+system.physmem.bytes_read::total 130987352 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 471296 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 314048 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 785344 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3775232 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 1328636 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 1687436 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6791304 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 15 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 7337 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 61485 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 4910 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 80559 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15293132 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 58975 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 332220 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 421798 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 812993 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47687002 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 353 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu0.inst 7364 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 61319 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 9 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 4907 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 80736 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15293167 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 58988 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 332159 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 421859 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 813006 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47687034 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 378 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 184891 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1548768 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 252 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 123731 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 2030075 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51575097 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 184891 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 123731 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 308623 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1486162 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 523244 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 664328 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2673733 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1486162 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47687002 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 353 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 185572 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1544585 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 227 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 123656 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 2034537 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51576014 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 185572 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 123656 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 309228 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
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-system.physmem.bw_total::total 54248831 # Total bandwidth to/from this memory (bytes/s)
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-system.physmem.bytesReadWrQ 3518592 # Total number of bytes read from write queue
-system.physmem.bytesWritten 6826496 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 130985112 # Total read bytes from the system interface side
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-system.physmem.mergedWrBursts 706304 # Number of DRAM write bursts merged with an existing one
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2539695718000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 18 # Read request sizes (log2)
system.physmem.readPktSize::3 15138826 # Read request sizes (log2)
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-system.physmem.bytesPerActivate::stdev 200.561203 # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::1024-1151 941712 93.36% 100.00% # Bytes accessed per row activation
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-system.physmem.rdPerTurnAround::mean 2509.988470 # Reads before turning the bus around for writes
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-system.physmem.rdPerTurnAround::0-65535 6043 99.54% 99.54% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::65536-131071 3 0.05% 99.59% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.72% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-262143 5 0.08% 99.80% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::983040-1.04858e+06 2 0.03% 99.88% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.10% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6071 # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::mean 17.569428 # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::13 1 0.02% 0.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::14 3 0.05% 0.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::15 10 0.16% 0.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 2784 45.86% 46.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 49 0.81% 47.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 1358 22.37% 69.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 1417 23.34% 93.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 155 2.55% 95.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 60 0.99% 96.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 36 0.59% 97.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 21 0.35% 97.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 24 0.40% 98.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 17 0.28% 98.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 23 0.38% 98.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 14 0.23% 98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28 10 0.16% 99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29 12 0.20% 99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30 16 0.26% 99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31 11 0.18% 99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32 14 0.23% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6071 # Writes before turning the bus around for reads
-system.physmem.totQLat 392019251500 # Total ticks spent queuing
-system.physmem.totMemAccLat 677734639000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 76190770000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 25726.16 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 6078 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6078 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.552813 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.369881 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 2.322612 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1 5 0.08% 0.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2 4 0.07% 0.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::3 4 0.07% 0.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4 4 0.07% 0.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::5 2 0.03% 0.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::6 2 0.03% 0.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::7 3 0.05% 0.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8 1 0.02% 0.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::9 6 0.10% 0.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::10 3 0.05% 0.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::11 2 0.03% 0.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12 3 0.05% 0.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::13 3 0.05% 0.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::14 2 0.03% 0.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::15 13 0.21% 0.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 2782 45.77% 46.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 46 0.76% 47.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 1401 23.05% 70.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 1370 22.54% 93.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 152 2.50% 95.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 75 1.23% 96.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 36 0.59% 97.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 22 0.36% 97.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 24 0.39% 98.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 25 0.41% 98.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 13 0.21% 98.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27 15 0.25% 99.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28 16 0.26% 99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29 12 0.20% 99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30 9 0.15% 99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31 11 0.18% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32 12 0.20% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6078 # Writes before turning the bus around for reads
+system.physmem.totQLat 392436805250 # Total ticks spent queuing
+system.physmem.totMemAccLat 678145799000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 76189065000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 25754.14 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44476.16 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 384.00 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 44504.14 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 383.99 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.69 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 51.58 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s
system.physmem.busUtil 3.02 # Data bus utilization in percentage
system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 5.74 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 14.90 # Average write queue length when enqueuing
-system.physmem.readRowHits 14244888 # Number of row buffer hits during reads
-system.physmem.writeRowHits 91209 # Number of row buffer hits during writes
+system.physmem.avgRdQLen 6.40 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 14.87 # Average write queue length when enqueuing
+system.physmem.readRowHits 14244486 # Number of row buffer hits during reads
+system.physmem.writeRowHits 91200 # Number of row buffer hits during writes
system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 85.49 # Row buffer hit rate for writes
-system.physmem.avgGap 157685.09 # Average gap between requests
+system.physmem.writeRowHitRate 85.47 # Row buffer hit rate for writes
+system.physmem.avgGap 157684.51 # Average gap between requests
system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2193828681000 # Time in different power states
-system.physmem.memoryStateTime::REF 84806020000 # Time in different power states
+system.physmem.memoryStateTime::IDLE 2193361967750 # Time in different power states
+system.physmem.memoryStateTime::REF 84805760000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 261061225250 # Time in different power states
+system.physmem.memoryStateTime::ACT 261520412250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 55193080 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 16345666 # Transaction distribution
-system.membus.trans_dist::ReadResp 16345666 # Transaction distribution
+system.membus.trans_dist::ReadReq 16345693 # Transaction distribution
+system.membus.trans_dist::ReadResp 16345693 # Transaction distribution
system.membus.trans_dist::WriteReq 763357 # Transaction distribution
system.membus.trans_dist::WriteResp 763357 # Transaction distribution
-system.membus.trans_dist::Writeback 58975 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4635 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4635 # Transaction distribution
-system.membus.trans_dist::ReadExReq 131547 # Transaction distribution
-system.membus.trans_dist::ReadExResp 131547 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::Writeback 58988 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4647 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4647 # Transaction distribution
+system.membus.trans_dist::ReadExReq 131549 # Transaction distribution
+system.membus.trans_dist::ReadExResp 131549 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1884913 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4271753 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885020 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 4271848 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 34549385 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16665056 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total 19063162 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 140173690 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 140173690 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1487406000 # Layer occupancy (ticks)
+system.membus.pkt_count::total 34549480 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16668128 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 19066210 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 140176738 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 217843 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 217843 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 217843 # Request fanout histogram
+system.membus.reqLayer0.occupancy 1488348000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3427500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 3508000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer6.occupancy 17563315500 # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy 17564779000 # Layer occupancy (ticks)
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4754319520 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 4755343440 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 37450374673 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 37440252152 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 64063 # number of replacements
-system.l2c.tags.tagsinuse 51393.584080 # Cycle average of tags in use
-system.l2c.tags.total_refs 1901876 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 129454 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 14.691520 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 2528371598500 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 37072.406553 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 9.476763 # Average occupied blocks per requestor
+system.l2c.tags.replacements 64097 # number of replacements
+system.l2c.tags.tagsinuse 51403.492359 # Cycle average of tags in use
+system.l2c.tags.total_refs 1900046 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 129489 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 14.673416 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 2528369126500 # Cycle when the warmup percentage was hit.
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system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000251 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 5409.710973 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 3302.260075 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.209843 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 2641.050651 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 2952.468970 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.565680 # Average percentage of cache occupancy
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system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
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system.l2c.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024 65378 # Occupied blocks per task id
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system.l2c.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 438 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 3140 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 5952 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 55810 # Occupied blocks per task id
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system.l2c.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024 0.997589 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 18903981 # Number of tag accesses
-system.l2c.tags.data_accesses 18903981 # Number of data accesses
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-system.l2c.ReadReq_hits::cpu0.itb.walker 7459 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 477090 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 174144 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 29829 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 8048 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 498641 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 211687 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1434623 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 606690 # number of Writeback hits
-system.l2c.Writeback_hits::total 606690 # number of Writeback hits
+system.l2c.tags.occ_task_id_percent::1024 0.997604 # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses 18888451 # Number of tag accesses
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+system.l2c.ReadReq_hits::cpu0.data 174980 # number of ReadReq hits
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+system.l2c.ReadReq_hits::cpu1.itb.walker 8090 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 496617 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 210611 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1432882 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 606482 # number of Writeback hits
+system.l2c.Writeback_hits::total 606482 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 30 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 33 # number of UpgradeReq hits
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-system.l2c.overall_mshr_uncacheable_latency::cpu0.data 91413286250 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 92574327345 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 183993731345 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000505 # mshr miss rate for ReadReq accesses
+system.l2c.overall_mshr_miss_latency::cpu0.inst 429544750 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data 3686910075 # number of overall MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::cpu1.inst 294088000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 5088718653 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 9501314478 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6123500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83706366250 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83236564000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 166949053750 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 7705500500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 9339419914 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 17044920414 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6123500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 91411866750 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 92575983914 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 183993974164 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000544 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000134 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014912 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.033208 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000335 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009751 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020750 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.015526 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014952 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.033125 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000300 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009784 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020836 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.015567 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987717 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991618 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.989779 # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.504178 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.572862 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.541691 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000505 # mshr miss rate for demand accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989697 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.988764 # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.502309 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.574686 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.541813 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000544 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000134 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014912 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.213414 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000335 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009751 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.232382 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.091527 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000505 # mshr miss rate for overall accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014952 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.212202 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000300 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009784 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.233690 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.091649 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000544 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000134 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014912 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.213414 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000335 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009751 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.232382 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.091527 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 83107.142857 # average ReadReq mshr miss latency
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+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009784 # mshr miss rate for overall accesses
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system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59140.058156 # average ReadReq mshr miss latency
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60047.861507 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62769.113464 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 60616.591002 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.852231 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.950585 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.786575 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59057.570972 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62004.347298 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 60759.611396 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83107.142857 # average overall mshr miss latency
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62130.911200 # average ReadReq mshr miss latency
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+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.252440 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.098829 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59183.401294 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62336.364578 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 61008.728881 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 91950 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59140.058156 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 59262.842293 # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60047.861507 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62046.459848 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 60738.855032 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83107.142857 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59255.724928 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 59349.507018 # average overall mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59932.341553 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62325.086383 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 60924.998737 # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59140.058156 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 59262.842293 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60047.861507 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62046.459848 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 60738.855032 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59255.724928 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 59349.507018 # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59932.341553 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62325.086383 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 60924.998737 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.toL2Bus.throughput 58696725 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 2675214 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2675214 # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq 2673184 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2673184 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 606690 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 2935 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 2937 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 246039 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 246039 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1976942 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5792286 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42218 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 136665 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 7948111 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 63231360 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85355770 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 62032 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 230312 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 148879474 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 148879474 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 192412 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 4956067661 # Layer occupancy (ticks)
+system.toL2Bus.trans_dist::Writeback 606482 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 2937 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 2940 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 246011 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 246011 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1973853 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5791552 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42247 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 136455 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 7944107 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 63133312 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85325794 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 62264 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 230296 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 148751666 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 33359 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 2344441 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 2344441 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 2344441 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 4954098182 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 4453658755 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 4446552172 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 4478828129 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 4477877910 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 26774357 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 26748853 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 79740148 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 79493732 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.throughput 48628247 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution
-system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution
+system.iobus.trans_dist::ReadReq 16322162 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16322162 # Transaction distribution
system.iobus.trans_dist::WriteReq 8176 # Transaction distribution
system.iobus.trans_dist::WriteResp 8176 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7928 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 520 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1028 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2383056 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2383044 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 123501006 # Total data (bytes)
+system.iobus.pkt_count::total 32660676 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15856 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 2390454 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 123500982 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 3969000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 520000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 2374868000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 38124261327 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 38127481848 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
-system.cpu0.branchPred.lookups 7765284 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 5771603 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 325703 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 4845901 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 3829041 # Number of BTB hits
+system.cpu0.branchPred.lookups 7736387 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 5741528 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 324689 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 4736478 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 3796485 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 79.016080 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 808445 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 22619 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 80.154178 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 808967 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 22406 # Number of incorrect RAS predictions.
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 27181562 # DTB read hits
-system.cpu0.dtb.read_misses 37782 # DTB read misses
-system.cpu0.dtb.write_hits 5596065 # DTB write hits
-system.cpu0.dtb.write_misses 10098 # DTB write misses
+system.cpu0.dtb.read_hits 27184101 # DTB read hits
+system.cpu0.dtb.read_misses 37692 # DTB read misses
+system.cpu0.dtb.write_hits 5601213 # DTB write hits
+system.cpu0.dtb.write_misses 10069 # DTB write misses
system.cpu0.dtb.flush_tlb 510 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 731 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_mva_asid 726 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 5491 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 645 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 284 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 5493 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 558 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 288 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 704 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 27219344 # DTB read accesses
-system.cpu0.dtb.write_accesses 5606163 # DTB write accesses
+system.cpu0.dtb.perms_faults 698 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 27221793 # DTB read accesses
+system.cpu0.dtb.write_accesses 5611282 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 32777627 # DTB hits
-system.cpu0.dtb.misses 47880 # DTB misses
-system.cpu0.dtb.accesses 32825507 # DTB accesses
+system.cpu0.dtb.hits 32785314 # DTB hits
+system.cpu0.dtb.misses 47761 # DTB misses
+system.cpu0.dtb.accesses 32833075 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 5349242 # ITB inst hits
-system.cpu0.itb.inst_misses 7594 # ITB inst misses
+system.cpu0.itb.inst_hits 5349776 # ITB inst hits
+system.cpu0.itb.inst_misses 7612 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 510 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 731 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_mva_asid 726 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 2622 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 2439 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 2424 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 5356836 # ITB inst accesses
-system.cpu0.itb.hits 5349242 # DTB hits
-system.cpu0.itb.misses 7594 # DTB misses
-system.cpu0.itb.accesses 5356836 # DTB accesses
-system.cpu0.numCycles 234138431 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 5357388 # ITB inst accesses
+system.cpu0.itb.hits 5349776 # DTB hits
+system.cpu0.itb.misses 7612 # DTB misses
+system.cpu0.itb.accesses 5357388 # DTB accesses
+system.cpu0.numCycles 234157878 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 14733348 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 42294638 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 7765284 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 4637486 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 215157682 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 899672 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 103093 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles 978 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles 1882 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles 100153 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 1830103 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 127 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 5346345 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 204670 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 3021 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 232377075 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.216391 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 1.156919 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 14748705 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 42201957 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 7736387 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 4605452 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 215146781 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 898208 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 106243 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles 1405 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles 1864 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles 95051 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 1850622 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 160 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 5346983 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 204760 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 2833 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 232399808 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.216000 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 1.156571 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 222728537 95.85% 95.85% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 885926 0.38% 96.23% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 959241 0.41% 96.64% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 1030592 0.44% 97.09% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 1233052 0.53% 97.62% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 718062 0.31% 97.93% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 1129349 0.49% 98.41% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 448984 0.19% 98.60% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 3243332 1.40% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 222777653 95.86% 95.86% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 886693 0.38% 96.24% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 957710 0.41% 96.65% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 1031526 0.44% 97.10% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 1201262 0.52% 97.61% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 716459 0.31% 97.92% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 1131800 0.49% 98.41% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 450199 0.19% 98.60% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 3246506 1.40% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 232377075 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.033165 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.180639 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 12160999 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 212353937 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 6177683 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 1309281 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 372986 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 974074 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 78107 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 45045632 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 258698 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 372986 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 12774661 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 53419035 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 30524585 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 6795741 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 128487965 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 43632543 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 1343 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 95385189 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents 124519108 # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents 1934134 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands 46283925 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 200651385 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 53129662 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 5272 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 36330469 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 9953456 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 576590 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 492282 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 7436987 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 7977179 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 6240861 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1088795 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 1688387 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 41277277 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1012498 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 59014531 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 58753 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 7256631 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 15830718 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 292140 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 232377075 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.253960 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 0.959343 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 232399808 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.033039 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.180229 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 12178110 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 212389955 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 6147086 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 1310186 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 372224 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 973042 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 78155 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 44916036 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 260169 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 372224 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 12790792 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 53545394 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 30504571 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 6768689 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 128415973 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 43504199 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 1378 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 95402427 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 124537502 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 1839930 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands 46109442 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 200228601 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 53009049 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 5261 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 36340147 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 9769295 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 578634 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 493652 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 7443860 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 7970278 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 6245265 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1090249 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 1688574 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 41187030 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 989826 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 58971927 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 58739 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 7127220 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 15644672 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 268943 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 232399808 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.253752 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 0.958915 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 212079469 91.27% 91.27% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 6238226 2.68% 93.95% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 2924438 1.26% 95.21% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2416467 1.04% 96.25% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 6166815 2.65% 98.90% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1071194 0.46% 99.36% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 901941 0.39% 99.75% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 385048 0.17% 99.92% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 193477 0.08% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 212110796 91.27% 91.27% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 6244814 2.69% 93.96% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 2921782 1.26% 95.21% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2401444 1.03% 96.25% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 6174292 2.66% 98.90% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1067597 0.46% 99.36% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 901998 0.39% 99.75% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 384604 0.17% 99.92% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 192481 0.08% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 232377075 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 232399808 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 114630 2.27% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 3 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 4666706 92.48% 94.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 264598 5.24% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 115073 2.28% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 2 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 4670641 92.37% 94.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 270791 5.36% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 15012 0.03% 0.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 25515552 43.24% 43.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 47770 0.08% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 902 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 27508063 46.61% 89.96% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5927232 10.04% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 15020 0.03% 0.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 25465355 43.18% 43.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 47791 0.08% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 896 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 27510585 46.65% 89.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5932280 10.06% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 59014531 # Type of FU issued
-system.cpu0.iq.rate 0.252050 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 5045937 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.085503 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 355498871 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 49563440 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 38260615 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 11956 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 6482 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 5191 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 64039026 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 6430 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 226085 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 58971927 # Type of FU issued
+system.cpu0.iq.rate 0.251847 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 5056507 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.085744 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 355447115 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 49321417 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 38218166 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 11793 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 6394 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 5095 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 64007055 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 6359 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 225424 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1459518 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2588 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 24632 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 672041 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1448099 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 2516 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 24796 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 671952 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 17098280 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 3147229 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 17102895 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 3149110 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 372986 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 50915247 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 1803662 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 42401043 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 79571 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 7977179 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 6240861 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 734817 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 139591 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 1596321 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 24632 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 160350 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 132588 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 292938 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 58604130 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 27345857 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 362682 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 372224 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 50935329 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 1903194 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 42289333 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 78950 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 7970278 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 6245265 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 710795 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 138182 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 1696089 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 24796 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 159500 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 133057 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 292557 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 58565137 # Number of executed instructions
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+system.cpu0.iew.iewExecSquashedInsts 359214 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 111268 # number of nop insts executed
-system.cpu0.iew.exec_refs 33208867 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 5668977 # Number of branches executed
-system.cpu0.iew.exec_stores 5863010 # Number of stores executed
-system.cpu0.iew.exec_rate 0.250297 # Inst execution rate
-system.cpu0.iew.wb_sent 55434698 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 38265806 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 21645924 # num instructions producing a value
-system.cpu0.iew.wb_consumers 38521221 # num instructions consuming a value
+system.cpu0.iew.exec_nop 112477 # number of nop insts executed
+system.cpu0.iew.exec_refs 33216509 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 5651382 # Number of branches executed
+system.cpu0.iew.exec_stores 5868056 # Number of stores executed
+system.cpu0.iew.exec_rate 0.250110 # Inst execution rate
+system.cpu0.iew.wb_sent 55395790 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 38223261 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 21614386 # num instructions producing a value
+system.cpu0.iew.wb_consumers 38462259 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.163432 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.561922 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.163237 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.561964 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 7110536 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 720358 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 248726 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 231246727 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.150700 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 0.849611 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 7051288 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 720883 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 247682 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 231240606 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.150761 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 0.850016 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 218753445 94.60% 94.60% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 6297983 2.72% 97.32% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 1708084 0.74% 98.06% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 1059115 0.46% 98.52% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 644957 0.28% 98.80% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 581299 0.25% 99.05% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 449364 0.19% 99.24% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 245033 0.11% 99.35% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1507447 0.65% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 218744105 94.60% 94.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 6302358 2.73% 97.32% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 1708730 0.74% 98.06% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 1054896 0.46% 98.52% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 648771 0.28% 98.80% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 578680 0.25% 99.05% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 445136 0.19% 99.24% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 245162 0.11% 99.35% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1512768 0.65% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 231246727 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 29059194 # Number of instructions committed
-system.cpu0.commit.committedOps 34848810 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 231240606 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 29065490 # Number of instructions committed
+system.cpu0.commit.committedOps 34862084 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 12086481 # Number of memory references committed
-system.cpu0.commit.loads 6517661 # Number of loads committed
-system.cpu0.commit.membars 192728 # Number of memory barriers committed
-system.cpu0.commit.branches 4958536 # Number of branches committed
-system.cpu0.commit.fp_insts 5174 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 30757342 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 472350 # Number of function calls committed.
+system.cpu0.commit.refs 12095492 # Number of memory references committed
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+system.cpu0.commit.membars 193065 # Number of memory barriers committed
+system.cpu0.commit.branches 4958543 # Number of branches committed
+system.cpu0.commit.fp_insts 5094 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 30770331 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 472637 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 22717072 65.19% 65.19% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 44355 0.13% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult 0 0.00% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult 0 0.00% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift 0 0.00% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 65.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 902 0.00% 65.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 65.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.32% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 6517661 18.70% 84.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 5568820 15.98% 100.00% # Class of committed instruction
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+system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 65.30% # Class of committed instruction
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+system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 65.30% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult 0 0.00% 65.30% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 65.30% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 65.30% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 65.30% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 65.30% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 65.30% # Class of committed instruction
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+system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 65.30% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult 0 0.00% 65.30% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 65.30% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift 0 0.00% 65.30% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 65.30% # Class of committed instruction
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+system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 65.30% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 65.30% # Class of committed instruction
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system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total 34848810 # Class of committed instruction
-system.cpu0.commit.bw_lim_events 1507447 # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total 34862084 # Class of committed instruction
+system.cpu0.commit.bw_lim_events 1512768 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 270795640 # The number of ROB reads
-system.cpu0.rob.rob_writes 85052492 # The number of ROB writes
-system.cpu0.timesIdled 264396 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 1761356 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 2270391996 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 28992496 # Number of Instructions Simulated
-system.cpu0.committedOps 34782112 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 8.075829 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 8.075829 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.123826 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.123826 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 66468797 # number of integer regfile reads
-system.cpu0.int_regfile_writes 24185826 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 44758 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 41844 # number of floating regfile writes
-system.cpu0.cc_regfile_reads 196782773 # number of cc regfile reads
-system.cpu0.cc_regfile_writes 15711716 # number of cc regfile writes
-system.cpu0.misc_regfile_reads 291428250 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 565781 # number of misc regfile writes
-system.cpu0.icache.tags.replacements 988317 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.592753 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 9970376 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 988829 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 10.083013 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 6654117250 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 184.676713 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 326.916040 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.360697 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.638508 # Average percentage of cache occupancy
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+system.cpu0.rob.rob_writes 84952654 # The number of ROB writes
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+system.cpu0.idleCycles 1758070 # Total number of cycles that the CPU has spent unscheduled due to idling
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+system.cpu0.committedInsts 28998871 # Number of Instructions Simulated
+system.cpu0.committedOps 34795465 # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi 8.074724 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 8.074724 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.123843 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.123843 # IPC: Total IPC of All Threads
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+system.cpu0.misc_regfile_writes 565980 # number of misc regfile writes
+system.cpu0.icache.tags.replacements 986757 # number of replacements
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+system.cpu0.icache.tags.total_refs 9965260 # Total number of references to valid blocks.
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+system.cpu0.icache.tags.avg_refs 10.093764 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 6651821250 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 184.507996 # Average occupied blocks per requestor
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+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.360367 # Average percentage of cache occupancy
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system.cpu0.icache.tags.occ_percent::total 0.999205 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 157 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 12025421 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 12025421 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 4823915 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 5146461 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 9970376 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 4823915 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 5146461 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 9970376 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 4823915 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 5146461 # number of overall hits
-system.cpu0.icache.overall_hits::total 9970376 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 522311 # number of ReadReq misses
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system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu0.dcache.tags.warmup_cycle 42094250 # Cycle when the warmup percentage was hit.
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-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26407.375234 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26572.067225 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 28080.800096 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27418.071003 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25412.080003 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27335.661116 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26459.484546 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 8288231 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 6165176 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 342380 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 5156418 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 4057157 # Number of BTB hits
+system.cpu1.branchPred.lookups 8293404 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 6173471 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 340831 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 5168505 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 4065400 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 78.681693 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 881950 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 23449 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 78.657175 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 881063 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 23561 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 28293531 # DTB read hits
-system.cpu1.dtb.read_misses 40544 # DTB read misses
-system.cpu1.dtb.write_hits 6190636 # DTB write hits
-system.cpu1.dtb.write_misses 14491 # DTB write misses
+system.cpu1.dtb.read_hits 28281448 # DTB read hits
+system.cpu1.dtb.read_misses 40913 # DTB read misses
+system.cpu1.dtb.write_hits 6183126 # DTB write hits
+system.cpu1.dtb.write_misses 14267 # DTB write misses
system.cpu1.dtb.flush_tlb 506 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 708 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_mva_asid 713 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 5400 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 865 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 285 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 5407 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 858 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 300 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 723 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 28334075 # DTB read accesses
-system.cpu1.dtb.write_accesses 6205127 # DTB write accesses
+system.cpu1.dtb.perms_faults 709 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 28322361 # DTB read accesses
+system.cpu1.dtb.write_accesses 6197393 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 34484167 # DTB hits
-system.cpu1.dtb.misses 55035 # DTB misses
-system.cpu1.dtb.accesses 34539202 # DTB accesses
+system.cpu1.dtb.hits 34464574 # DTB hits
+system.cpu1.dtb.misses 55180 # DTB misses
+system.cpu1.dtb.accesses 34519754 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 5693555 # ITB inst hits
-system.cpu1.itb.inst_misses 8207 # ITB inst misses
+system.cpu1.itb.inst_hits 5686404 # ITB inst hits
+system.cpu1.itb.inst_misses 8235 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 506 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 708 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_mva_asid 713 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 2675 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 2681 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 2702 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 2705 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 5701762 # ITB inst accesses
-system.cpu1.itb.hits 5693555 # DTB hits
-system.cpu1.itb.misses 8207 # DTB misses
-system.cpu1.itb.accesses 5701762 # DTB accesses
-system.cpu1.numCycles 237058963 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 5694639 # ITB inst accesses
+system.cpu1.itb.hits 5686404 # DTB hits
+system.cpu1.itb.misses 8235 # DTB misses
+system.cpu1.itb.accesses 5694639 # DTB accesses
+system.cpu1.numCycles 237046957 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 15389347 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 44896719 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 8288231 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 4939107 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 217242159 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 949095 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 106364 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles 1987 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles 1943 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles 92979 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 2091650 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 5690360 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 215494 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 3361 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 235400962 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.228809 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 1.188674 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 15347817 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 44890949 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 8293404 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 4946463 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 217272167 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 945647 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 107708 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles 1915 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles 1869 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles 102411 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 2087291 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 117 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 5683206 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 214159 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 3400 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 235393992 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.228723 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 1.188286 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 225085908 95.62% 95.62% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 947634 0.40% 96.02% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 1047135 0.44% 96.47% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 1048515 0.45% 96.91% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1240998 0.53% 97.44% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 829745 0.35% 97.79% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1296822 0.55% 98.34% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 452969 0.19% 98.53% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 3451236 1.47% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 225080067 95.62% 95.62% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 947919 0.40% 96.02% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 1046635 0.44% 96.47% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 1047767 0.45% 96.91% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1244626 0.53% 97.44% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 829831 0.35% 97.79% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1297650 0.55% 98.34% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 454057 0.19% 98.54% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 3445440 1.46% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 235400962 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.034963 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.189391 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 12590716 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 214453384 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 6500032 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 1465156 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 389454 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 1047596 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 86470 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 48240012 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 288766 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 389454 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 13272686 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 54002992 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 31282477 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 7201814 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 129249426 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 46761611 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 1258 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 95572539 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 124561907 # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents 2450017 # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands 49620172 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 215588900 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 57377506 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 4944 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 39615169 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 10004995 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 609511 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 515718 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 8221045 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 8459299 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 6818667 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 1033426 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1557443 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 44314605 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 1045489 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 62743783 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 61525 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 7205140 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 16025571 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 281591 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 235400962 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.266540 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 0.981476 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 235393992 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.034986 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.189376 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 12555511 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 214484659 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 6498538 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 1464859 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 388308 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 1045918 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 85921 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 48232824 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 288029 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 388308 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 13237235 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 54097542 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 31323893 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 7199069 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 129145928 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 46754074 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 1435 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 95558668 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 124530529 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 2374363 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands 49626992 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 215510826 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 57366811 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 4976 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 39600958 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 10026026 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 608668 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 515191 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 8234978 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 8452340 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 6808261 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 1032874 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 1526046 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 44303656 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1049317 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 62721282 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 61124 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 7218810 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 16029580 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 286052 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 235393992 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.266452 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 0.981415 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 213793871 90.82% 90.82% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 6637383 2.82% 93.64% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 3199231 1.36% 95.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 2579548 1.10% 96.10% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 6422119 2.73% 98.82% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1152982 0.49% 99.31% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 1001630 0.43% 99.74% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 407456 0.17% 99.91% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 206742 0.09% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 213794873 90.82% 90.82% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 6639662 2.82% 93.64% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 3193505 1.36% 95.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 2580445 1.10% 96.10% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 6412648 2.72% 98.82% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1155018 0.49% 99.31% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 1003845 0.43% 99.74% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 407445 0.17% 99.91% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 206551 0.09% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 235400962 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 235393992 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 146491 2.81% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 1 0.00% 2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 146677 2.81% 2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 3 0.00% 2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 4788852 91.80% 94.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 281237 5.39% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 4785763 91.77% 94.59% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 282272 5.41% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 13506 0.02% 0.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 27516436 43.86% 43.88% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 46370 0.07% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 1209 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 28654021 45.67% 89.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 6512241 10.38% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 13498 0.02% 0.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 27514443 43.87% 43.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 46382 0.07% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 1213 0.00% 43.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 28642016 45.67% 89.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 6503730 10.37% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 62743783 # Type of FU issued
-system.cpu1.iq.rate 0.264676 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 5216581 # FU busy when requested
+system.cpu1.iq.FU_type_0::total 62721282 # Type of FU issued
+system.cpu1.iq.rate 0.264594 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 5214715 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.083141 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 366155152 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 52582376 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 41291326 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 11482 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 6074 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 5054 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 67940659 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 6199 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 226253 # Number of loads that had data forwarded from stores
+system.cpu1.iq.int_inst_queue_reads 366100496 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 52588764 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 41277568 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 11899 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 6202 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 5156 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 67916046 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 6453 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 226153 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 1460814 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 2639 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 24306 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 652998 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 1459547 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 2673 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 24270 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 647934 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 17101900 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 3881798 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 17097171 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 3878321 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 389454 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 50160792 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 3093797 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 45494090 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 85835 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 8459299 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 6818667 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 741438 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 149727 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 2862513 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 24306 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 166054 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 139765 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 305819 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 62318890 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 28486625 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 369994 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 388308 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 50150951 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 3201381 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 45487056 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 83691 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 8452340 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 6808261 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 746320 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 150012 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 2969807 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 24270 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 165680 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 138748 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 304428 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 62296746 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 28474223 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 369499 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 133996 # number of nop insts executed
-system.cpu1.iew.exec_refs 34929125 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 6064585 # Number of branches executed
-system.cpu1.iew.exec_stores 6442500 # Number of stores executed
-system.cpu1.iew.exec_rate 0.262884 # Inst execution rate
-system.cpu1.iew.wb_sent 58464614 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 41296380 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 23329556 # num instructions producing a value
-system.cpu1.iew.wb_consumers 41830645 # num instructions consuming a value
+system.cpu1.iew.exec_nop 134083 # number of nop insts executed
+system.cpu1.iew.exec_refs 34908741 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 6065757 # Number of branches executed
+system.cpu1.iew.exec_stores 6434518 # Number of stores executed
+system.cpu1.iew.exec_rate 0.262803 # Inst execution rate
+system.cpu1.iew.wb_sent 58446379 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 41282724 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 23334628 # num instructions producing a value
+system.cpu1.iew.wb_consumers 41837805 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.174203 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.557714 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.174154 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.557740 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 7169441 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 763898 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 257160 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 234250313 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.162130 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 0.884909 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 7166738 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 763265 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 256189 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 234203986 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.162086 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 0.884581 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 220821840 94.27% 94.27% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 6746509 2.88% 97.15% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 1771690 0.76% 97.90% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1085849 0.46% 98.37% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 731494 0.31% 98.68% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 648369 0.28% 98.96% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 505518 0.22% 99.17% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 281725 0.12% 99.29% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1657319 0.71% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 220778060 94.27% 94.27% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 6743716 2.88% 97.15% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 1772623 0.76% 97.90% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1087484 0.46% 98.37% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 731864 0.31% 98.68% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 647370 0.28% 98.96% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 507514 0.22% 99.17% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 282341 0.12% 99.29% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1653014 0.71% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 234250313 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 31416794 # Number of instructions committed
-system.cpu1.commit.committedOps 37978992 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 234203986 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 31407169 # Number of instructions committed
+system.cpu1.commit.committedOps 37961303 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 13164154 # Number of memory references committed
-system.cpu1.commit.loads 6998485 # Number of loads committed
-system.cpu1.commit.membars 211048 # Number of memory barriers committed
-system.cpu1.commit.branches 5351716 # Number of branches committed
-system.cpu1.commit.fp_insts 5038 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 33506635 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 519749 # Number of function calls committed.
+system.cpu1.commit.refs 13153120 # Number of memory references committed
+system.cpu1.commit.loads 6992793 # Number of loads committed
+system.cpu1.commit.membars 210663 # Number of memory barriers committed
+system.cpu1.commit.branches 5351172 # Number of branches committed
+system.cpu1.commit.fp_insts 5118 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 33489601 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 519360 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 24770094 65.22% 65.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 43535 0.11% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 1209 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 6998485 18.43% 83.77% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 6165669 16.23% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 24763487 65.23% 65.23% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 43483 0.11% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc 1213 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead 6992793 18.42% 83.77% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite 6160327 16.23% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 37978992 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 1657319 # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total 37961303 # Class of committed instruction
+system.cpu1.commit.bw_lim_events 1653014 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 276790751 # The number of ROB reads
-system.cpu1.rob.rob_writes 91451122 # The number of ROB writes
-system.cpu1.timesIdled 270857 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 1658001 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 2279071980 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 31333111 # Number of Instructions Simulated
-system.cpu1.committedOps 37895309 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 7.565765 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 7.565765 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.132174 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.132174 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 71132794 # number of integer regfile reads
-system.cpu1.int_regfile_writes 26016814 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 44316 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 42056 # number of floating regfile writes
-system.cpu1.cc_regfile_reads 209312794 # number of cc regfile reads
-system.cpu1.cc_regfile_writes 17049814 # number of cc regfile writes
-system.cpu1.misc_regfile_reads 299103919 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 609097 # number of misc regfile writes
+system.cpu1.rob.rob_reads 276729293 # The number of ROB reads
+system.cpu1.rob.rob_writes 91408516 # The number of ROB writes
+system.cpu1.timesIdled 270232 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 1652965 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 2279190242 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 31323407 # Number of Instructions Simulated
+system.cpu1.committedOps 37877541 # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi 7.567726 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 7.567726 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.132140 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.132140 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 71111518 # number of integer regfile reads
+system.cpu1.int_regfile_writes 26004877 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 44415 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 42120 # number of floating regfile writes
+system.cpu1.cc_regfile_reads 209232786 # number of cc regfile reads
+system.cpu1.cc_regfile_writes 17062784 # number of cc regfile writes
+system.cpu1.misc_regfile_reads 298304880 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 608841 # number of misc regfile writes
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1732377463327 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1732377463327 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1732377463327 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1732377463327 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1732753268848 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1732753268848 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1732753268848 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1732753268848 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 83365 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 83356 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- Begin Simulation Statistics ----------
-sim_seconds 2.626162 # Number of seconds simulated
-sim_ticks 2626161554000 # Number of ticks simulated
-final_tick 2626161554000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.627904 # Number of seconds simulated
+sim_ticks 2627903712000 # Number of ticks simulated
+final_tick 2627903712000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 476066 # Simulator instruction rate (inst/s)
-host_op_rate 568569 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 20761634862 # Simulator tick rate (ticks/s)
-host_mem_usage 472496 # Number of bytes of host memory used
-host_seconds 126.49 # Real time elapsed on the host
-sim_insts 60218144 # Number of instructions simulated
-sim_ops 71918894 # Number of ops (including micro ops) simulated
+host_inst_rate 497056 # Simulator instruction rate (inst/s)
+host_op_rate 593637 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 21691918305 # Simulator tick rate (ticks/s)
+host_mem_usage 460332 # Number of bytes of host memory used
+host_seconds 121.15 # Real time elapsed on the host
+sim_insts 60216663 # Number of instructions simulated
+sim_ops 71917112 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 306888 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4490328 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 306056 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4559448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 399040 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4560448 # Number of bytes read from this memory
-system.physmem.bytes_read::total 134013152 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 306888 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 399040 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 399872 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 4486720 # Number of bytes read from this memory
+system.physmem.bytes_read::total 134008544 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 306056 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 399872 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 705928 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3677952 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1536620 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 1479452 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6694024 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 3673856 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 1536536 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 1479536 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6689928 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 11007 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 70187 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 10994 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 71267 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 6235 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 71257 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15690721 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 57468 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 384155 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 369863 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 811486 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47314780 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu1.inst 6248 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 70105 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15690649 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 57404 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 384134 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 369884 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 811422 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47283413 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 116858 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1709845 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 116464 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1735013 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 151948 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1736545 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51030049 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 116858 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 151948 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 268806 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1400505 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 585120 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 563351 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2548976 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1400505 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47314780 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 152164 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 1707338 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 50994465 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 116464 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 152164 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 268628 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1398018 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 584700 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 563010 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2545728 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1398018 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47283413 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 116858 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 2294965 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 116464 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 2319714 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 151948 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 2299897 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53579025 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15690721 # Number of read requests accepted
-system.physmem.writeReqs 811486 # Number of write requests accepted
-system.physmem.readBursts 15690721 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 811486 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 1004205504 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 640 # Total number of bytes read from write queue
-system.physmem.bytesWritten 6711360 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 134013152 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 6694024 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 706602 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 4522 # Number of requests that are neither read nor write
+system.physmem.bw_total::cpu1.inst 152164 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 2270348 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53540193 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15690649 # Number of read requests accepted
+system.physmem.writeReqs 811422 # Number of write requests accepted
+system.physmem.readBursts 15690649 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 811422 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 1004200960 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue
+system.physmem.bytesWritten 6711168 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 134008544 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 6689928 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 706554 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 4516 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 980414 # Per bank write bursts
-system.physmem.perBankRdBursts::1 980046 # Per bank write bursts
-system.physmem.perBankRdBursts::2 979991 # Per bank write bursts
+system.physmem.perBankRdBursts::1 980044 # Per bank write bursts
+system.physmem.perBankRdBursts::2 979984 # Per bank write bursts
system.physmem.perBankRdBursts::3 980262 # Per bank write bursts
system.physmem.perBankRdBursts::4 986671 # Per bank write bursts
system.physmem.perBankRdBursts::5 980424 # Per bank write bursts
-system.physmem.perBankRdBursts::6 980568 # Per bank write bursts
+system.physmem.perBankRdBursts::6 980555 # Per bank write bursts
system.physmem.perBankRdBursts::7 980428 # Per bank write bursts
-system.physmem.perBankRdBursts::8 980784 # Per bank write bursts
+system.physmem.perBankRdBursts::8 980781 # Per bank write bursts
system.physmem.perBankRdBursts::9 980432 # Per bank write bursts
system.physmem.perBankRdBursts::10 979731 # Per bank write bursts
-system.physmem.perBankRdBursts::11 979594 # Per bank write bursts
-system.physmem.perBankRdBursts::12 980346 # Per bank write bursts
-system.physmem.perBankRdBursts::13 980257 # Per bank write bursts
+system.physmem.perBankRdBursts::11 979566 # Per bank write bursts
+system.physmem.perBankRdBursts::12 980337 # Per bank write bursts
+system.physmem.perBankRdBursts::13 980248 # Per bank write bursts
system.physmem.perBankRdBursts::14 980396 # Per bank write bursts
system.physmem.perBankRdBursts::15 980367 # Per bank write bursts
-system.physmem.perBankWrBursts::0 6649 # Per bank write bursts
-system.physmem.perBankWrBursts::1 6328 # Per bank write bursts
-system.physmem.perBankWrBursts::2 6318 # Per bank write bursts
+system.physmem.perBankWrBursts::0 6669 # Per bank write bursts
+system.physmem.perBankWrBursts::1 6337 # Per bank write bursts
+system.physmem.perBankWrBursts::2 6309 # Per bank write bursts
system.physmem.perBankWrBursts::3 6427 # Per bank write bursts
-system.physmem.perBankWrBursts::4 6389 # Per bank write bursts
-system.physmem.perBankWrBursts::5 6673 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6856 # Per bank write bursts
-system.physmem.perBankWrBursts::7 6766 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7040 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6684 # Per bank write bursts
-system.physmem.perBankWrBursts::10 6144 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6041 # Per bank write bursts
-system.physmem.perBankWrBursts::12 6664 # Per bank write bursts
-system.physmem.perBankWrBursts::13 6480 # Per bank write bursts
-system.physmem.perBankWrBursts::14 6708 # Per bank write bursts
-system.physmem.perBankWrBursts::15 6698 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2626157242500 # Total gap between requests
+system.physmem.totGap 2627899414000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 6644 # Read request sizes (log2)
system.physmem.readPktSize::3 15532042 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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-system.physmem.bytesPerActivate::samples 1040256 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 971.796235 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 905.926694 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 203.945376 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 22813 2.19% 2.19% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::256-383 8969 0.86% 5.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2415 0.23% 5.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2270 0.22% 5.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1819 0.17% 5.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 9086 0.87% 6.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 877 0.08% 6.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 969093 93.16% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1040256 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5997 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 2616.425880 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 48628.845120 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-65535 5973 99.60% 99.60% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::131072-196607 7 0.12% 99.72% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-262143 4 0.07% 99.78% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 1040215 # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::total 1040215 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::393216-458751 2 0.03% 99.82% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.83% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.85% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.87% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 7 0.12% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5997 # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::mean 17.486243 # Writes before turning the bus around for reads
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-system.physmem.avgQLat 25749.13 # Average queueing delay per DRAM burst
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+system.physmem.avgQLat 25663.99 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44499.13 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 382.39 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.56 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 51.03 # Average system read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 44413.99 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 382.13 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.55 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 50.99 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 3.01 # Data bus utilization in percentage
system.physmem.busUtilRead 2.99 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 6.57 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 16.75 # Average write queue length when enqueuing
-system.physmem.readRowHits 14667428 # Number of row buffer hits during reads
-system.physmem.writeRowHits 87892 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
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system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined
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system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes)
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system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
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system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
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-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20010 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 49988 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 7549283 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54763036 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83799850 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28424 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 78676 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 138669986 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 138669986 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 170112 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 4808749000 # Layer occupancy (ticks)
+system.toL2Bus.trans_dist::Writeback 596597 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 2901 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 2901 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 247697 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 247697 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725344 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5754019 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20105 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50232 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 7549700 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54760476 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83807014 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28584 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79048 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 138675122 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 18167 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 2128077 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 2128077 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 2128077 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 4809198500 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 3866196743 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 3866085496 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 4420580083 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 4420737429 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 12904000 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 12959000 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 30319250 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 30470250 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.throughput 48225066 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 16715396 # Transaction distribution
-system.iobus.trans_dist::ReadResp 16715396 # Transaction distribution
+system.iobus.trans_dist::ReadReq 16715395 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16715395 # Transaction distribution
system.iobus.trans_dist::WriteReq 8184 # Transaction distribution
system.iobus.trans_dist::WriteResp 8184 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7948 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1044 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2383096 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2383094 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 33447160 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15896 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2088 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 2390558 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 126646814 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 126646814 # Total data (bytes)
+system.iobus.pkt_count::total 33447158 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2088 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 2390554 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 126646810 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 3979000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2374912000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy 15532032000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 2374910000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 39164946750 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 39130786750 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 6652404 # DTB read hits
-system.cpu0.dtb.read_misses 6867 # DTB read misses
-system.cpu0.dtb.write_hits 5702862 # DTB write hits
-system.cpu0.dtb.write_misses 1758 # DTB write misses
-system.cpu0.dtb.flush_tlb 2489 # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits 6554416 # DTB read hits
+system.cpu0.dtb.read_misses 6570 # DTB read misses
+system.cpu0.dtb.write_hits 5649486 # DTB write hits
+system.cpu0.dtb.write_misses 1771 # DTB write misses
+system.cpu0.dtb.flush_tlb 2491 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 6327 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid 701 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 28 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 6094 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 129 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 127 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 214 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 6659271 # DTB read accesses
-system.cpu0.dtb.write_accesses 5704620 # DTB write accesses
+system.cpu0.dtb.perms_faults 206 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 6560986 # DTB read accesses
+system.cpu0.dtb.write_accesses 5651257 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 12355266 # DTB hits
-system.cpu0.dtb.misses 8625 # DTB misses
-system.cpu0.dtb.accesses 12363891 # DTB accesses
+system.cpu0.dtb.hits 12203902 # DTB hits
+system.cpu0.dtb.misses 8341 # DTB misses
+system.cpu0.dtb.accesses 12212243 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 30639417 # ITB inst hits
-system.cpu0.itb.inst_misses 3605 # ITB inst misses
+system.cpu0.itb.inst_hits 30237068 # ITB inst hits
+system.cpu0.itb.inst_misses 3286 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 2489 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb 2491 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2770 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 701 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 28 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 2575 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 30643022 # ITB inst accesses
-system.cpu0.itb.hits 30639417 # DTB hits
-system.cpu0.itb.misses 3605 # DTB misses
-system.cpu0.itb.accesses 30643022 # DTB accesses
-system.cpu0.numCycles 2625139831 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 30240354 # ITB inst accesses
+system.cpu0.itb.hits 30237068 # DTB hits
+system.cpu0.itb.misses 3286 # DTB misses
+system.cpu0.itb.accesses 30240354 # DTB accesses
+system.cpu0.numCycles 2626678485 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 30062808 # Number of instructions committed
-system.cpu0.committedOps 36081752 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 32258130 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 5851 # Number of float alu accesses
-system.cpu0.num_func_calls 1105626 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 3807715 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 32258130 # number of integer instructions
-system.cpu0.num_fp_insts 5851 # number of float instructions
-system.cpu0.num_int_register_reads 58404320 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 21560333 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 4184 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 1670 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 129650201 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 14353458 # number of times the CC registers were written
-system.cpu0.num_mem_refs 12793226 # number of memory refs
-system.cpu0.num_load_insts 6826552 # Number of load instructions
-system.cpu0.num_store_insts 5966674 # Number of store instructions
-system.cpu0.num_idle_cycles 2291568668.895058 # Number of idle cycles
-system.cpu0.num_busy_cycles 333571162.104942 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.127068 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.872932 # Percentage of idle cycles
-system.cpu0.Branches 5192489 # Number of branches fetched
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103509639251 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208315207337 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024990 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026178 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.025588 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024427 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024582 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.405988 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.391579 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.398948 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048503 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043758 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046177 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024724 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025433 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.025079 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028001 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028434 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.028218 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11979.369508 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11592.953814 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11780.390067 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42740.384905 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43022.134234 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42880.988611 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16806.578638 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16494.840246 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16657.087797 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11375.367167 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12612.417686 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11949.947566 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26339.543065 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25768.662677 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26049.740170 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25151.564832 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24722.030271 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24934.947711 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 6516178 # DTB read hits
-system.cpu1.dtb.read_misses 7066 # DTB read misses
-system.cpu1.dtb.write_hits 5531450 # DTB write hits
-system.cpu1.dtb.write_misses 1844 # DTB write misses
-system.cpu1.dtb.flush_tlb 2489 # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits 6613806 # DTB read hits
+system.cpu1.dtb.read_misses 7420 # DTB read misses
+system.cpu1.dtb.write_hits 5584575 # DTB write hits
+system.cpu1.dtb.write_misses 1868 # DTB write misses
+system.cpu1.dtb.flush_tlb 2491 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 6501 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid 738 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 35 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 6816 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 152 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 238 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 6523244 # DTB read accesses
-system.cpu1.dtb.write_accesses 5533294 # DTB write accesses
+system.cpu1.dtb.perms_faults 246 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 6621226 # DTB read accesses
+system.cpu1.dtb.write_accesses 5586443 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 12047628 # DTB hits
-system.cpu1.dtb.misses 8910 # DTB misses
-system.cpu1.dtb.accesses 12056538 # DTB accesses
+system.cpu1.dtb.hits 12198381 # DTB hits
+system.cpu1.dtb.misses 9288 # DTB misses
+system.cpu1.dtb.accesses 12207669 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 30872911 # ITB inst hits
-system.cpu1.itb.inst_misses 3673 # ITB inst misses
+system.cpu1.itb.inst_hits 31273770 # ITB inst hits
+system.cpu1.itb.inst_misses 4023 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 2489 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb 2491 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 2794 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 738 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 35 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 3046 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 30876584 # ITB inst accesses
-system.cpu1.itb.hits 30872911 # DTB hits
-system.cpu1.itb.misses 3673 # DTB misses
-system.cpu1.itb.accesses 30876584 # DTB accesses
-system.cpu1.numCycles 2627183277 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 31277793 # ITB inst accesses
+system.cpu1.itb.hits 31273770 # DTB hits
+system.cpu1.itb.misses 4023 # DTB misses
+system.cpu1.itb.accesses 31277793 # DTB accesses
+system.cpu1.numCycles 2629128939 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 30155336 # Number of instructions committed
-system.cpu1.committedOps 35837142 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 32021976 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 4418 # Number of float alu accesses
-system.cpu1.num_func_calls 1035067 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 3744201 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 32021976 # number of integer instructions
-system.cpu1.num_fp_insts 4418 # number of float instructions
-system.cpu1.num_int_register_reads 57765753 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 21325005 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 3309 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 1110 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 128250854 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 14653287 # number of times the CC registers were written
-system.cpu1.num_mem_refs 12466012 # number of memory refs
-system.cpu1.num_load_insts 6694911 # Number of load instructions
-system.cpu1.num_store_insts 5771101 # Number of store instructions
-system.cpu1.num_idle_cycles 2287259017.662607 # Number of idle cycles
-system.cpu1.num_busy_cycles 339924259.337393 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.129387 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.870613 # Percentage of idle cycles
-system.cpu1.Branches 5118153 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 15840 0.04% 0.04% # Class of executed instruction
-system.cpu1.op_class::IntAlu 23832212 65.55% 65.59% # Class of executed instruction
-system.cpu1.op_class::IntMult 42672 0.12% 65.71% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 1070 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.71% # Class of executed instruction
-system.cpu1.op_class::MemRead 6694911 18.41% 84.13% # Class of executed instruction
-system.cpu1.op_class::MemWrite 5771101 15.87% 100.00% # Class of executed instruction
+system.cpu1.committedInsts 30562057 # Number of instructions committed
+system.cpu1.committedOps 36321926 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 32452923 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 4971 # Number of float alu accesses
+system.cpu1.num_func_calls 1056400 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 3813741 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 32452923 # number of integer instructions
+system.cpu1.num_fp_insts 4971 # number of float instructions
+system.cpu1.num_int_register_reads 58477662 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 21639168 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 3605 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 1368 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 130057431 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 14822724 # number of times the CC registers were written
+system.cpu1.num_mem_refs 12626030 # number of memory refs
+system.cpu1.num_load_insts 6797131 # Number of load instructions
+system.cpu1.num_store_insts 5828899 # Number of store instructions
+system.cpu1.num_idle_cycles 2287592720.742589 # Number of idle cycles
+system.cpu1.num_busy_cycles 341536218.257411 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.129905 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.870095 # Percentage of idle cycles
+system.cpu1.Branches 5215542 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 17085 0.05% 0.05% # Class of executed instruction
+system.cpu1.op_class::IntAlu 24167965 65.58% 65.62% # Class of executed instruction
+system.cpu1.op_class::IntMult 43107 0.12% 65.74% # Class of executed instruction
+system.cpu1.op_class::IntDiv 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 1123 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.74% # Class of executed instruction
+system.cpu1.op_class::MemRead 6797131 18.44% 84.18% # Class of executed instruction
+system.cpu1.op_class::MemWrite 5828899 15.82% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 36357806 # Class of executed instruction
+system.cpu1.op_class::total 36855310 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.iocache.tags.replacements 0 # number of replacements
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1781125703750 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1781125703750 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1781125703750 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1781125703750 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1779782747750 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1779782747750 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1779782747750 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1779782747750 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 5.129874 # Number of seconds simulated
-sim_ticks 5129873616500 # Number of ticks simulated
-final_tick 5129873616500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.129877 # Number of seconds simulated
+sim_ticks 5129876981500 # Number of ticks simulated
+final_tick 5129876981500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 122712 # Simulator instruction rate (inst/s)
-host_op_rate 242564 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1543734215 # Simulator tick rate (ticks/s)
-host_mem_usage 750608 # Number of bytes of host memory used
-host_seconds 3323.03 # Real time elapsed on the host
-sim_insts 407773893 # Number of instructions simulated
-sim_ops 806048632 # Number of ops (including micro ops) simulated
+host_inst_rate 179907 # Simulator instruction rate (inst/s)
+host_op_rate 355619 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2263051238 # Simulator tick rate (ticks/s)
+host_mem_usage 804092 # Number of bytes of host memory used
+host_seconds 2266.80 # Real time elapsed on the host
+sim_insts 407812863 # Number of instructions simulated
+sim_ops 806114915 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 4224 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1049344 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10817792 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11900032 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1049344 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1049344 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6600896 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker 4096 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1048192 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10832768 # Number of bytes read from this memory
+system.physmem.bytes_read::total 11913792 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1048192 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9590976 # Number of bytes written to this memory
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system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 66 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 16396 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 169028 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 185938 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 103139 # Number of write requests responded to by this memory
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system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 149859 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 149802 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 5527 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 823 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 204556 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2108783 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2319751 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 204556 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 204556 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1286756 # Write bandwidth from this memory (bytes/s)
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+system.physmem.bw_read::cpu.data 2111701 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_inst_read::total 204331 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::pc.south_bridge.ide 582876 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1869632 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1286756 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 588403 # Total bandwidth to/from this memory (bytes/s)
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-system.physmem.bw_total::cpu.data 2108783 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4189384 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 185938 # Number of read requests accepted
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-system.physmem.readBursts 185938 # Number of DRAM read bursts, including those serviced by the write queue
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-system.physmem.bytesReadWrQ 18880 # Total number of bytes read from write queue
-system.physmem.bytesWritten 9589248 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 11900032 # Total read bytes from the system interface side
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-system.physmem.servicedByWrQ 295 # Number of DRAM read bursts serviced by the write queue
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+system.physmem.servicedByWrQ 288 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 1710 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 11383 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 4 # Number of times write queue was full causing retry
-system.physmem.totGap 5129873502000 # Total gap between requests
+system.physmem.numWrRetry 2 # Number of times write queue was full causing retry
+system.physmem.totGap 5129876930000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
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-system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
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-system.physmem.bytesPerActivate::mean 298.717718 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 177.081512 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 320.465816 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 27438 38.17% 38.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 17395 24.20% 62.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 7359 10.24% 72.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 4225 5.88% 78.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2947 4.10% 82.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2054 2.86% 85.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1404 1.95% 87.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1166 1.62% 89.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 7887 10.97% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 71875 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 7354 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 25.241501 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 560.072825 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 7353 99.99% 99.99% # Reads before turning the bus around for writes
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+system.physmem.bytesPerActivate::stdev 318.841917 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 28215 38.81% 38.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 17447 24.00% 62.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 7490 10.30% 73.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 4112 5.66% 78.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 3047 4.19% 82.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2009 2.76% 85.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1387 1.91% 87.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1145 1.57% 89.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 7848 10.80% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 72700 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 7372 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 25.211883 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 559.387781 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 7371 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 7354 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 7354 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.374218 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.656947 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 12.477131 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 6319 85.93% 85.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 51 0.69% 86.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 33 0.45% 87.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 263 3.58% 90.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 273 3.71% 94.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 24 0.33% 94.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 24 0.33% 95.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 15 0.20% 95.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 39 0.53% 95.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 6 0.08% 95.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 3 0.04% 95.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 1 0.01% 95.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 229 3.11% 98.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 5 0.07% 99.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 3 0.04% 99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 2 0.03% 99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 25 0.34% 99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 13 0.18% 99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 2 0.03% 99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 3 0.04% 99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 5 0.07% 99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 1 0.01% 99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 2 0.03% 99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 10 0.14% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 1 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 7354 # Writes before turning the bus around for reads
-system.physmem.totQLat 1988147750 # Total ticks spent queuing
-system.physmem.totMemAccLat 5468954000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 928215000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10709.52 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 7372 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 7372 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 20.317824 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.630780 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 12.249046 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 6322 85.76% 85.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 58 0.79% 86.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 24 0.33% 86.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 276 3.74% 90.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 291 3.95% 94.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 18 0.24% 94.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 12 0.16% 94.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 14 0.19% 95.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 37 0.50% 95.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 4 0.05% 95.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 3 0.04% 95.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 3 0.04% 95.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 249 3.38% 99.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 3 0.04% 99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 4 0.05% 99.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 4 0.05% 99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 19 0.26% 99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 1 0.01% 99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 7 0.09% 99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 1 0.01% 99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 1 0.01% 99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 2 0.03% 99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 6 0.08% 99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 1 0.01% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 1 0.01% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 7 0.09% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 1 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 2 0.03% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 7372 # Writes before turning the bus around for reads
+system.physmem.totQLat 2030519500 # Total ticks spent queuing
+system.physmem.totMemAccLat 5515488250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 929325000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 10924.70 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29459.52 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 29674.70 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 22.59 # Average write queue length when enqueuing
-system.physmem.readRowHits 152685 # Number of row buffer hits during reads
-system.physmem.writeRowHits 110914 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 74.01 # Row buffer hit rate for writes
-system.physmem.avgGap 15276710.34 # Average gap between requests
-system.physmem.pageHitRate 78.57 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 4923726743250 # Time in different power states
+system.physmem.avgRdQLen 1.49 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.68 # Average write queue length when enqueuing
+system.physmem.readRowHits 152396 # Number of row buffer hits during reads
+system.physmem.writeRowHits 110551 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.80 # Row buffer hit rate for writes
+system.physmem.avgGap 15269535.89 # Average gap between requests
+system.physmem.pageHitRate 78.34 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 4923406969000 # Time in different power states
system.physmem.memoryStateTime::REF 171297620000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 34849149750 # Time in different power states
+system.physmem.memoryStateTime::ACT 35172289500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 4545861 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 662568 # Transaction distribution
-system.membus.trans_dist::ReadResp 662557 # Transaction distribution
+system.membus.trans_dist::ReadReq 662528 # Transaction distribution
+system.membus.trans_dist::ReadResp 662520 # Transaction distribution
system.membus.trans_dist::WriteReq 13776 # Transaction distribution
system.membus.trans_dist::WriteResp 13776 # Transaction distribution
-system.membus.trans_dist::Writeback 103139 # Transaction distribution
+system.membus.trans_dist::Writeback 103082 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 2217 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 1710 # Transaction distribution
-system.membus.trans_dist::ReadExReq 133156 # Transaction distribution
-system.membus.trans_dist::ReadExResp 133153 # Transaction distribution
-system.membus.trans_dist::MessageReq 1644 # Transaction distribution
-system.membus.trans_dist::MessageResp 1644 # Transaction distribution
-system.membus.trans_dist::BadAddressError 11 # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::UpgradeReq 2203 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 1739 # Transaction distribution
+system.membus.trans_dist::ReadExReq 133413 # Transaction distribution
+system.membus.trans_dist::ReadExResp 133410 # Transaction distribution
+system.membus.trans_dist::MessageReq 1645 # Transaction distribution
+system.membus.trans_dist::MessageResp 1645 # Transaction distribution
+system.membus.trans_dist::BadAddressError 8 # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775070 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478059 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 22 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724235 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94797 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 94797 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1822320 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550137 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18472576 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20264541 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 23289549 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 23289549 # Total data (bytes)
-system.membus.snoop_data_through_bus 30144 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 251288000 # Layer occupancy (ticks)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478447 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724617 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94802 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 94802 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1822709 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550137 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18482688 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20274653 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 23299665 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 943 # Total snoops (count)
+system.membus.snoop_fanout::samples 338647 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 338647 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 338647 # Request fanout histogram
+system.membus.reqLayer0.occupancy 251233500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 583699000 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 583254000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 3290000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 1574361000 # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy 1574333248 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 13500 # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy 9500 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy 1645000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 3158618040 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 3160566012 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer4.occupancy 54966743 # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy 55015741 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 47579 # number of replacements
-system.iocache.tags.tagsinuse 0.103859 # Cycle average of tags in use
+system.iocache.tags.replacements 47584 # number of replacements
+system.iocache.tags.tagsinuse 0.103867 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 47600 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 4992945696000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103859 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006491 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.006491 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 4992945897000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103867 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006492 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.006492 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 428706 # Number of tag accesses
-system.iocache.tags.data_accesses 428706 # Number of data accesses
+system.iocache.tags.tag_accesses 428751 # Number of tag accesses
+system.iocache.tags.data_accesses 428751 # Number of data accesses
system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
-system.iocache.ReadReq_misses::pc.south_bridge.ide 914 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 914 # number of ReadReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 914 # number of demand (read+write) misses
-system.iocache.demand_misses::total 914 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 914 # number of overall misses
-system.iocache.overall_misses::total 914 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152667446 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 152667446 # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 152667446 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 152667446 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 152667446 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 152667446 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 914 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 914 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_misses::pc.south_bridge.ide 919 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 919 # number of ReadReq misses
+system.iocache.demand_misses::pc.south_bridge.ide 919 # number of demand (read+write) misses
+system.iocache.demand_misses::total 919 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 919 # number of overall misses
+system.iocache.overall_misses::total 919 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 156299196 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 156299196 # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 156299196 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 156299196 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 156299196 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 156299196 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 919 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 919 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 914 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 914 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 914 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 914 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 919 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 919 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 919 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 919 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167032.216630 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 167032.216630 # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167032.216630 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 167032.216630 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167032.216630 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 167032.216630 # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 170075.294886 # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 170075.294886 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 170075.294886 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 46720 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 914 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 914 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 919 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 919 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 914 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 914 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 914 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 914 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105114946 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 105114946 # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2850047667 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2850047667 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 105114946 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 105114946 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 105114946 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 105114946 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 919 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 919 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 919 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 919 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 108481196 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2843906419 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2843906419 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 108481196 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 108481196 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 115005.411379 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 61002.732598 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 61002.732598 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 115005.411379 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 115005.411379 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 118042.650707 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60871.284653 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60871.284653 # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 118042.650707 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 118042.650707 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.iobus.throughput 638663 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 225570 # Transaction distribution
-system.iobus.trans_dist::ReadResp 225570 # Transaction distribution
+system.iobus.trans_dist::ReadReq 225575 # Transaction distribution
+system.iobus.trans_dist::ReadResp 225575 # Transaction distribution
system.iobus.trans_dist::WriteReq 57606 # Transaction distribution
system.iobus.trans_dist::WriteResp 57606 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1644 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1644 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1645 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1645 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 569640 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027856 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027856 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 3276260 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 3276260 # Total data (bytes)
-system.iobus.reqLayer0.occupancy 3918185 # Layer occupancy (ticks)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95278 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95278 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 569652 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027896 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027896 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 3276304 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 3920684 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 422017356 # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy 422027356 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 52370257 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 52381259 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 86877356 # Number of BP lookups
-system.cpu.branchPred.condPredicted 86877356 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 902542 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 80133511 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 78163225 # Number of BTB hits
+system.cpu.branchPred.lookups 86898883 # Number of BP lookups
+system.cpu.branchPred.condPredicted 86898883 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 901790 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 80120336 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 78166165 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.541246 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1555611 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 178528 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 97.560955 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1553548 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 177807 # Number of incorrect RAS predictions.
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.numCycles 449309558 # number of cpu cycles simulated
+system.cpu.numCycles 449490093 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 27651859 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 428959611 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 86877356 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 79718836 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 417653044 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1892712 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 141479 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 49827 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 205407 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 127451 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 417 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 9182196 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 444767 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5009 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 446775840 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.894723 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.051895 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 27736713 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 428990683 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 86898883 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 79719713 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 417726391 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1890728 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 147536 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 50079 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 202600 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 127031 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 405 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 9184683 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 447260 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5357 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 446936119 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.894164 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.051823 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 281257253 62.95% 62.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2318085 0.52% 63.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 72134929 16.15% 79.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1613434 0.36% 79.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2149929 0.48% 80.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2328393 0.52% 80.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1530698 0.34% 81.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1882713 0.42% 81.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 81560406 18.26% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 281459283 62.98% 62.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2262059 0.51% 63.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 72137620 16.14% 79.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1613997 0.36% 79.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2155091 0.48% 80.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2322801 0.52% 80.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1535694 0.34% 81.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1854025 0.41% 81.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 81595549 18.26% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 446775840 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.193357 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.954708 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 23023114 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 264661195 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 150717323 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 7427852 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 946356 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 838299668 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 946356 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 25879231 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 223164657 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 13208529 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 154609969 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 28967098 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 834812666 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 479412 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 12346095 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 191662 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 13684658 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 997151203 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1813191058 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1114665342 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 185 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 963963482 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 33187719 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 468373 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 472487 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 39006494 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 17336272 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 10188880 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1345741 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1123547 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 829275749 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1209290 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 824021244 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 242579 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 23492118 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 36175819 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 154222 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 446775840 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.844373 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.418251 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 446936119 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.193328 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.954394 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 23065529 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 264763767 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 150736142 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 7425317 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 945364 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 838360092 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 945364 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 25914691 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 223241691 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 13213057 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 154633432 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 28987884 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 834905613 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 478581 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 12335118 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 182483 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 13727584 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 997265714 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1813395255 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1114768158 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 110 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 964051126 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 33214586 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 466449 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 470370 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 38986770 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 17343174 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 10196687 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1348761 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1124760 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 829365293 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1208199 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 824078412 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 244412 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 23515910 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 36291432 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 152927 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 446936119 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.843839 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.418170 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 262561849 58.77% 58.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 13882888 3.11% 61.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 10086827 2.26% 64.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6921999 1.55% 65.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 74315249 16.63% 82.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 4452451 1.00% 83.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 72780033 16.29% 99.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1201096 0.27% 99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 573448 0.13% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 262716607 58.78% 58.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13881580 3.11% 61.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 10086185 2.26% 64.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 6914821 1.55% 65.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 74322504 16.63% 82.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 4455510 1.00% 83.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 72776226 16.28% 99.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1206411 0.27% 99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 576275 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 446775840 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 446936119 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 1974933 71.79% 71.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 151 0.01% 71.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 606 0.02% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 614459 22.33% 94.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 161026 5.85% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 1975200 71.80% 71.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 252 0.01% 71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 1109 0.04% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 614218 22.33% 94.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 160061 5.82% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 292875 0.04% 0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 795624977 96.55% 96.59% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 150449 0.02% 96.61% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 125321 0.02% 96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 293084 0.04% 0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 795671914 96.55% 96.59% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 150614 0.02% 96.61% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 125303 0.02% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 18429310 2.24% 98.86% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 9398312 1.14% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 18435146 2.24% 98.86% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 9402351 1.14% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 824021244 # Type of FU issued
-system.cpu.iq.rate 1.833972 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2751175 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.003339 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 2097811864 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 853989635 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 819447653 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 217 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 292 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 60 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 826479445 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 99 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1882501 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 824078412 # Type of FU issued
+system.cpu.iq.rate 1.833363 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2750840 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.003338 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 2098087999 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 854102050 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 819507550 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 195 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 194 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 56 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 826536078 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1879985 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 3343168 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 14800 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 14469 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1764190 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 3343174 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 14903 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 14336 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1767440 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2224524 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 72794 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2224972 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 73807 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 946356 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 205489198 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 9385897 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 830485039 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 188872 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 17336272 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 10188880 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 713065 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 415930 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 8070911 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 14469 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 518528 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 536731 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1055259 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 822394413 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 18030482 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1492613 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 945364 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 205481336 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 9444308 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 830573492 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 185181 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 17343194 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 10196687 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 711600 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 416792 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 8129202 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 14336 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 515306 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 539272 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1054578 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 822459197 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 18034619 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1483642 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 27200783 # number of memory reference insts executed
-system.cpu.iew.exec_branches 83281301 # Number of branches executed
-system.cpu.iew.exec_stores 9170301 # Number of stores executed
-system.cpu.iew.exec_rate 1.830351 # Inst execution rate
-system.cpu.iew.wb_sent 821885746 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 819447713 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 640810294 # num instructions producing a value
-system.cpu.iew.wb_consumers 1050192124 # num instructions consuming a value
+system.cpu.iew.exec_refs 27209233 # number of memory reference insts executed
+system.cpu.iew.exec_branches 83289157 # Number of branches executed
+system.cpu.iew.exec_stores 9174614 # Number of stores executed
+system.cpu.iew.exec_rate 1.829760 # Inst execution rate
+system.cpu.iew.wb_sent 821946704 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 819507606 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 640910074 # num instructions producing a value
+system.cpu.iew.wb_consumers 1050315789 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.823793 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.610184 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.823194 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.610207 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 24342460 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1055068 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 914367 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 443118746 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.819035 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.675250 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 24363502 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1055272 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 913280 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 443273616 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.818549 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.675153 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 272366005 61.47% 61.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11194221 2.53% 63.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3590232 0.81% 64.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 74521712 16.82% 81.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2434404 0.55% 82.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1603700 0.36% 82.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 952599 0.21% 82.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 71009883 16.03% 98.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5445990 1.23% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 272516770 61.48% 61.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11195258 2.53% 64.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3583043 0.81% 64.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 74523250 16.81% 81.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2432181 0.55% 82.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1605992 0.36% 82.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 951269 0.21% 82.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 71009301 16.02% 98.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5456552 1.23% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 443118746 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 407773893 # Number of instructions committed
-system.cpu.commit.committedOps 806048632 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 443273616 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 407812863 # Number of instructions committed
+system.cpu.commit.committedOps 806114915 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 22417793 # Number of memory references committed
-system.cpu.commit.loads 13993103 # Number of loads committed
-system.cpu.commit.membars 474875 # Number of memory barriers committed
-system.cpu.commit.branches 82158924 # Number of branches committed
+system.cpu.commit.refs 22429266 # Number of memory references committed
+system.cpu.commit.loads 14000019 # Number of loads committed
+system.cpu.commit.membars 474889 # Number of memory barriers committed
+system.cpu.commit.branches 82168190 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 734892496 # Number of committed integer instructions.
-system.cpu.commit.function_calls 1155452 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 174150 0.02% 0.02% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 783190673 97.16% 97.19% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 144749 0.02% 97.20% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 121267 0.02% 97.22% # Class of committed instruction
+system.cpu.commit.int_insts 734958550 # Number of committed integer instructions.
+system.cpu.commit.function_calls 1155635 # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass 174258 0.02% 0.02% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 783245185 97.16% 97.18% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 144842 0.02% 97.20% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv 121364 0.02% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 13993103 1.74% 98.95% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 8424690 1.05% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 14000019 1.74% 98.95% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 8429247 1.05% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 806048632 # Class of committed instruction
-system.cpu.commit.bw_lim_events 5445990 # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total 806114915 # Class of committed instruction
+system.cpu.commit.bw_lim_events 5456552 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1267985613 # The number of ROB reads
-system.cpu.rob.rob_writes 1664458820 # The number of ROB writes
-system.cpu.timesIdled 297027 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 2533718 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 9810435335 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 407773893 # Number of Instructions Simulated
-system.cpu.committedOps 806048632 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.101860 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.101860 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.907557 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.907557 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1092201088 # number of integer regfile reads
-system.cpu.int_regfile_writes 655889202 # number of integer regfile writes
-system.cpu.fp_regfile_reads 60 # number of floating regfile reads
-system.cpu.cc_regfile_reads 416095530 # number of cc regfile reads
-system.cpu.cc_regfile_writes 321948927 # number of cc regfile writes
-system.cpu.misc_regfile_reads 265553416 # number of misc regfile reads
-system.cpu.misc_regfile_writes 402606 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 55008962 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 3071462 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 3070914 # Transaction distribution
+system.cpu.rob.rob_reads 1268217156 # The number of ROB reads
+system.cpu.rob.rob_writes 1664635865 # The number of ROB writes
+system.cpu.timesIdled 297982 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 2553974 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 9810264132 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 407812863 # Number of Instructions Simulated
+system.cpu.committedOps 806114915 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 1.102197 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.102197 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.907279 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.907279 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1092267062 # number of integer regfile reads
+system.cpu.int_regfile_writes 655932610 # number of integer regfile writes
+system.cpu.fp_regfile_reads 56 # number of floating regfile reads
+system.cpu.cc_regfile_reads 416128291 # number of cc regfile reads
+system.cpu.cc_regfile_writes 321990784 # number of cc regfile writes
+system.cpu.misc_regfile_reads 265578345 # number of misc regfile reads
+system.cpu.misc_regfile_writes 402863 # number of misc regfile writes
+system.cpu.toL2Bus.trans_dist::ReadReq 3083726 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 3083187 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 13776 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 13776 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 1585837 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46724 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2242 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2242 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 287030 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 287030 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError 11 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1996026 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6130754 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30653 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 164256 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 8321689 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63869504 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207903453 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 978368 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5729920 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 278481245 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 278457117 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 3731904 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 4072507880 # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::Writeback 1587489 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46722 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2231 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2231 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 287826 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 287826 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2007150 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6137120 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 34489 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 168921 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 8347680 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64225408 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208172445 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1082112 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5828032 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 279307997 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 61506 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 4398693 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3.010831 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.103506 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 4351052 98.92% 98.92% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 47641 1.08% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 4398693 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 4081523356 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 565500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy 582000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1501244795 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1509600495 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3142652109 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 3145861612 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 23061226 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 26384476 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 112150627 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 116845140 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu.icache.tags.replacements 997506 # number of replacements
-system.cpu.icache.tags.tagsinuse 509.982226 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 8120756 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 998018 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 8.136883 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 147598371250 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 509.982226 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.996059 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.996059 # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements 1003070 # number of replacements
+system.cpu.icache.tags.tagsinuse 510.154171 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 8117984 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 1003582 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 8.089009 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 147599073250 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 510.154171 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.996395 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.996395 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 140 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 201 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 10180257 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 10180257 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 8120756 # number of ReadReq hits
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+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11088.105910 # average overall miss latency
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system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.itb_walker_cache.writebacks::total 2963 # number of writebacks
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-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15366 # number of ReadReq MSHR misses
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-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 143113289 # number of demand (read+write) MSHR miss cycles
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-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 143113289 # number of overall MSHR miss cycles
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system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id
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system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu.dtb_walker_cache.demand_accesses::total 190660 # number of demand (read+write) accesses
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-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12199.384565 # average overall miss latency
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-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12199.384565 # average overall miss latency
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+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12121.666547 # average overall miss latency
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+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12121.666547 # average overall miss latency
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system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021259 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823995 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823995 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464509 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464509 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000921 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000440 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016321 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102037 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.067678 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000921 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000440 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016321 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102037 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.067678 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63424.410795 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66919.297156 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65831.101285 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10025.380495 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10025.380495 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57315.934896 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57315.934896 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63424.410795 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59347.019988 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59710.606556 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63424.410795 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59347.019988 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59710.606556 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 5.304497 # Number of seconds simulated
-sim_ticks 5304496799500 # Number of ticks simulated
-final_tick 5304496799500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.300439 # Number of seconds simulated
+sim_ticks 5300438650000 # Number of ticks simulated
+final_tick 5300438650000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 120327 # Simulator instruction rate (inst/s)
-host_op_rate 230715 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5973118168 # Simulator tick rate (ticks/s)
-host_mem_usage 829584 # Number of bytes of host memory used
-host_seconds 888.06 # Real time elapsed on the host
-sim_insts 106858198 # Number of instructions simulated
-sim_ops 204889266 # Number of ops (including micro ops) simulated
+host_inst_rate 184616 # Simulator instruction rate (inst/s)
+host_op_rate 353991 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 9163289290 # Simulator tick rate (ticks/s)
+host_mem_usage 842832 # Number of bytes of host memory used
+host_seconds 578.44 # Real time elapsed on the host
+sim_insts 106789618 # Number of instructions simulated
+sim_ops 204763566 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::pc.south_bridge.ide 35160 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 168624 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 87432 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 563238768 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 42054251 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 54624 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 20152 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 449830560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 51714243 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1107203814 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 563238768 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 449830560 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1013069328 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::pc.south_bridge.ide 35184 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 121960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 61480 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 541981136 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 38703389 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 101016 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 45856 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 470377672 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 54942760 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1106370453 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 541981136 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 470377672 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1012358808 # Number of instructions bytes read from this memory
system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 34106065 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 33949188 # Number of bytes written to this memory
-system.physmem.bytes_written::total 71046373 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 811 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 21078 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 10929 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 70404846 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 7007948 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 6828 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 2519 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 56228820 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 8722584 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 142406363 # Number of read requests responded to by this memory
+system.physmem.bytes_written::cpu0.data 31533942 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 36447976 # Number of bytes written to this memory
+system.physmem.bytes_written::total 70973038 # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide 814 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 15245 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 7685 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 67747642 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 6493671 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 12627 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 5732 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 58797209 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 9219399 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 142300024 # Number of read requests responded to by this memory
system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 5095102 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 4745797 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 9887637 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 6628 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 31789 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 16483 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 106181376 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 7928038 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 10298 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 3799 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 84801740 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 9749133 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 208729283 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 106181376 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 84801740 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 190983116 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide 563881 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::cpu0.data 4739534 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 5091384 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 9877656 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 6638 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 23009 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 11599 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 102252129 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 7301922 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 19058 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 8651 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 88743159 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 10365701 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 208731867 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 102252129 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 88743159 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 190995288 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide 564313 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 6429651 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 6400077 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 13393612 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 570509 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 31789 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 16486 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 106181376 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 14357689 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 10298 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 3799 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 84801740 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 16149210 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 222122895 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 5949308 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 6876407 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 13390031 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 570950 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 23009 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 11602 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 102252129 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 13251230 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 19058 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 8651 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 88743159 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 17242108 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 222121898 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 0 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 0 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap nan # Average gap between requests
system.physmem.pageHitRate nan # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 5127363440000 # Time in different power states
-system.physmem.memoryStateTime::REF 177128640000 # Time in different power states
+system.physmem.memoryStateTime::IDLE 5123442263750 # Time in different power states
+system.physmem.memoryStateTime::REF 176993180000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 0 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.ruby.clk_domain.clock 500 # Clock period in ticks
system.ruby.delayHist::bucket_size 4 # delay histogram for all message
system.ruby.delayHist::max_bucket 39 # delay histogram for all message
-system.ruby.delayHist::samples 10864368 # delay histogram for all message
-system.ruby.delayHist::mean 0.442902 # delay histogram for all message
-system.ruby.delayHist::stdev 1.830573 # delay histogram for all message
-system.ruby.delayHist | 10263231 94.47% 94.47% | 1369 0.01% 94.48% | 599393 5.52% 100.00% | 125 0.00% 100.00% | 205 0.00% 100.00% | 8 0.00% 100.00% | 37 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
-system.ruby.delayHist::total 10864368 # delay histogram for all message
+system.ruby.delayHist::samples 10855969 # delay histogram for all message
+system.ruby.delayHist::mean 0.443071 # delay histogram for all message
+system.ruby.delayHist::stdev 1.830936 # delay histogram for all message
+system.ruby.delayHist | 10255101 94.47% 94.47% | 1445 0.01% 94.48% | 599037 5.52% 100.00% | 126 0.00% 100.00% | 212 0.00% 100.00% | 12 0.00% 100.00% | 36 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
+system.ruby.delayHist::total 10855969 # delay histogram for all message
system.ruby.outstanding_req_hist::bucket_size 1
system.ruby.outstanding_req_hist::max_bucket 9
-system.ruby.outstanding_req_hist::samples 152246454
+system.ruby.outstanding_req_hist::samples 152130131
system.ruby.outstanding_req_hist::mean 1.000112
system.ruby.outstanding_req_hist::gmean 1.000078
-system.ruby.outstanding_req_hist::stdev 0.010602
-system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152229339 99.99% 99.99% | 17115 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist::total 152246454
+system.ruby.outstanding_req_hist::stdev 0.010599
+system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152113038 99.99% 99.99% | 17093 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist::total 152130131
system.ruby.latency_hist::bucket_size 32
system.ruby.latency_hist::max_bucket 319
-system.ruby.latency_hist::samples 152246453
-system.ruby.latency_hist::mean 3.380088
-system.ruby.latency_hist::gmean 3.106160
-system.ruby.latency_hist::stdev 3.773917
-system.ruby.latency_hist | 152072522 99.89% 99.89% | 120 0.00% 99.89% | 79139 0.05% 99.94% | 93729 0.06% 100.00% | 941 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist::total 152246453
+system.ruby.latency_hist::samples 152130130
+system.ruby.latency_hist::mean 3.380455
+system.ruby.latency_hist::gmean 3.106132
+system.ruby.latency_hist::stdev 3.781513
+system.ruby.latency_hist | 151955103 99.88% 99.88% | 126 0.00% 99.89% | 79786 0.05% 99.94% | 94134 0.06% 100.00% | 979 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist::total 152130130
system.ruby.hit_latency_hist::bucket_size 1
system.ruby.hit_latency_hist::max_bucket 9
-system.ruby.hit_latency_hist::samples 149587693
+system.ruby.hit_latency_hist::samples 149475024
system.ruby.hit_latency_hist::mean 3
system.ruby.hit_latency_hist::gmean 3.000000
-system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 149587693 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist::total 149587693
+system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 149475024 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.hit_latency_hist::total 149475024
system.ruby.miss_latency_hist::bucket_size 32
system.ruby.miss_latency_hist::max_bucket 319
-system.ruby.miss_latency_hist::samples 2658760
-system.ruby.miss_latency_hist::mean 24.764674
-system.ruby.miss_latency_hist::gmean 21.974787
-system.ruby.miss_latency_hist::stdev 18.711640
-system.ruby.miss_latency_hist | 2484829 93.46% 93.46% | 120 0.00% 93.46% | 79139 2.98% 96.44% | 93729 3.53% 99.96% | 941 0.04% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist::total 2658760
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 11563536 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 571523 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 12135059 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 70045998 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 358848 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 70404846 # Number of cache demand accesses
+system.ruby.miss_latency_hist::samples 2655106
+system.ruby.miss_latency_hist::mean 24.799008
+system.ruby.miss_latency_hist::gmean 21.990340
+system.ruby.miss_latency_hist::stdev 18.773320
+system.ruby.miss_latency_hist | 2480079 93.41% 93.41% | 126 0.00% 93.41% | 79786 3.01% 96.42% | 94134 3.55% 99.96% | 979 0.04% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist::total 2655106
+system.ruby.l1_cntrl0.L1Dcache.demand_hits 10730190 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses 525947 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11256137 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits 67423344 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses 324298 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses 67747642 # Number of cache demand accesses
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl0.fully_busy_cycles 13 # cycles for which number of transistions == max transitions
-system.ruby.network.routers0.percent_links_utilized 0.032337
-system.ruby.network.routers0.msg_count.Control::0 930371
-system.ruby.network.routers0.msg_count.Request_Control::2 42522
-system.ruby.network.routers0.msg_count.Response_Data::1 958517
-system.ruby.network.routers0.msg_count.Response_Control::1 545617
-system.ruby.network.routers0.msg_count.Response_Control::2 541977
-system.ruby.network.routers0.msg_count.Writeback_Data::0 316333
-system.ruby.network.routers0.msg_count.Writeback_Data::1 73
-system.ruby.network.routers0.msg_count.Writeback_Control::0 187850
-system.ruby.network.routers0.msg_bytes.Control::0 7442968
-system.ruby.network.routers0.msg_bytes.Request_Control::2 340176
-system.ruby.network.routers0.msg_bytes.Response_Data::1 69013224
-system.ruby.network.routers0.msg_bytes.Response_Control::1 4364936
-system.ruby.network.routers0.msg_bytes.Response_Control::2 4335816
-system.ruby.network.routers0.msg_bytes.Writeback_Data::0 22775976
-system.ruby.network.routers0.msg_bytes.Writeback_Data::1 5256
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0 1502800
-system.ruby.l1_cntrl1.L1Dcache.demand_hits 12207979 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses 1269749 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses 13477728 # Number of cache demand accesses
-system.ruby.l1_cntrl1.L1Icache.demand_hits 55770180 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Icache.demand_misses 458640 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Icache.demand_accesses 56228820 # Number of cache demand accesses
+system.ruby.l1_cntrl0.fully_busy_cycles 12 # cycles for which number of transistions == max transitions
+system.ruby.network.routers0.percent_links_utilized 0.029767
+system.ruby.network.routers0.msg_count.Control::0 850245
+system.ruby.network.routers0.msg_count.Request_Control::2 42194
+system.ruby.network.routers0.msg_count.Response_Data::1 878350
+system.ruby.network.routers0.msg_count.Response_Control::1 503571
+system.ruby.network.routers0.msg_count.Response_Control::2 500402
+system.ruby.network.routers0.msg_count.Writeback_Data::0 294663
+system.ruby.network.routers0.msg_count.Writeback_Data::1 77
+system.ruby.network.routers0.msg_count.Writeback_Control::0 168221
+system.ruby.network.routers0.msg_bytes.Control::0 6801960
+system.ruby.network.routers0.msg_bytes.Request_Control::2 337552
+system.ruby.network.routers0.msg_bytes.Response_Data::1 63241200
+system.ruby.network.routers0.msg_bytes.Response_Control::1 4028568
+system.ruby.network.routers0.msg_bytes.Response_Control::2 4003216
+system.ruby.network.routers0.msg_bytes.Writeback_Data::0 21215736
+system.ruby.network.routers0.msg_bytes.Writeback_Data::1 5544
+system.ruby.network.routers0.msg_bytes.Writeback_Control::0 1345768
+system.ruby.l1_cntrl1.L1Dcache.demand_hits 13015788 # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Dcache.demand_misses 1313354 # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14329142 # Number of cache demand accesses
+system.ruby.l1_cntrl1.L1Icache.demand_hits 58305702 # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Icache.demand_misses 491507 # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Icache.demand_accesses 58797209 # Number of cache demand accesses
system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed
system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made
system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl1.fully_busy_cycles 12 # cycles for which number of transistions == max transitions
-system.ruby.network.routers1.percent_links_utilized 0.054687
-system.ruby.network.routers1.msg_count.Control::0 1728389
-system.ruby.network.routers1.msg_count.Request_Control::2 38822
-system.ruby.network.routers1.msg_count.Response_Data::1 1752004
-system.ruby.network.routers1.msg_count.Response_Control::1 1215403
-system.ruby.network.routers1.msg_count.Response_Control::2 1215696
-system.ruby.network.routers1.msg_count.Writeback_Data::0 257519
-system.ruby.network.routers1.msg_count.Writeback_Data::1 203
-system.ruby.network.routers1.msg_count.Writeback_Control::0 921082
-system.ruby.network.routers1.msg_bytes.Control::0 13827112
-system.ruby.network.routers1.msg_bytes.Request_Control::2 310576
-system.ruby.network.routers1.msg_bytes.Response_Data::1 126144288
-system.ruby.network.routers1.msg_bytes.Response_Control::1 9723224
-system.ruby.network.routers1.msg_bytes.Response_Control::2 9725568
-system.ruby.network.routers1.msg_bytes.Writeback_Data::0 18541368
-system.ruby.network.routers1.msg_bytes.Writeback_Data::1 14616
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0 7368656
-system.ruby.l2_cntrl0.L2cache.demand_hits 2436175 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 222585 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 2658760 # Number of cache demand accesses
+system.ruby.l1_cntrl1.fully_busy_cycles 13 # cycles for which number of transistions == max transitions
+system.ruby.network.routers1.percent_links_utilized 0.057220
+system.ruby.network.routers1.msg_count.Control::0 1804861
+system.ruby.network.routers1.msg_count.Request_Control::2 38457
+system.ruby.network.routers1.msg_count.Response_Data::1 1828237
+system.ruby.network.routers1.msg_count.Response_Control::1 1255902
+system.ruby.network.routers1.msg_count.Response_Control::2 1256112
+system.ruby.network.routers1.msg_count.Writeback_Data::0 279082
+system.ruby.network.routers1.msg_count.Writeback_Data::1 227
+system.ruby.network.routers1.msg_count.Writeback_Control::0 940216
+system.ruby.network.routers1.msg_bytes.Control::0 14438888
+system.ruby.network.routers1.msg_bytes.Request_Control::2 307656
+system.ruby.network.routers1.msg_bytes.Response_Data::1 131633064
+system.ruby.network.routers1.msg_bytes.Response_Control::1 10047216
+system.ruby.network.routers1.msg_bytes.Response_Control::2 10048896
+system.ruby.network.routers1.msg_bytes.Writeback_Data::0 20093904
+system.ruby.network.routers1.msg_bytes.Writeback_Data::1 16344
+system.ruby.network.routers1.msg_bytes.Writeback_Control::0 7521728
+system.ruby.l2_cntrl0.L2cache.demand_hits 2431773 # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses 223333 # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses 2655106 # Number of cache demand accesses
system.ruby.l2_cntrl0.fully_busy_cycles 2 # cycles for which number of transistions == max transitions
-system.ruby.network.routers2.percent_links_utilized 0.091278
-system.ruby.network.routers2.msg_count.Control::0 2832571
-system.ruby.network.routers2.msg_count.Request_Control::2 79701
-system.ruby.network.routers2.msg_count.Response_Data::1 2883607
-system.ruby.network.routers2.msg_count.Response_Control::1 1836255
-system.ruby.network.routers2.msg_count.Response_Control::2 1757673
-system.ruby.network.routers2.msg_count.Writeback_Data::0 573852
-system.ruby.network.routers2.msg_count.Writeback_Data::1 276
-system.ruby.network.routers2.msg_count.Writeback_Control::0 1108932
-system.ruby.network.routers2.msg_bytes.Control::0 22660568
-system.ruby.network.routers2.msg_bytes.Request_Control::2 637608
-system.ruby.network.routers2.msg_bytes.Response_Data::1 207619704
-system.ruby.network.routers2.msg_bytes.Response_Control::1 14690040
-system.ruby.network.routers2.msg_bytes.Response_Control::2 14061384
-system.ruby.network.routers2.msg_bytes.Writeback_Data::0 41317344
-system.ruby.network.routers2.msg_bytes.Writeback_Data::1 19872
-system.ruby.network.routers2.msg_bytes.Writeback_Control::0 8871456
+system.ruby.network.routers2.percent_links_utilized 0.091305
+system.ruby.network.routers2.msg_count.Control::0 2830007
+system.ruby.network.routers2.msg_count.Request_Control::2 78985
+system.ruby.network.routers2.msg_count.Response_Data::1 2882064
+system.ruby.network.routers2.msg_count.Response_Control::1 1837383
+system.ruby.network.routers2.msg_count.Response_Control::2 1756514
+system.ruby.network.routers2.msg_count.Writeback_Data::0 573745
+system.ruby.network.routers2.msg_count.Writeback_Data::1 304
+system.ruby.network.routers2.msg_count.Writeback_Control::0 1108437
+system.ruby.network.routers2.msg_bytes.Control::0 22640056
+system.ruby.network.routers2.msg_bytes.Request_Control::2 631880
+system.ruby.network.routers2.msg_bytes.Response_Data::1 207508608
+system.ruby.network.routers2.msg_bytes.Response_Control::1 14699064
+system.ruby.network.routers2.msg_bytes.Response_Control::2 14052112
+system.ruby.network.routers2.msg_bytes.Writeback_Data::0 41309640
+system.ruby.network.routers2.msg_bytes.Writeback_Data::1 21888
+system.ruby.network.routers2.msg_bytes.Writeback_Control::0 8867496
system.ruby.memctrl_clk_domain.clock 1500 # Clock period in ticks
-system.ruby.dir_cntrl0.memBuffer.memReq 316333 # Total number of memory requests
-system.ruby.dir_cntrl0.memBuffer.memRead 174271 # Number of memory reads
-system.ruby.dir_cntrl0.memBuffer.memWrite 142062 # Number of memory writes
-system.ruby.dir_cntrl0.memBuffer.memRefresh 709010 # Number of memory refreshes
-system.ruby.dir_cntrl0.memBuffer.memWaitCycles 938353 # Delay stalled at the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.memInputQ 49 # Delay in the input queue
-system.ruby.dir_cntrl0.memBuffer.memBankQ 6542 # Delay behind the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.totalStalls 944944 # Total number of stall cycles
-system.ruby.dir_cntrl0.memBuffer.stallsPerReq 2.987181 # Expected number of stall cycles per request
-system.ruby.dir_cntrl0.memBuffer.memBankBusy 926785 # memory stalls due to busy bank
-system.ruby.dir_cntrl0.memBuffer.memBusBusy 8256 # memory stalls due to busy bus
-system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 98 # memory stalls due to read write turnaround
-system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 9 # memory stalls due to read read turnaround
-system.ruby.dir_cntrl0.memBuffer.memArbWait 3205 # memory stalls due to arbitration
-system.ruby.dir_cntrl0.memBuffer.memBankCount | 10282 3.25% 3.25% | 9688 3.06% 6.31% | 9618 3.04% 9.35% | 9663 3.05% 12.41% | 10044 3.18% 15.58% | 9949 3.15% 18.73% | 9819 3.10% 21.83% | 9702 3.07% 24.90% | 9851 3.11% 28.01% | 9707 3.07% 31.08% | 9714 3.07% 34.15% | 9748 3.08% 37.23% | 9782 3.09% 40.33% | 9588 3.03% 43.36% | 9583 3.03% 46.39% | 8652 2.74% 49.12% | 10210 3.23% 52.35% | 9818 3.10% 55.45% | 9760 3.09% 58.54% | 9707 3.07% 61.61% | 10012 3.17% 64.77% | 9864 3.12% 67.89% | 9722 3.07% 70.96% | 9786 3.09% 74.06% | 10077 3.19% 77.24% | 9920 3.14% 80.38% | 10090 3.19% 83.57% | 10790 3.41% 86.98% | 10587 3.35% 90.33% | 10505 3.32% 93.65% | 10419 3.29% 96.94% | 9676 3.06% 100.00% # Number of accesses per bank
-system.ruby.dir_cntrl0.memBuffer.memBankCount::total 316333 # Number of accesses per bank
-system.ruby.network.routers3.percent_links_utilized 0.006678
-system.ruby.network.routers3.msg_count.Control::0 173811
-system.ruby.network.routers3.msg_count.Response_Data::1 271445
-system.ruby.network.routers3.msg_count.Response_Control::1 122871
-system.ruby.network.routers3.msg_count.Writeback_Control::0 47547
+system.ruby.dir_cntrl0.memBuffer.memReq 317875 # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead 175364 # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite 142511 # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh 714751 # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles 942834 # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.memInputQ 46 # Delay in the input queue
+system.ruby.dir_cntrl0.memBuffer.memBankQ 6611 # Delay behind the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls 949491 # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq 2.986995 # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy 931351 # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy 8237 # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 87 # memory stalls due to read write turnaround
+system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 8 # memory stalls due to read read turnaround
+system.ruby.dir_cntrl0.memBuffer.memArbWait 3151 # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memBankCount | 10282 3.23% 3.23% | 9701 3.05% 6.29% | 9679 3.04% 9.33% | 9712 3.06% 12.39% | 10010 3.15% 15.54% | 9927 3.12% 18.66% | 9854 3.10% 21.76% | 9702 3.05% 24.81% | 9904 3.12% 27.93% | 9752 3.07% 30.99% | 9805 3.08% 34.08% | 9914 3.12% 37.20% | 9948 3.13% 40.33% | 9724 3.06% 43.39% | 9647 3.03% 46.42% | 8750 2.75% 49.17% | 10266 3.23% 52.40% | 9887 3.11% 55.51% | 9844 3.10% 58.61% | 9758 3.07% 61.68% | 10022 3.15% 64.83% | 9879 3.11% 67.94% | 9766 3.07% 71.01% | 9852 3.10% 74.11% | 10073 3.17% 77.28% | 9931 3.12% 80.41% | 10175 3.20% 83.61% | 10769 3.39% 86.99% | 10605 3.34% 90.33% | 10522 3.31% 93.64% | 10506 3.31% 96.95% | 9709 3.05% 100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total 317875 # Number of accesses per bank
+system.ruby.network.routers3.percent_links_utilized 0.006727
+system.ruby.network.routers3.msg_count.Control::0 174901
+system.ruby.network.routers3.msg_count.Response_Data::1 273155
+system.ruby.network.routers3.msg_count.Response_Control::1 125034
+system.ruby.network.routers3.msg_count.Writeback_Control::0 47550
system.ruby.network.routers3.msg_count.Writeback_Control::1 46736
-system.ruby.network.routers3.msg_bytes.Control::0 1390488
-system.ruby.network.routers3.msg_bytes.Response_Data::1 19544040
-system.ruby.network.routers3.msg_bytes.Response_Control::1 982968
-system.ruby.network.routers3.msg_bytes.Writeback_Control::0 380376
+system.ruby.network.routers3.msg_bytes.Control::0 1399208
+system.ruby.network.routers3.msg_bytes.Response_Data::1 19667160
+system.ruby.network.routers3.msg_bytes.Response_Control::1 1000272
+system.ruby.network.routers3.msg_bytes.Writeback_Control::0 380400
system.ruby.network.routers3.msg_bytes.Writeback_Control::1 373888
-system.ruby.network.routers4.percent_links_utilized 0.000239
-system.ruby.network.routers4.msg_count.Response_Data::1 811
-system.ruby.network.routers4.msg_count.Writeback_Control::0 47547
+system.ruby.network.routers4.percent_links_utilized 0.000240
+system.ruby.network.routers4.msg_count.Response_Data::1 814
+system.ruby.network.routers4.msg_count.Writeback_Control::0 47550
system.ruby.network.routers4.msg_count.Writeback_Control::1 46736
-system.ruby.network.routers4.msg_bytes.Response_Data::1 58392
-system.ruby.network.routers4.msg_bytes.Writeback_Control::0 380376
+system.ruby.network.routers4.msg_bytes.Response_Data::1 58608
+system.ruby.network.routers4.msg_bytes.Writeback_Control::0 380400
system.ruby.network.routers4.msg_bytes.Writeback_Control::1 373888
-system.ruby.network.routers5.percent_links_utilized 0.037045
-system.ruby.network.routers5.msg_count.Control::0 2832571
-system.ruby.network.routers5.msg_count.Request_Control::2 81344
-system.ruby.network.routers5.msg_count.Response_Data::1 2933192
-system.ruby.network.routers5.msg_count.Response_Control::1 1860073
-system.ruby.network.routers5.msg_count.Response_Control::2 1757673
-system.ruby.network.routers5.msg_count.Writeback_Data::0 573852
-system.ruby.network.routers5.msg_count.Writeback_Data::1 276
-system.ruby.network.routers5.msg_count.Writeback_Control::0 1156479
+system.ruby.network.routers5.percent_links_utilized 0.037053
+system.ruby.network.routers5.msg_count.Control::0 2830007
+system.ruby.network.routers5.msg_count.Request_Control::2 80651
+system.ruby.network.routers5.msg_count.Response_Data::1 2931310
+system.ruby.network.routers5.msg_count.Response_Control::1 1860945
+system.ruby.network.routers5.msg_count.Response_Control::2 1756514
+system.ruby.network.routers5.msg_count.Writeback_Data::0 573745
+system.ruby.network.routers5.msg_count.Writeback_Data::1 304
+system.ruby.network.routers5.msg_count.Writeback_Control::0 1155987
system.ruby.network.routers5.msg_count.Writeback_Control::1 46736
-system.ruby.network.routers5.msg_bytes.Control::0 22660568
-system.ruby.network.routers5.msg_bytes.Request_Control::2 650752
-system.ruby.network.routers5.msg_bytes.Response_Data::1 211189824
-system.ruby.network.routers5.msg_bytes.Response_Control::1 14880584
-system.ruby.network.routers5.msg_bytes.Response_Control::2 14061384
-system.ruby.network.routers5.msg_bytes.Writeback_Data::0 41317344
-system.ruby.network.routers5.msg_bytes.Writeback_Data::1 19872
-system.ruby.network.routers5.msg_bytes.Writeback_Control::0 9251832
+system.ruby.network.routers5.msg_bytes.Control::0 22640056
+system.ruby.network.routers5.msg_bytes.Request_Control::2 645208
+system.ruby.network.routers5.msg_bytes.Response_Data::1 211054320
+system.ruby.network.routers5.msg_bytes.Response_Control::1 14887560
+system.ruby.network.routers5.msg_bytes.Response_Control::2 14052112
+system.ruby.network.routers5.msg_bytes.Writeback_Data::0 41309640
+system.ruby.network.routers5.msg_bytes.Writeback_Data::1 21888
+system.ruby.network.routers5.msg_bytes.Writeback_Control::0 9247896
system.ruby.network.routers5.msg_bytes.Writeback_Control::1 373888
-system.ruby.network.msg_count.Control 8497713
-system.ruby.network.msg_count.Request_Control 242389
-system.ruby.network.msg_count.Response_Data 8799576
-system.ruby.network.msg_count.Response_Control 10853238
-system.ruby.network.msg_count.Writeback_Data 1722384
-system.ruby.network.msg_count.Writeback_Control 3609645
-system.ruby.network.msg_byte.Control 67981704
-system.ruby.network.msg_byte.Request_Control 1939112
-system.ruby.network.msg_byte.Response_Data 633569472
-system.ruby.network.msg_byte.Response_Control 86825904
-system.ruby.network.msg_byte.Writeback_Data 124011648
-system.ruby.network.msg_byte.Writeback_Control 28877160
+system.ruby.network.msg_count.Control 8490021
+system.ruby.network.msg_count.Request_Control 240287
+system.ruby.network.msg_count.Response_Data 8793930
+system.ruby.network.msg_count.Response_Control 10852377
+system.ruby.network.msg_count.Writeback_Data 1722147
+system.ruby.network.msg_count.Writeback_Control 3608169
+system.ruby.network.msg_byte.Control 67920168
+system.ruby.network.msg_byte.Request_Control 1922296
+system.ruby.network.msg_byte.Response_Data 633162960
+system.ruby.network.msg_byte.Response_Control 86819016
+system.ruby.network.msg_byte.Writeback_Data 123994584
+system.ruby.network.msg_byte.Writeback_Control 28865352
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.iobus.throughput 383266 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 858445 # Transaction distribution
-system.iobus.trans_dist::ReadResp 858445 # Transaction distribution
-system.iobus.trans_dist::WriteReq 37732 # Transaction distribution
-system.iobus.trans_dist::WriteResp 37732 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1926 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1926 # Transaction distribution
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1702 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1646 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3348 # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq 858433 # Transaction distribution
+system.iobus.trans_dist::ReadResp 858433 # Transaction distribution
+system.iobus.trans_dist::WriteReq 37701 # Transaction distribution
+system.iobus.trans_dist::WriteResp 37701 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1920 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1920 # Transaction distribution
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1700 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1644 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3344 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6438 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5246 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 956 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 934582 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 980 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 984 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 90 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14492 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 743214 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14276 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 743206 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 246 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1703394 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1701984 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4650 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5796 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 408 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 33042 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 354 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 350 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 33130 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12176 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12392 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 260 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 5252 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 89464 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 1796206 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3404 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3292 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6696 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3666 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 478 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 467291 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1960 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 45 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7246 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1486422 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 488 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1972089 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3020 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 204 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 16521 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 708 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 16565 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6088 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 520 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 10501 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 54249 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 2033034 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 2033034 # Total data (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 250 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 5220 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 90780 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 1796108 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3400 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3288 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6688 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 2968 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 478 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 467291 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1968 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 45 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7138 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1486406 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 492 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1971279 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3692 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 204 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 16521 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 700 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 16565 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6196 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 10437 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 54937 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2032904 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 44000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 6500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 10235000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 10297000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 144000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 1064500 # Layer occupancy (ticks)
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system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
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+system.iobus.reqLayer6.occupancy 56500 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 30321000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 467293000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 1237000 # Layer occupancy (ticks)
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system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 41501500 # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy 41493500 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
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+system.iobus.reqLayer12.occupancy 23740500 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks)
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system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
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+system.iobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 7824868 # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy 8238216 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 1328500 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2417900 # Layer occupancy (ticks)
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system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 1790325500 # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy 1790015500 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer4.occupancy 80269500 # Layer occupancy (ticks)
+system.iobus.respLayer4.occupancy 80920500 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu0.numCycles 10608993599 # number of cpu cycles simulated
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 60256011 # Number of instructions committed
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+system.cpu0.committedOps 111982705 # Number of ops (including micro ops) committed
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system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu0.num_func_calls 1055482 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 10261722 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 108487069 # number of integer instructions
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system.cpu0.num_fp_insts 0 # number of float instructions
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-system.cpu0.num_int_register_writes 91998767 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 197725542 # number of times the integer registers were read
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system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
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-system.cpu0.num_cc_register_reads 62453256 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 44908337 # number of times the CC registers were written
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-system.cpu0.num_store_insts 5106061 # Number of store instructions
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-system.cpu0.not_idle_fraction 0.049657 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.950343 # Percentage of idle cycles
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-system.cpu0.op_class::No_OpClass 146086 0.13% 0.13% # Class of executed instruction
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system.cpu0.kern.inst.arm 0 # number of arm instructions executed
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system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks
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system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu1.kern.inst.arm 0 # number of arm instructions executed
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-system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 529385
-system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 340176
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 66107376
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 4235080
-system.ruby.network.routers0.throttle1.link_utilization 0.023034
-system.ruby.network.routers0.throttle1.msg_count.Control::0 930371
-system.ruby.network.routers0.throttle1.msg_count.Response_Data::1 40359
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 16232
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 541977
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 316333
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 73
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 187850
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-system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::1 2905848
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 129856
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system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 373888
system.ruby.network.routers4.throttle0.link_utilization 0.000255
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system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::1 46736
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system.ruby.network.routers4.throttle1.link_utilization 0.000224
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system.ruby.network.routers5.throttle4.link_utilization 0.000255
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system.ruby.network.routers5.throttle4.msg_count.Writeback_Control::1 46736
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system.ruby.network.routers5.throttle4.msg_bytes.Writeback_Control::1 373888
system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::samples 6099217 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::mean 0.754439 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::stdev 2.340051 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0 | 5524579 90.58% 90.58% | 410 0.01% 90.59% | 573855 9.41% 99.99% | 123 0.00% 100.00% | 205 0.00% 100.00% | 8 0.00% 100.00% | 37 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::total 6099217 # delay histogram for vnet_0
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+system.ruby.delayVCHist.vnet_0::mean 0.755007 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::stdev 2.340941 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0 | 5519285 90.57% 90.57% | 399 0.01% 90.58% | 573737 9.42% 99.99% | 123 0.00% 100.00% | 210 0.00% 100.00% | 12 0.00% 100.00% | 36 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::total 6093802 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples 4683807 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean 0.044910 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev 0.595023 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 4656927 99.43% 99.43% | 381 0.01% 99.43% | 370 0.01% 99.44% | 589 0.01% 99.45% | 25416 0.54% 100.00% | 122 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total 4683807 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::samples 4681516 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::mean 0.044663 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::stdev 0.593096 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1 | 4654718 99.43% 99.43% | 447 0.01% 99.44% | 398 0.01% 99.45% | 648 0.01% 99.46% | 25177 0.54% 100.00% | 123 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total 4681516 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples 81344 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean 0.000123 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev 0.015680 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2 | 81339 99.99% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total 81344 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::samples 80651 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::mean 0.000124 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::stdev 0.015747 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2 | 80646 99.99% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::total 80651 # delay histogram for vnet_2
system.ruby.LD.latency_hist::bucket_size 16
system.ruby.LD.latency_hist::max_bucket 159
-system.ruby.LD.latency_hist::samples 14937313
-system.ruby.LD.latency_hist::mean 4.746801
-system.ruby.LD.latency_hist::gmean 3.589441
-system.ruby.LD.latency_hist::stdev 6.550511
-system.ruby.LD.latency_hist | 13550250 90.71% 90.71% | 1355967 9.08% 99.79% | 85 0.00% 99.79% | 0 0.00% 99.79% | 9654 0.06% 99.86% | 173 0.00% 99.86% | 20215 0.14% 99.99% | 758 0.01% 100.00% | 186 0.00% 100.00% | 25 0.00% 100.00%
-system.ruby.LD.latency_hist::total 14937313
+system.ruby.LD.latency_hist::samples 14920569
+system.ruby.LD.latency_hist::mean 4.752955
+system.ruby.LD.latency_hist::gmean 3.589881
+system.ruby.LD.latency_hist::stdev 6.604009
+system.ruby.LD.latency_hist | 13535034 90.71% 90.71% | 1353292 9.07% 99.78% | 96 0.00% 99.78% | 0 0.00% 99.78% | 9982 0.07% 99.85% | 163 0.00% 99.85% | 20984 0.14% 99.99% | 796 0.01% 100.00% | 200 0.00% 100.00% | 22 0.00% 100.00%
+system.ruby.LD.latency_hist::total 14920569
system.ruby.LD.hit_latency_hist::bucket_size 1
system.ruby.LD.hit_latency_hist::max_bucket 9
-system.ruby.LD.hit_latency_hist::samples 13550250
+system.ruby.LD.hit_latency_hist::samples 13535034
system.ruby.LD.hit_latency_hist::mean 3
system.ruby.LD.hit_latency_hist::gmean 3.000000
-system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13550250 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist::total 13550250
+system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13535034 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.hit_latency_hist::total 13535034
system.ruby.LD.miss_latency_hist::bucket_size 16
system.ruby.LD.miss_latency_hist::max_bucket 159
-system.ruby.LD.miss_latency_hist::samples 1387063
-system.ruby.LD.miss_latency_hist::mean 21.811342
-system.ruby.LD.miss_latency_hist::gmean 20.705599
-system.ruby.LD.miss_latency_hist::stdev 11.877845
-system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 1355967 97.76% 97.76% | 85 0.01% 97.76% | 0 0.00% 97.76% | 9654 0.70% 98.46% | 173 0.01% 98.47% | 20215 1.46% 99.93% | 758 0.05% 99.98% | 186 0.01% 100.00% | 25 0.00% 100.00%
-system.ruby.LD.miss_latency_hist::total 1387063
+system.ruby.LD.miss_latency_hist::samples 1385535
+system.ruby.LD.miss_latency_hist::mean 21.877250
+system.ruby.LD.miss_latency_hist::gmean 20.732182
+system.ruby.LD.miss_latency_hist::stdev 12.099590
+system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 1353292 97.67% 97.67% | 96 0.01% 97.68% | 0 0.00% 97.68% | 9982 0.72% 98.40% | 163 0.01% 98.41% | 20984 1.51% 99.93% | 796 0.06% 99.98% | 200 0.01% 100.00% | 22 0.00% 100.00%
+system.ruby.LD.miss_latency_hist::total 1385535
system.ruby.ST.latency_hist::bucket_size 32
system.ruby.ST.latency_hist::max_bucket 319
-system.ruby.ST.latency_hist::samples 9501279
-system.ruby.ST.latency_hist::mean 4.608129
-system.ruby.ST.latency_hist::gmean 3.286792
-system.ruby.ST.latency_hist::stdev 10.643686
-system.ruby.ST.latency_hist | 9375615 98.68% 98.68% | 20 0.00% 98.68% | 64184 0.68% 99.35% | 60844 0.64% 99.99% | 614 0.01% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.latency_hist::total 9501279
+system.ruby.ST.latency_hist::samples 9491428
+system.ruby.ST.latency_hist::mean 4.608485
+system.ruby.ST.latency_hist::gmean 3.286938
+system.ruby.ST.latency_hist::stdev 10.640707
+system.ruby.ST.latency_hist | 9365714 98.68% 98.68% | 17 0.00% 98.68% | 64552 0.68% 99.36% | 60510 0.64% 99.99% | 633 0.01% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.latency_hist::total 9491428
system.ruby.ST.hit_latency_hist::bucket_size 1
system.ruby.ST.hit_latency_hist::max_bucket 9
-system.ruby.ST.hit_latency_hist::samples 9151065
+system.ruby.ST.hit_latency_hist::samples 9141411
system.ruby.ST.hit_latency_hist::mean 3
system.ruby.ST.hit_latency_hist::gmean 3.000000
-system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9151065 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.hit_latency_hist::total 9151065
+system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9141411 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.hit_latency_hist::total 9141411
system.ruby.ST.miss_latency_hist::bucket_size 32
system.ruby.ST.miss_latency_hist::max_bucket 319
-system.ruby.ST.miss_latency_hist::samples 350214
-system.ruby.ST.miss_latency_hist::mean 46.628404
-system.ruby.ST.miss_latency_hist::gmean 35.714857
-system.ruby.ST.miss_latency_hist::stdev 35.216783
-system.ruby.ST.miss_latency_hist | 224550 64.12% 64.12% | 20 0.01% 64.12% | 64184 18.33% 82.45% | 60844 17.37% 99.82% | 614 0.18% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.miss_latency_hist::total 350214
+system.ruby.ST.miss_latency_hist::samples 350017
+system.ruby.ST.miss_latency_hist::mean 46.617353
+system.ruby.ST.miss_latency_hist::gmean 35.715902
+system.ruby.ST.miss_latency_hist::stdev 35.185303
+system.ruby.ST.miss_latency_hist | 224303 64.08% 64.08% | 17 0.00% 64.09% | 64552 18.44% 82.53% | 60510 17.29% 99.82% | 633 0.18% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.miss_latency_hist::total 350017
system.ruby.IFETCH.latency_hist::bucket_size 16
system.ruby.IFETCH.latency_hist::max_bucket 159
-system.ruby.IFETCH.latency_hist::samples 126633666
-system.ruby.IFETCH.latency_hist::mean 3.112947
-system.ruby.IFETCH.latency_hist::gmean 3.036567
-system.ruby.IFETCH.latency_hist::stdev 1.654702
-system.ruby.IFETCH.latency_hist | 125816178 99.35% 99.35% | 802052 0.63% 99.99% | 5 0.00% 99.99% | 0 0.00% 99.99% | 3918 0.00% 99.99% | 22 0.00% 99.99% | 11172 0.01% 100.00% | 208 0.00% 100.00% | 111 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist::total 126633666
+system.ruby.IFETCH.latency_hist::samples 126544851
+system.ruby.IFETCH.latency_hist::mean 3.112747
+system.ruby.IFETCH.latency_hist::gmean 3.036514
+system.ruby.IFETCH.latency_hist::stdev 1.652226
+system.ruby.IFETCH.latency_hist | 125729046 99.36% 99.36% | 800495 0.63% 99.99% | 4 0.00% 99.99% | 0 0.00% 99.99% | 3856 0.00% 99.99% | 28 0.00% 99.99% | 11079 0.01% 100.00% | 224 0.00% 100.00% | 119 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.latency_hist::total 126544851
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
-system.ruby.IFETCH.hit_latency_hist::samples 125816178
+system.ruby.IFETCH.hit_latency_hist::samples 125729046
system.ruby.IFETCH.hit_latency_hist::mean 3
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
-system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 125816178 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.hit_latency_hist::total 125816178
+system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 125729046 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.hit_latency_hist::total 125729046
system.ruby.IFETCH.miss_latency_hist::bucket_size 16
system.ruby.IFETCH.miss_latency_hist::max_bucket 159
-system.ruby.IFETCH.miss_latency_hist::samples 817488
-system.ruby.IFETCH.miss_latency_hist::mean 20.496144
-system.ruby.IFETCH.miss_latency_hist::gmean 19.596306
-system.ruby.IFETCH.miss_latency_hist::stdev 10.954425
-system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 802052 98.11% 98.11% | 5 0.00% 98.11% | 0 0.00% 98.11% | 3918 0.48% 98.59% | 22 0.00% 98.59% | 11172 1.37% 99.96% | 208 0.03% 99.99% | 111 0.01% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.miss_latency_hist::total 817488
+system.ruby.IFETCH.miss_latency_hist::samples 815805
+system.ruby.IFETCH.miss_latency_hist::mean 20.488864
+system.ruby.IFETCH.miss_latency_hist::gmean 19.593048
+system.ruby.IFETCH.miss_latency_hist::stdev 10.934190
+system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 800495 98.12% 98.12% | 4 0.00% 98.12% | 0 0.00% 98.12% | 3856 0.47% 98.60% | 28 0.00% 98.60% | 11079 1.36% 99.96% | 224 0.03% 99.99% | 119 0.01% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist::total 815805
system.ruby.RMW_Read.latency_hist::bucket_size 16
system.ruby.RMW_Read.latency_hist::max_bucket 159
-system.ruby.RMW_Read.latency_hist::samples 494951
-system.ruby.RMW_Read.latency_hist::mean 5.895220
-system.ruby.RMW_Read.latency_hist::gmean 3.951159
-system.ruby.RMW_Read.latency_hist::stdev 8.211294
-system.ruby.RMW_Read.latency_hist | 429288 86.73% 86.73% | 64260 12.98% 99.72% | 3 0.00% 99.72% | 0 0.00% 99.72% | 989 0.20% 99.92% | 21 0.00% 99.92% | 364 0.07% 99.99% | 22 0.00% 100.00% | 3 0.00% 100.00% | 1 0.00% 100.00%
-system.ruby.RMW_Read.latency_hist::total 494951
+system.ruby.RMW_Read.latency_hist::samples 494298
+system.ruby.RMW_Read.latency_hist::mean 5.892257
+system.ruby.RMW_Read.latency_hist::gmean 3.949809
+system.ruby.RMW_Read.latency_hist::stdev 8.207792
+system.ruby.RMW_Read.latency_hist | 428816 86.75% 86.75% | 64079 12.96% 99.72% | 2 0.00% 99.72% | 0 0.00% 99.72% | 994 0.20% 99.92% | 20 0.00% 99.92% | 365 0.07% 100.00% | 18 0.00% 100.00% | 3 0.00% 100.00% | 1 0.00% 100.00%
+system.ruby.RMW_Read.latency_hist::total 494298
system.ruby.RMW_Read.hit_latency_hist::bucket_size 1
system.ruby.RMW_Read.hit_latency_hist::max_bucket 9
-system.ruby.RMW_Read.hit_latency_hist::samples 429288
+system.ruby.RMW_Read.hit_latency_hist::samples 428816
system.ruby.RMW_Read.hit_latency_hist::mean 3
system.ruby.RMW_Read.hit_latency_hist::gmean 3.000000
-system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 429288 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.RMW_Read.hit_latency_hist::total 429288
+system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 428816 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.RMW_Read.hit_latency_hist::total 428816
system.ruby.RMW_Read.miss_latency_hist::bucket_size 16
system.ruby.RMW_Read.miss_latency_hist::max_bucket 159
-system.ruby.RMW_Read.miss_latency_hist::samples 65663
-system.ruby.RMW_Read.miss_latency_hist::mean 24.823432
-system.ruby.RMW_Read.miss_latency_hist::gmean 23.914448
-system.ruby.RMW_Read.miss_latency_hist::stdev 9.754848
-system.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 64260 97.86% 97.86% | 3 0.00% 97.87% | 0 0.00% 97.87% | 989 1.51% 99.37% | 21 0.03% 99.41% | 364 0.55% 99.96% | 22 0.03% 99.99% | 3 0.00% 100.00% | 1 0.00% 100.00%
-system.ruby.RMW_Read.miss_latency_hist::total 65663
+system.ruby.RMW_Read.miss_latency_hist::samples 65482
+system.ruby.RMW_Read.miss_latency_hist::mean 24.832519
+system.ruby.RMW_Read.miss_latency_hist::gmean 23.924296
+system.ruby.RMW_Read.miss_latency_hist::stdev 9.747837
+system.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 64079 97.86% 97.86% | 2 0.00% 97.86% | 0 0.00% 97.86% | 994 1.52% 99.38% | 20 0.03% 99.41% | 365 0.56% 99.97% | 18 0.03% 99.99% | 3 0.00% 100.00% | 1 0.00% 100.00%
+system.ruby.RMW_Read.miss_latency_hist::total 65482
system.ruby.Locked_RMW_Read.latency_hist::bucket_size 16
system.ruby.Locked_RMW_Read.latency_hist::max_bucket 159
-system.ruby.Locked_RMW_Read.latency_hist::samples 339622
-system.ruby.Locked_RMW_Read.latency_hist::mean 5.235927
-system.ruby.Locked_RMW_Read.latency_hist::gmean 3.761812
-system.ruby.Locked_RMW_Read.latency_hist::stdev 6.715360
-system.ruby.Locked_RMW_Read.latency_hist | 301290 88.71% 88.71% | 38000 11.19% 99.90% | 7 0.00% 99.90% | 0 0.00% 99.90% | 176 0.05% 99.96% | 2 0.00% 99.96% | 134 0.04% 100.00% | 12 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Read.latency_hist::total 339622
+system.ruby.Locked_RMW_Read.latency_hist::samples 339492
+system.ruby.Locked_RMW_Read.latency_hist::mean 5.237555
+system.ruby.Locked_RMW_Read.latency_hist::gmean 3.760998
+system.ruby.Locked_RMW_Read.latency_hist::stdev 6.749704
+system.ruby.Locked_RMW_Read.latency_hist | 301225 88.73% 88.73% | 37910 11.17% 99.89% | 7 0.00% 99.90% | 0 0.00% 99.90% | 190 0.06% 99.95% | 1 0.00% 99.95% | 148 0.04% 100.00% | 10 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Locked_RMW_Read.latency_hist::total 339492
system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size 1
system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket 9
-system.ruby.Locked_RMW_Read.hit_latency_hist::samples 301290
+system.ruby.Locked_RMW_Read.hit_latency_hist::samples 301225
system.ruby.Locked_RMW_Read.hit_latency_hist::mean 3
system.ruby.Locked_RMW_Read.hit_latency_hist::gmean 3.000000
-system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 301290 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Read.hit_latency_hist::total 301290
+system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 301225 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Locked_RMW_Read.hit_latency_hist::total 301225
system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 16
system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 159
-system.ruby.Locked_RMW_Read.miss_latency_hist::samples 38332
-system.ruby.Locked_RMW_Read.miss_latency_hist::mean 22.810341
-system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.276488
-system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 7.169146
-system.ruby.Locked_RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 38000 99.13% 99.13% | 7 0.02% 99.15% | 0 0.00% 99.15% | 176 0.46% 99.61% | 2 0.01% 99.62% | 134 0.35% 99.97% | 12 0.03% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Read.miss_latency_hist::total 38332
+system.ruby.Locked_RMW_Read.miss_latency_hist::samples 38267
+system.ruby.Locked_RMW_Read.miss_latency_hist::mean 22.850838
+system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.292446
+system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 7.385228
+system.ruby.Locked_RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 37910 99.07% 99.07% | 7 0.02% 99.09% | 0 0.00% 99.09% | 190 0.50% 99.58% | 1 0.00% 99.58% | 148 0.39% 99.97% | 10 0.03% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Locked_RMW_Read.miss_latency_hist::total 38267
system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1
system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9
-system.ruby.Locked_RMW_Write.latency_hist::samples 339622
+system.ruby.Locked_RMW_Write.latency_hist::samples 339492
system.ruby.Locked_RMW_Write.latency_hist::mean 3
system.ruby.Locked_RMW_Write.latency_hist::gmean 3.000000
-system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339622 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Write.latency_hist::total 339622
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system.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size 1
system.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket 9
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system.ruby.Locked_RMW_Write.hit_latency_hist::mean 3
system.ruby.Locked_RMW_Write.hit_latency_hist::gmean 3.000000
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system.ruby.L1Cache_Controller.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00%
system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total 4
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-system.ruby.L1Cache_Controller.Ack | 12213 55.20% 55.20% | 9911 44.80% 100.00%
-system.ruby.L1Cache_Controller.Ack::total 22124
-system.ruby.L1Cache_Controller.Ack_all | 12989 54.53% 54.53% | 10829 45.47% 100.00%
-system.ruby.L1Cache_Controller.Ack_all::total 23818
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system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00%
system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total 4
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-system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 10969 43.68% 43.68% | 14142 56.32% 100.00%
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+system.ruby.L2Cache_Controller.SS.L1_GETX 1783 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_UPGRADE 21814 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement 268 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 6335 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.MEM_Inv 3 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L1_GET_INSTR 28 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS 1247342 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 279324 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 94480 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement_clean 5571 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.MEM_Inv 1763 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS 1245738 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX 279152 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement 94920 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement_clean 6421 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.MEM_Inv 1897 0.00% 0.00%
system.ruby.L2Cache_Controller.MT.L1_GET_INSTR 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETS 25107 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETX 23663 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX 1682784 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement 153 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 115 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.MEM_Inv 81 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.Mem_Ack 108923 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.MEM_Inv 1763 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_I.WB_Data 187 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_I.Ack_all 47 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_I.MEM_Inv 81 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data 89 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.Ack_all 26 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_I.Ack 1386 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_I.Ack_all 6503 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_I.Ack 257 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_I.Ack_all 257 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_I.MEM_Inv 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.Mem_Data 31011 0.00% 0.00%
-system.ruby.L2Cache_Controller.IS.Mem_Data 15431 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.Mem_Data 127369 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.L1_GETS 164 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 23853 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_GETS 46 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1708709 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data 22985 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2126 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_SB.Unblock 25111 0.00% 0.00%
-system.ruby.DMA_Controller.ReadRequest 811 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETS 24859 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETX 23569 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX 1682182 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement 161 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 108 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.MEM_Inv 116 0.00% 0.00%
+system.ruby.L2Cache_Controller.M_I.Mem_Ack 110229 0.00% 0.00%
+system.ruby.L2Cache_Controller.M_I.MEM_Inv 1897 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_I.WB_Data 229 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_I.Ack_all 48 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_I.MEM_Inv 116 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data 75 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.Ack_all 33 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_I.Ack 1395 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_I.Ack_all 6335 0.00% 0.00%
+system.ruby.L2Cache_Controller.S_I.Ack 271 0.00% 0.00%
+system.ruby.L2Cache_Controller.S_I.Ack_all 271 0.00% 0.00%
+system.ruby.L2Cache_Controller.S_I.MEM_Inv 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.ISS.Mem_Data 32147 0.00% 0.00%
+system.ruby.L2Cache_Controller.IS.Mem_Data 15306 0.00% 0.00%
+system.ruby.L2Cache_Controller.IM.Mem_Data 127448 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS_MB.L1_GETS 111 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 23597 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_GETS 37 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_GETX 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1708054 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data 22706 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2155 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IIB.Unblock 2 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IB.WB_Data 2 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_SB.Unblock 24861 0.00% 0.00%
+system.ruby.DMA_Controller.ReadRequest 814 0.00% 0.00%
system.ruby.DMA_Controller.WriteRequest 46736 0.00% 0.00%
-system.ruby.DMA_Controller.Data 811 0.00% 0.00%
+system.ruby.DMA_Controller.Data 814 0.00% 0.00%
system.ruby.DMA_Controller.Ack 46736 0.00% 0.00%
-system.ruby.DMA_Controller.READY.ReadRequest 811 0.00% 0.00%
+system.ruby.DMA_Controller.READY.ReadRequest 814 0.00% 0.00%
system.ruby.DMA_Controller.READY.WriteRequest 46736 0.00% 0.00%
-system.ruby.DMA_Controller.BUSY_RD.Data 811 0.00% 0.00%
+system.ruby.DMA_Controller.BUSY_RD.Data 814 0.00% 0.00%
system.ruby.DMA_Controller.BUSY_WR.Ack 46736 0.00% 0.00%
-system.ruby.Directory_Controller.Fetch 173811 0.00% 0.00%
-system.ruby.Directory_Controller.Data 96823 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 174271 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 142062 0.00% 0.00%
-system.ruby.Directory_Controller.DMA_READ 811 0.00% 0.00%
+system.ruby.Directory_Controller.Fetch 174901 0.00% 0.00%
+system.ruby.Directory_Controller.Data 97440 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 175364 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 142511 0.00% 0.00%
+system.ruby.Directory_Controller.DMA_READ 814 0.00% 0.00%
system.ruby.Directory_Controller.DMA_WRITE 46736 0.00% 0.00%
-system.ruby.Directory_Controller.CleanReplacement 12100 0.00% 0.00%
-system.ruby.Directory_Controller.I.Fetch 173811 0.00% 0.00%
-system.ruby.Directory_Controller.I.DMA_READ 460 0.00% 0.00%
-system.ruby.Directory_Controller.I.DMA_WRITE 45239 0.00% 0.00%
-system.ruby.Directory_Controller.ID.Memory_Data 460 0.00% 0.00%
-system.ruby.Directory_Controller.ID_W.Memory_Ack 45239 0.00% 0.00%
-system.ruby.Directory_Controller.M.Data 94975 0.00% 0.00%
+system.ruby.Directory_Controller.CleanReplacement 12789 0.00% 0.00%
+system.ruby.Directory_Controller.I.Fetch 174901 0.00% 0.00%
+system.ruby.Directory_Controller.I.DMA_READ 463 0.00% 0.00%
+system.ruby.Directory_Controller.I.DMA_WRITE 45071 0.00% 0.00%
+system.ruby.Directory_Controller.ID.Memory_Data 463 0.00% 0.00%
+system.ruby.Directory_Controller.ID_W.Memory_Ack 45071 0.00% 0.00%
+system.ruby.Directory_Controller.M.Data 95424 0.00% 0.00%
system.ruby.Directory_Controller.M.DMA_READ 351 0.00% 0.00%
-system.ruby.Directory_Controller.M.DMA_WRITE 1497 0.00% 0.00%
-system.ruby.Directory_Controller.M.CleanReplacement 12100 0.00% 0.00%
-system.ruby.Directory_Controller.IM.Memory_Data 173811 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack 94975 0.00% 0.00%
+system.ruby.Directory_Controller.M.DMA_WRITE 1665 0.00% 0.00%
+system.ruby.Directory_Controller.M.CleanReplacement 12789 0.00% 0.00%
+system.ruby.Directory_Controller.IM.Memory_Data 174901 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack 95424 0.00% 0.00%
system.ruby.Directory_Controller.M_DRD.Data 351 0.00% 0.00%
system.ruby.Directory_Controller.M_DRDI.Memory_Ack 351 0.00% 0.00%
-system.ruby.Directory_Controller.M_DWR.Data 1497 0.00% 0.00%
-system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1497 0.00% 0.00%
+system.ruby.Directory_Controller.M_DWR.Data 1665 0.00% 0.00%
+system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1665 0.00% 0.00%
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 5.137881 # Number of seconds simulated
-sim_ticks 5137881357500 # Number of ticks simulated
-final_tick 5137881357500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.133872 # Number of seconds simulated
+sim_ticks 5133872107500 # Number of ticks simulated
+final_tick 5133872107500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 401147 # Simulator instruction rate (inst/s)
-host_op_rate 797370 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 8430324111 # Simulator tick rate (ticks/s)
-host_mem_usage 944704 # Number of bytes of host memory used
-host_seconds 609.45 # Real time elapsed on the host
-sim_insts 244480058 # Number of instructions simulated
-sim_ops 485958826 # Number of ops (including micro ops) simulated
+host_inst_rate 287663 # Simulator instruction rate (inst/s)
+host_op_rate 571806 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6046720341 # Simulator tick rate (ticks/s)
+host_mem_usage 1024224 # Number of bytes of host memory used
+host_seconds 849.03 # Real time elapsed on the host
+sim_insts 244235751 # Number of instructions simulated
+sim_ops 485482573 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 396800 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 5697984 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 149888 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 1826880 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 430976 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 2905472 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11438656 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 396800 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 149888 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 430976 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 977664 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6187584 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 396736 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 5572928 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 164928 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 1639680 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker 2240 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 412864 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 3220800 # Number of bytes read from this memory
+system.physmem.bytes_read::total 11438848 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 396736 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 164928 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 412864 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 974528 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6205312 # Number of bytes written to this memory
system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9177664 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9195392 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 6200 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 89031 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 2342 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 28545 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 6734 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 45398 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 178729 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 96681 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 6199 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 87077 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 2577 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 25620 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker 35 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 6451 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 50325 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 178732 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 96958 # Number of write requests responded to by this memory
system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 143401 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 5518 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 77230 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1109014 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 29173 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 355571 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker 386 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 83882 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 565500 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2226337 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 77230 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 29173 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 83882 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 190285 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1204307 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide 581968 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1786274 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1204307 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 587486 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 77230 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 1109014 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 29173 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 355571 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker 386 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 83882 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 565500 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4012611 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 83494 # Number of read requests accepted
-system.physmem.writeReqs 76163 # Number of write requests accepted
-system.physmem.readBursts 83494 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 76163 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 5331584 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 12032 # Total number of bytes read from write queue
-system.physmem.bytesWritten 4872768 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 5343616 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 4874432 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 188 # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_writes::total 143678 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 5523 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 77278 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1085521 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 32125 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 319385 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker 436 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 80420 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 627363 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2228113 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 77278 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 32125 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 80420 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 189823 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1208700 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide 582422 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1791122 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1208700 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 587945 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 77278 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1085521 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 32125 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 319385 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker 436 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 80420 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 627363 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4019235 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 85451 # Number of read requests accepted
+system.physmem.writeReqs 85019 # Number of write requests accepted
+system.physmem.readBursts 85451 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 85019 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 5457024 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 11840 # Total number of bytes read from write queue
+system.physmem.bytesWritten 5440128 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 5468864 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 5441216 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 185 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 873 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 4736 # Per bank write bursts
-system.physmem.perBankRdBursts::1 4757 # Per bank write bursts
-system.physmem.perBankRdBursts::2 5051 # Per bank write bursts
-system.physmem.perBankRdBursts::3 5281 # Per bank write bursts
-system.physmem.perBankRdBursts::4 5400 # Per bank write bursts
-system.physmem.perBankRdBursts::5 4765 # Per bank write bursts
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-system.physmem.bytesPerActivate::1024-1151 3103 8.06% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 38507 # Bytes accessed per row activation
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-system.physmem.rdPerTurnAround::mean 21.615365 # Reads before turning the bus around for writes
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-system.physmem.rdPerTurnAround::0-255 3842 99.71% 99.71% # Reads before turning the bus around for writes
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-system.physmem.rdPerTurnAround::512-767 1 0.03% 99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2560-2815 1 0.03% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::6656-6911 1 0.03% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 3853 # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::mean 19.760446 # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::0-3 66 1.71% 1.71% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::20-23 44 1.14% 88.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 26 0.67% 88.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 135 3.50% 92.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 114 2.96% 95.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 3 0.08% 95.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 14 0.36% 95.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 8 0.21% 95.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 13 0.34% 96.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 2 0.05% 96.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 2 0.05% 96.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 1 0.03% 96.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 96 2.49% 98.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 1 0.03% 98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 5 0.13% 99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 13 0.34% 99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 4 0.10% 99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 1 0.03% 99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 2 0.05% 99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 1 0.03% 99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 5 0.13% 99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 2 0.05% 99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 1 0.03% 99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 1 0.03% 99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 4 0.10% 99.95% # Writes before turning the bus around for reads
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+system.physmem.bytesPerActivate::128-255 9834 24.61% 65.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 4112 10.29% 75.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2230 5.58% 81.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 1552 3.88% 85.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1069 2.68% 87.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 711 1.78% 89.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 597 1.49% 91.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 3512 8.79% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 39962 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 4105 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 20.770767 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 117.592245 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-255 4095 99.76% 99.76% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::256-511 7 0.17% 99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-767 1 0.02% 99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2560-2815 1 0.02% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::6656-6911 1 0.02% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 4105 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 4105 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 20.706943 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.214534 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 13.616872 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3 63 1.53% 1.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7 7 0.17% 1.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11 1 0.02% 1.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15 4 0.10% 1.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 3359 81.83% 83.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 49 1.19% 84.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 26 0.63% 85.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 173 4.21% 89.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 182 4.43% 94.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 7 0.17% 94.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 12 0.29% 94.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 8 0.19% 94.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 10 0.24% 95.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 2 0.05% 95.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 1 0.02% 95.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 1 0.02% 95.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 157 3.82% 98.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 1 0.02% 98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 3 0.07% 99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 10 0.24% 99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 1 0.02% 99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 7 0.17% 99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 2 0.05% 99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 2 0.05% 99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 5 0.12% 99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 2 0.05% 99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 8 0.19% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.05% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 3853 # Writes before turning the bus around for reads
-system.physmem.totQLat 942120750 # Total ticks spent queuing
-system.physmem.totMemAccLat 2504108250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 416530000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11309.16 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total 4105 # Writes before turning the bus around for reads
+system.physmem.totQLat 1041221500 # Total ticks spent queuing
+system.physmem.totMemAccLat 2639959000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 426330000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 12211.45 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30059.16 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.04 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.95 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.04 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.95 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 30961.45 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.06 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.06 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.07 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.06 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 7.45 # Average write queue length when enqueuing
-system.physmem.readRowHits 65566 # Number of row buffer hits during reads
-system.physmem.writeRowHits 55368 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 78.71 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 72.70 # Row buffer hit rate for writes
-system.physmem.avgGap 32174481.33 # Average gap between requests
-system.physmem.pageHitRate 75.84 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 4942580735250 # Time in different power states
-system.physmem.memoryStateTime::REF 171564900000 # Time in different power states
+system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 6.94 # Average write queue length when enqueuing
+system.physmem.readRowHits 67077 # Number of row buffer hits during reads
+system.physmem.writeRowHits 63228 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 78.67 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 74.37 # Row buffer hit rate for writes
+system.physmem.avgGap 30110118.97 # Average gap between requests
+system.physmem.pageHitRate 76.52 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 4938526642750 # Time in different power states
+system.physmem.memoryStateTime::REF 171431260000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 23734191750 # Time in different power states
+system.physmem.memoryStateTime::ACT 23914099250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 5877722 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 425622 # Transaction distribution
-system.membus.trans_dist::ReadResp 425619 # Transaction distribution
-system.membus.trans_dist::WriteReq 7303 # Transaction distribution
-system.membus.trans_dist::WriteResp 7303 # Transaction distribution
-system.membus.trans_dist::Writeback 54691 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 21472 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 21472 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 873 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 873 # Transaction distribution
-system.membus.trans_dist::ReadExReq 56661 # Transaction distribution
-system.membus.trans_dist::ReadExResp 56661 # Transaction distribution
-system.membus.trans_dist::MessageReq 1005 # Transaction distribution
-system.membus.trans_dist::MessageResp 1005 # Transaction distribution
-system.membus.trans_dist::BadAddressError 3 # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 2010 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total 2010 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 313168 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 498446 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 222539 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 6 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 1034159 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 44112 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 44112 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1080281 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 4020 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::total 4020 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 160913 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 996889 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8815488 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total 9973290 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 1402560 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 1402560 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 11379870 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 30180989 # Total data (bytes)
-system.membus.snoop_data_through_bus 18048 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 165986000 # Layer occupancy (ticks)
+system.membus.trans_dist::ReadReq 5056260 # Transaction distribution
+system.membus.trans_dist::ReadResp 5056258 # Transaction distribution
+system.membus.trans_dist::WriteReq 13754 # Transaction distribution
+system.membus.trans_dist::WriteResp 13754 # Transaction distribution
+system.membus.trans_dist::Writeback 96958 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 1654 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 1654 # Transaction distribution
+system.membus.trans_dist::ReadExReq 129924 # Transaction distribution
+system.membus.trans_dist::ReadExResp 129924 # Transaction distribution
+system.membus.trans_dist::MessageReq 1664 # Transaction distribution
+system.membus.trans_dist::MessageResp 1664 # Transaction distribution
+system.membus.trans_dist::BadAddressError 2 # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3328 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total 3328 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7028524 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3012958 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 456844 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 10498330 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94955 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 94955 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 10596613 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6656 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total 6656 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3520458 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6025913 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17615808 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 27162179 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3029056 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 3029056 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 30197891 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 297 # Total snoops (count)
+system.membus.snoop_fanout::samples 324529 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 324529 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 324529 # Request fanout histogram
+system.membus.reqLayer0.occupancy 165183000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 315728000 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 315920500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 2010000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 1960000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 815495498 # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy 897247500 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 3500 # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer0.occupancy 1005000 # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy 980000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1662343876 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 1679098885 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer4.occupancy 28017243 # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy 35042997 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 105452 # number of replacements
-system.l2c.tags.tagsinuse 64826.295665 # Cycle average of tags in use
-system.l2c.tags.total_refs 3690842 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 169644 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 21.756396 # Average number of references to valid blocks.
+system.l2c.tags.replacements 105529 # number of replacements
+system.l2c.tags.tagsinuse 64826.632454 # Cycle average of tags in use
+system.l2c.tags.total_refs 3692969 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 169653 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 21.767779 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 50973.887089 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131156 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 1039.864675 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 3857.355286 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 297.125354 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 1525.078899 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.736641 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.itb.walker 0.003210 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 1792.530465 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 5328.582890 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.777800 # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks 50921.041202 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134275 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 1022.158767 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 3887.538850 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 285.540185 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 1563.161522 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker 13.370475 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst 1774.545144 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data 5359.142034 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.776993 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.015867 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.058859 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.004534 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.023271 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000179 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst 0.027352 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data 0.081308 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.989171 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024 64192 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 605 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 3319 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 7395 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 52837 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024 0.979492 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 33876235 # Number of tag accesses
-system.l2c.tags.data_accesses 33876235 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker 20790 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 10881 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 323642 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 493790 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 11848 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 6379 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 159823 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 243124 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker 53625 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker 12570 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst 372046 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data 571492 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 2280010 # number of ReadReq hits
+system.l2c.tags.occ_percent::cpu0.inst 0.015597 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data 0.059319 # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu1.data 0.023852 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000204 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst 0.027077 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data 0.081774 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.989176 # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024 64124 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1 541 # Occupied blocks per task id
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+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 132202779 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 132202779 # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 132202779 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 132202779 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 132202779 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 132202779 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 906 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 906 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 907 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 907 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 907 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 907 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 906 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 906 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 906 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 906 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145544.142227 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 145544.142227 # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145544.142227 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 145544.142227 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145544.142227 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 145544.142227 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145919.182119 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 145919.182119 # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145919.182119 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 145919.182119 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145919.182119 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 145919.182119 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 46720 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 725 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 725 # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 21472 # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total 21472 # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 725 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 725 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 725 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 725 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94282037 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 94282037 # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 1310743323 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1310743323 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 94282037 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 94282037 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 94282037 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 94282037 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.799338 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 0.799338 # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.459589 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.459589 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.799338 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 0.799338 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.799338 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 0.799338 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 130044.188966 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 130044.188966 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 61044.305281 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 61044.305281 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 130044.188966 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 130044.188966 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 130044.188966 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 130044.188966 # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 740 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 740 # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 28368 # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total 28368 # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 740 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 740 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 740 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 740 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93698779 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 93698779 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 1718205368 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1718205368 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 93698779 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 93698779 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 93698779 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 93698779 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.816777 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 0.816777 # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.607192 # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.607192 # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.816777 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 0.816777 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.816777 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 0.816777 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 126619.971622 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60568.435138 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60568.435138 # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 126619.971622 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 126619.971622 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.toL2Bus.throughput 53202678 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 1873297 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 1872762 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 7303 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 7303 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 935388 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 21472 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 816 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 816 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 157258 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 157258 # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError 3 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1081926 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3727147 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 42874 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 142768 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 4994715 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 34620672 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 124341034 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 151600 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 524032 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 159637338 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 270199237 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 3149808 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 5231949371 # Layer occupancy (ticks)
+system.toL2Bus.trans_dist::ReadReq 7367165 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 7366643 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 13756 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 13756 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 1548978 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 28368 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 1663 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 1663 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 296632 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 296632 # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1740682 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14873990 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 71302 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 198555 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 16884529 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55700736 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213654403 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 264160 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 728920 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 270348219 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 69633 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 4254339 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 3.011195 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.105211 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 4206713 98.88% 98.88% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 47626 1.12% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 4254339 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 5229007845 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 868500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 990000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 2437443949 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 2442789502 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 4869271823 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 4872933864 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 23963155 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 24776404 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 77561882 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 82986153 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.throughput 1275815 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 151004 # Transaction distribution
-system.iobus.trans_dist::ReadResp 151004 # Transaction distribution
-system.iobus.trans_dist::WriteReq 27777 # Transaction distribution
-system.iobus.trans_dist::WriteResp 27777 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1005 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1005 # Transaction distribution
+system.iobus.trans_dist::ReadReq 3504325 # Transaction distribution
+system.iobus.trans_dist::ReadResp 3504325 # Transaction distribution
+system.iobus.trans_dist::WriteReq 57563 # Transaction distribution
+system.iobus.trans_dist::WriteResp 39211 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 18352 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1664 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1664 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5602 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1160 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 50 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287262 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 594 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 142 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 16180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 6984892 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27280 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 313168 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 44394 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 44394 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 2010 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 2010 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 359572 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3164 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 580 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 25 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143631 # Cumulative packet size per connected master and slave (bytes)
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-system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 71 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 8090 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes)
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-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1410472 # Cumulative packet size per connected master and slave (bytes)
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-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 4020 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 1575405 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 6554984 # Total data (bytes)
-system.iobus.reqLayer0.occupancy 2375600 # Layer occupancy (ticks)
+system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
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+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95252 # Packet count per connected master and slave (bytes)
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+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3328 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 7127104 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
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+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
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+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
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+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
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+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 3520458 # Cumulative packet size per connected master and slave (bytes)
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+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027792 # Cumulative packet size per connected master and slave (bytes)
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+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6656 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 6554906 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 2324808 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 4000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 4638000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 4502000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 42000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 143632000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 469000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy 361000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 142000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 12075000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy 11636000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 194319603 # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy 256433144 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 1024000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 306863000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 306163000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 26743757 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 33668003 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 1005000 # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy 980000 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu0.numCycles 1069887436 # number of cpu cycles simulated
+system.cpu0.numCycles 1069607129 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 70857782 # Number of instructions committed
-system.cpu0.committedOps 144307609 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 132405898 # Number of integer alu accesses
+system.cpu0.committedInsts 70538619 # Number of instructions committed
+system.cpu0.committedOps 143755687 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 131850662 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu0.num_func_calls 941314 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 14024705 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 132405898 # number of integer instructions
+system.cpu0.num_func_calls 928819 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 13976393 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 131850662 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
-system.cpu0.num_int_register_reads 243097330 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 113712565 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 241989475 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 113259644 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 82467233 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 55021807 # number of times the CC registers were written
-system.cpu0.num_mem_refs 13631596 # number of memory refs
-system.cpu0.num_load_insts 10001277 # Number of load instructions
-system.cpu0.num_store_insts 3630319 # Number of store instructions
-system.cpu0.num_idle_cycles 1016044794.752217 # Number of idle cycles
-system.cpu0.num_busy_cycles 53842641.247783 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.050326 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.949674 # Percentage of idle cycles
-system.cpu0.Branches 15304700 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 96295 0.07% 0.07% # Class of executed instruction
-system.cpu0.op_class::IntAlu 130472194 90.41% 90.48% # Class of executed instruction
-system.cpu0.op_class::IntMult 58212 0.04% 90.52% # Class of executed instruction
-system.cpu0.op_class::IntDiv 49897 0.03% 90.55% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.55% # Class of executed instruction
-system.cpu0.op_class::MemRead 10001277 6.93% 97.48% # Class of executed instruction
-system.cpu0.op_class::MemWrite 3630319 2.52% 100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads 82136389 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 54810829 # number of times the CC registers were written
+system.cpu0.num_mem_refs 13501731 # number of memory refs
+system.cpu0.num_load_insts 9912408 # Number of load instructions
+system.cpu0.num_store_insts 3589323 # Number of store instructions
+system.cpu0.num_idle_cycles 1016224343.330366 # Number of idle cycles
+system.cpu0.num_busy_cycles 53382785.669634 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.049909 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.950091 # Percentage of idle cycles
+system.cpu0.Branches 15238819 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 94852 0.07% 0.07% # Class of executed instruction
+system.cpu0.op_class::IntAlu 130054750 90.47% 90.53% # Class of executed instruction
+system.cpu0.op_class::IntMult 56051 0.04% 90.57% # Class of executed instruction
+system.cpu0.op_class::IntDiv 48845 0.03% 90.61% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 90.61% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 90.61% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 90.61% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 90.61% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 90.61% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 90.61% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 90.61% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 90.61% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 90.61% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 90.61% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 90.61% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 90.61% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 90.61% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 90.61% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 90.61% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.61% # Class of executed instruction
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+system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.61% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.61% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.61% # Class of executed instruction
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+system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.61% # Class of executed instruction
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+system.cpu0.op_class::MemRead 9912408 6.90% 97.50% # Class of executed instruction
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system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 144308194 # Class of executed instruction
+system.cpu0.op_class::total 143756229 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements 870298 # number of replacements
-system.cpu0.icache.tags.tagsinuse 510.224543 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 128999874 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 870810 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 148.137796 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 147420132000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 125.471919 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 137.049993 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst 247.702632 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.245062 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.267676 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst 0.483794 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.996532 # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements 869835 # number of replacements
+system.cpu0.icache.tags.tagsinuse 510.810026 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 128546541 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 870347 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 147.695736 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 147420125000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 125.953257 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst 137.567270 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst 247.289498 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.246002 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst 0.268686 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst 0.482987 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.997676 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 250 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id
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-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15072.458106 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14453.910270 # average SoftPFReq mshr miss latency
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-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17533.020659 # average overall mshr miss latency
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-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16741.448211 # average overall mshr miss latency
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+system.cpu0.dcache.overall_mshr_hits::total 387337 # number of overall MSHR hits
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+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.061209 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084010 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045295 # mshr miss rate for ReadReq accesses
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+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031937 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018640 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.862400 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.842514 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.545962 # mshr miss rate for SoftPFReq accesses
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+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.063972 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.034738 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065711 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.084391 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.045740 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11810.286560 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14263.787110 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13540.083936 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32259.387031 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33496.144849 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33027.559834 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13258.729101 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15436.668492 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14794.396908 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17074.737561 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17958.421554 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17682.002602 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16136.757886 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17298.147148 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16940.202896 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.numCycles 2606024060 # number of cpu cycles simulated
+system.cpu1.numCycles 2604021576 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 35944624 # Number of instructions committed
-system.cpu1.committedOps 69816061 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 64937038 # Number of integer alu accesses
+system.cpu1.committedInsts 35901808 # Number of instructions committed
+system.cpu1.committedOps 69778761 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 64893692 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu1.num_func_calls 484528 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 6597164 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 64937038 # number of integer instructions
+system.cpu1.num_func_calls 487874 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 6598396 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 64893692 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
-system.cpu1.num_int_register_reads 120144832 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 55989327 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 119938204 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 55974127 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 36928761 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 27400948 # number of times the CC registers were written
-system.cpu1.num_mem_refs 4904439 # number of memory refs
-system.cpu1.num_load_insts 3100845 # Number of load instructions
-system.cpu1.num_store_insts 1803594 # Number of store instructions
-system.cpu1.num_idle_cycles 2475176569.081452 # Number of idle cycles
-system.cpu1.num_busy_cycles 130847490.918548 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.050210 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.949790 # Percentage of idle cycles
-system.cpu1.Branches 7263647 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 35052 0.05% 0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu 64819822 92.84% 92.89% # Class of executed instruction
-system.cpu1.op_class::IntMult 29822 0.04% 92.94% # Class of executed instruction
-system.cpu1.op_class::IntDiv 27277 0.04% 92.98% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 92.98% # Class of executed instruction
-system.cpu1.op_class::MemRead 3100845 4.44% 97.42% # Class of executed instruction
-system.cpu1.op_class::MemWrite 1803594 2.58% 100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads 36929560 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 27415142 # number of times the CC registers were written
+system.cpu1.num_mem_refs 4838216 # number of memory refs
+system.cpu1.num_load_insts 3070311 # Number of load instructions
+system.cpu1.num_store_insts 1767905 # Number of store instructions
+system.cpu1.num_idle_cycles 2474835372.874957 # Number of idle cycles
+system.cpu1.num_busy_cycles 129186203.125043 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.049610 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.950390 # Percentage of idle cycles
+system.cpu1.Branches 7267731 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 34873 0.05% 0.05% # Class of executed instruction
+system.cpu1.op_class::IntAlu 64849393 92.94% 92.99% # Class of executed instruction
+system.cpu1.op_class::IntMult 30804 0.04% 93.03% # Class of executed instruction
+system.cpu1.op_class::IntDiv 25762 0.04% 93.07% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.07% # Class of executed instruction
+system.cpu1.op_class::MemRead 3070311 4.40% 97.47% # Class of executed instruction
+system.cpu1.op_class::MemWrite 1767905 2.53% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 69816412 # Class of executed instruction
+system.cpu1.op_class::total 69779048 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.branchPred.lookups 29512659 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 29512659 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 322904 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 26886254 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 26249300 # Number of BTB hits
+system.cpu2.branchPred.lookups 29537500 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 29537500 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 323734 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 26929505 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 26224950 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 97.630931 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 591365 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 64668 # Number of incorrect RAS predictions.
-system.cpu2.numCycles 155365551 # number of cpu cycles simulated
+system.cpu2.branchPred.BTBHitPct 97.383706 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 595117 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 63666 # Number of incorrect RAS predictions.
+system.cpu2.numCycles 155672620 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 10587640 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 145508462 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 29512659 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 26840665 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 143230873 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 673912 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles 95091 # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles 7931 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 8903 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 52631 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 2801 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 311 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 3432374 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 167414 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes 3341 # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples 154322486 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.857387 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 3.033367 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles 10607285 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 145694636 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 29537500 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 26820067 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 143529975 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 676631 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles 97153 # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles 5039 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 8049 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 56841 # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles 4424 # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles 421 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 3472431 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 167012 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes 3661 # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples 154646852 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.855079 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 3.032629 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 98410042 63.77% 63.77% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 833989 0.54% 64.31% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 24035117 15.57% 79.88% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 597750 0.39% 80.27% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 798628 0.52% 80.79% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 859445 0.56% 81.35% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 568143 0.37% 81.71% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 716402 0.46% 82.18% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 27502970 17.82% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 98720699 63.84% 63.84% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 840447 0.54% 64.38% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 23990695 15.51% 79.89% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 599923 0.39% 80.28% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 812589 0.53% 80.81% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 861055 0.56% 81.36% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 574182 0.37% 81.73% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 718315 0.46% 82.20% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 27528947 17.80% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 154322486 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.189956 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 0.936556 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 10280285 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 95091051 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 22517334 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 5911995 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 337607 # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts 283677190 # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles 337607 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 12887048 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 76613528 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 4915145 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 25582017 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 13802994 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 282449598 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 208301 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 6363616 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents 49211 # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents 4861555 # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands 337331977 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 615247721 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 378014471 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 38 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 325050122 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 12281853 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 158846 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 160455 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 28628976 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 6469632 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 3638513 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 420201 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 343826 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 280493266 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 428842 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 278404006 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 102314 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 8748691 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 13528194 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 64074 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 154322486 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.804040 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 2.401684 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 154646852 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.189741 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 0.935904 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 10277789 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 95381782 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 22559618 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 5904125 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 338966 # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts 283871353 # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles 338966 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 12885148 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 76664692 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 4829048 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 25619792 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 14124701 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 282624473 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 211024 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 6375709 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents 73879 # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents 5159969 # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands 337473501 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 616062521 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 378507156 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 50 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 325128635 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 12344864 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 162095 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 163797 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 28599466 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 6606628 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 3716011 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 425441 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 346966 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 280674873 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 430305 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 278581977 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 102725 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 8814114 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 13599788 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 65362 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 154646852 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.801407 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 2.400759 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 91177599 59.08% 59.08% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 5361636 3.47% 62.56% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 3887403 2.52% 65.08% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 4108764 2.66% 67.74% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 21799190 14.13% 81.86% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 3056480 1.98% 83.84% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 24267786 15.73% 99.57% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 453628 0.29% 99.86% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 210000 0.14% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 91425932 59.12% 59.12% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 5392264 3.49% 62.61% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 3912324 2.53% 65.14% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 4126244 2.67% 67.80% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 21795400 14.09% 81.90% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 3071037 1.99% 83.88% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 24235245 15.67% 99.55% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 469170 0.30% 99.86% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 219236 0.14% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 154322486 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 154646852 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 2321368 89.34% 89.34% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 246 0.01% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 89.35% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 217075 8.35% 97.70% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 59662 2.30% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 2310389 89.01% 89.01% # attempts to use FU when none available
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+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 89.02% # attempts to use FU when none available
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+system.cpu2.iq.fu_full::SimdMult 0 0.00% 89.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 89.02% # attempts to use FU when none available
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+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 89.02% # attempts to use FU when none available
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+system.cpu2.iq.fu_full::MemRead 223101 8.59% 97.61% # attempts to use FU when none available
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system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass 72561 0.03% 0.03% # Type of FU issued
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-system.cpu2.iq.FU_type_0::IntMult 57882 0.02% 96.34% # Type of FU issued
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-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.36% # Type of FU issued
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-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.36% # Type of FU issued
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-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.36% # Type of FU issued
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-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.36% # Type of FU issued
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-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 6794594 2.44% 98.80% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 3348237 1.20% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass 76436 0.03% 0.03% # Type of FU issued
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+system.cpu2.iq.FU_type_0::IntMult 58746 0.02% 96.26% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 49744 0.02% 96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.28% # Type of FU issued
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+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.28% # Type of FU issued
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+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.28% # Type of FU issued
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+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.28% # Type of FU issued
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+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.28% # Type of FU issued
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+system.cpu2.iq.FU_type_0::MemWrite 3422443 1.23% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 278404006 # Type of FU issued
-system.cpu2.iq.rate 1.791929 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 2598351 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.009333 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 713831099 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 289675272 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 276815941 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 63 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes
+system.cpu2.iq.FU_type_0::total 278581977 # Type of FU issued
+system.cpu2.iq.rate 1.789537 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 2595740 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.009318 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 714509188 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 289923619 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 276984093 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 82 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 18 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 280929766 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 30 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 708692 # Number of loads that had data forwarded from stores
+system.cpu2.iq.int_alu_accesses 281101244 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 37 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 733638 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 1202973 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 6613 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 5162 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 660777 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 1227908 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 6601 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 5025 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 667461 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 754641 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 21520 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads 754863 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 24022 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 337607 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 71713264 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 1590839 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 280922108 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 41019 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 6469632 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 3638513 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 247100 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 199459 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 1088059 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 5162 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 186556 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 187873 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 374429 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 277824668 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 6659327 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 530499 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles 338966 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 71689555 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 1628683 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 281105178 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 39439 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 6606628 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 3716011 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 250069 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 194031 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 1131651 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 5025 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 186633 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 188127 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 374760 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 278001109 # Number of executed instructions
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+system.cpu2.iew.iewExecSquashedInsts 530943 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 0 # number of nop insts executed
-system.cpu2.iew.exec_refs 9922055 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 28210243 # Number of branches executed
-system.cpu2.iew.exec_stores 3262728 # Number of stores executed
-system.cpu2.iew.exec_rate 1.788200 # Inst execution rate
-system.cpu2.iew.wb_sent 277637651 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 276815959 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 215923076 # num instructions producing a value
-system.cpu2.iew.wb_consumers 354065892 # num instructions consuming a value
+system.cpu2.iew.exec_refs 10133053 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 28226522 # Number of branches executed
+system.cpu2.iew.exec_stores 3337738 # Number of stores executed
+system.cpu2.iew.exec_rate 1.785806 # Inst execution rate
+system.cpu2.iew.wb_sent 277806882 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 276984111 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 215977189 # num instructions producing a value
+system.cpu2.iew.wb_consumers 354208085 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 1.781707 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.609839 # average fanout of values written-back
+system.cpu2.iew.wb_rate 1.779273 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.609747 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 9085200 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 364768 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 325355 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 152966387 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.777091 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 2.654040 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 9156375 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 364943 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 326343 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 153280377 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.774187 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 2.653000 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 95002675 62.11% 62.11% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 4175839 2.73% 64.84% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1266091 0.83% 65.66% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 24954040 16.31% 81.98% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 981729 0.64% 82.62% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 650164 0.43% 83.04% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 435006 0.28% 83.33% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 23529501 15.38% 98.71% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 1971342 1.29% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 95267512 62.15% 62.15% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 4211429 2.75% 64.90% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1288351 0.84% 65.74% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 24928908 16.26% 82.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 992667 0.65% 82.65% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 656859 0.43% 83.08% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 436979 0.29% 83.37% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 23484943 15.32% 98.69% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 2012729 1.31% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 152966387 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 137677652 # Number of instructions committed
-system.cpu2.commit.committedOps 271835156 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 153280377 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 137795324 # Number of instructions committed
+system.cpu2.commit.committedOps 271948125 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 8244394 # Number of memory references committed
-system.cpu2.commit.loads 5266658 # Number of loads committed
-system.cpu2.commit.membars 166791 # Number of memory barriers committed
-system.cpu2.commit.branches 27802655 # Number of branches committed
+system.cpu2.commit.refs 8427269 # Number of memory references committed
+system.cpu2.commit.loads 5378719 # Number of loads committed
+system.cpu2.commit.membars 165391 # Number of memory barriers committed
+system.cpu2.commit.branches 27813078 # Number of branches committed
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 248203210 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 440588 # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass 43200 0.02% 0.02% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu 263446464 96.91% 96.93% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult 55564 0.02% 96.95% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv 45534 0.02% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead 5266658 1.94% 98.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite 2977736 1.10% 100.00% # Class of committed instruction
+system.cpu2.commit.int_insts 248363308 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 444774 # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass 44974 0.02% 0.02% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu 263371453 96.85% 96.86% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult 56553 0.02% 96.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv 47876 0.02% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead 5378719 1.98% 98.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite 3048550 1.12% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total 271835156 # Class of committed instruction
-system.cpu2.commit.bw_lim_events 1971342 # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total 271948125 # Class of committed instruction
+system.cpu2.commit.bw_lim_events 2012729 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 431889681 # The number of ROB reads
-system.cpu2.rob.rob_writes 563202973 # The number of ROB writes
-system.cpu2.timesIdled 114782 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 1043065 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 4908353341 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 137677652 # Number of Instructions Simulated
-system.cpu2.committedOps 271835156 # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi 1.128473 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 1.128473 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.886153 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.886153 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 369541594 # number of integer regfile reads
-system.cpu2.int_regfile_writes 221773447 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 72930 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes
-system.cpu2.cc_regfile_reads 140769340 # number of cc regfile reads
-system.cpu2.cc_regfile_writes 108468562 # number of cc regfile writes
-system.cpu2.misc_regfile_reads 90221682 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 135530 # number of misc regfile writes
+system.cpu2.rob.rob_reads 432344700 # The number of ROB reads
+system.cpu2.rob.rob_writes 563581737 # The number of ROB writes
+system.cpu2.timesIdled 114304 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 1025768 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 4904031691 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 137795324 # Number of Instructions Simulated
+system.cpu2.committedOps 271948125 # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi 1.129738 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 1.129738 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.885161 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.885161 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 370036745 # number of integer regfile reads
+system.cpu2.int_regfile_writes 221903617 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 72874 # number of floating regfile reads
+system.cpu2.fp_regfile_writes 72912 # number of floating regfile writes
+system.cpu2.cc_regfile_reads 140867740 # number of cc regfile reads
+system.cpu2.cc_regfile_writes 108480868 # number of cc regfile writes
+system.cpu2.misc_regfile_reads 90412070 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 138782 # number of misc regfile writes
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
sim_ticks 61144411500 # Number of ticks simulated
final_tick 61144411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 253751 # Simulator instruction rate (inst/s)
-host_op_rate 255015 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 171247115 # Simulator tick rate (ticks/s)
-host_mem_usage 451144 # Number of bytes of host memory used
-host_seconds 357.05 # Real time elapsed on the host
+host_inst_rate 269135 # Simulator instruction rate (inst/s)
+host_op_rate 270476 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 181629122 # Simulator tick rate (ticks/s)
+host_mem_usage 440052 # Number of bytes of host memory used
+host_seconds 336.64 # Real time elapsed on the host
sim_insts 90602849 # Number of instructions simulated
sim_ops 91054080 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bytesPerActivate::896-1023 28 1.83% 54.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 704 45.98% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1531 # Bytes accessed per row activation
-system.physmem.totQLat 71444000 # Total ticks spent queuing
-system.physmem.totMemAccLat 363456500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 71490500 # Total ticks spent queuing
+system.physmem.totMemAccLat 363503000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 4587.39 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 4590.37 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 23337.39 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 23340.37 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 16.30 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 16.30 # Average system read bandwidth in MiByte/s
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 3193563500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 16301343 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 1030 # Transaction distribution
system.membus.trans_dist::ReadResp 1030 # Transaction distribution
system.membus.trans_dist::ReadExReq 14544 # Transaction distribution
system.membus.trans_dist::ReadExResp 14544 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 996736 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 21821000 # Layer occupancy (ticks)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 15574 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 15574 # Request fanout histogram
+system.membus.reqLayer0.occupancy 21822000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 149563500 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 149565000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 20748985 # Number of BP lookups
-system.cpu.branchPred.condPredicted 17053333 # Number of conditional branches predicted
+system.cpu.branchPred.lookups 20748984 # Number of BP lookups
+system.cpu.branchPred.condPredicted 17053332 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 764055 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 8969348 # Number of BTB lookups
system.cpu.branchPred.BTBHits 8846034 # Number of BTB hits
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.349724 # CPI: cycles per instruction
system.cpu.ipc 0.740892 # IPC: instructions per cycle
-system.cpu.tickCycles 109176310 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 13112513 # Total number of cycles that the object has spent stopped
+system.cpu.tickCycles 109176308 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 13112515 # Total number of cycles that the object has spent stopped
system.cpu.icache.tags.replacements 5 # number of replacements
-system.cpu.icache.tags.tagsinuse 690.927528 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 27773576 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 690.927522 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 27773574 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 34587.267746 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 34587.265255 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 690.927528 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst 690.927522 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.337367 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.337367 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 55549561 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 55549561 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 27773576 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 27773576 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 27773576 # number of demand (read+write) hits
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-system.cpu.icache.overall_hits::total 27773576 # number of overall hits
+system.cpu.icache.tags.tag_accesses 55549557 # Number of tag accesses
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+system.cpu.icache.overall_hits::total 27773574 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses
system.cpu.icache.overall_misses::total 803 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 55308998 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 55308998 # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::total 55308998 # number of demand (read+write) miss cycles
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-system.cpu.icache.overall_miss_latency::total 55308998 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 27774379 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 27774379 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 27774379 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 27774379 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 27774379 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 27774379 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 55313498 # number of ReadReq miss cycles
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+system.cpu.icache.demand_miss_latency::total 55313498 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 55313498 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 55313498 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 27774377 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 27774377 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 27774377 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 27774377 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 27774377 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 27774377 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68877.955168 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 68877.955168 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 68877.955168 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 68877.955168 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 68877.955168 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 68877.955168 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68883.559153 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 68883.559153 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 68883.559153 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 68883.559153 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 68883.559153 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 68883.559153 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53368002 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 53368002 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53368002 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 53368002 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53368002 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 53368002 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53373502 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 53373502 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53373502 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 53373502 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53373502 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 53373502 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
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-system.cpu.toL2Bus.throughput 1982677223 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 904183 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 904183 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 943269 # Transaction distribution
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-system.cpu.toL2Bus.tot_pkt_size::total 121229632 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 121229632 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.cpu.toL2Bus.reqLayer0.occupancy 1890375500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
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-system.cpu.l2cache.tags.tagsinuse 10264.635484 # Cycle average of tags in use
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system.cpu.l2cache.tags.total_refs 1831263 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 117.713119 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 9373.658869 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.976615 # Average occupied blocks per requestor
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system.cpu.l2cache.ReadReq_accesses::total 904183 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 943269 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001139 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001139 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.311028 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 946045 # number of replacements
system.cpu.dcache.tags.tagsinuse 3618.157159 # Cycle average of tags in use
system.cpu.dcache.overall_misses::total 988793 # number of overall misses
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system.cpu.dcache.ReadReq_accesses::cpu.inst 22511647 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.297569 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.297569 # average ReadReq miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.040129 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040129 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.406823 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.406823 # average ReadReq mshr miss latency
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.026367 # Number of seconds simulated
-sim_ticks 26367385000 # Number of ticks simulated
-final_tick 26367385000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.057713 # Number of seconds simulated
+sim_ticks 57712782000 # Number of ticks simulated
+final_tick 57712782000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 125019 # Simulator instruction rate (inst/s)
-host_op_rate 125641 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 36388385 # Simulator tick rate (ticks/s)
-host_mem_usage 387112 # Number of bytes of host memory used
-host_seconds 724.61 # Real time elapsed on the host
+host_inst_rate 133015 # Simulator instruction rate (inst/s)
+host_op_rate 133677 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 84740771 # Simulator tick rate (ticks/s)
+host_mem_usage 440040 # Number of bytes of host memory used
+host_seconds 681.05 # Real time elapsed on the host
sim_insts 90589798 # Number of instructions simulated
sim_ops 91041029 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 44608 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 947840 # Number of bytes read from this memory
-system.physmem.bytes_read::total 992448 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 44608 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 44608 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 697 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 14810 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15507 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1691787 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 35947440 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 37639227 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1691787 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1691787 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1691787 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 35947440 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 37639227 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15507 # Number of read requests accepted
-system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 15507 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 992448 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 992448 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 989 # Per bank write bursts
-system.physmem.perBankRdBursts::1 884 # Per bank write bursts
-system.physmem.perBankRdBursts::2 939 # Per bank write bursts
-system.physmem.perBankRdBursts::3 1031 # Per bank write bursts
-system.physmem.perBankRdBursts::4 1047 # Per bank write bursts
-system.physmem.perBankRdBursts::5 1105 # Per bank write bursts
-system.physmem.perBankRdBursts::6 1078 # Per bank write bursts
-system.physmem.perBankRdBursts::7 1078 # Per bank write bursts
-system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
-system.physmem.perBankRdBursts::9 961 # Per bank write bursts
-system.physmem.perBankRdBursts::10 931 # Per bank write bursts
-system.physmem.perBankRdBursts::11 899 # Per bank write bursts
-system.physmem.perBankRdBursts::12 906 # Per bank write bursts
-system.physmem.perBankRdBursts::13 864 # Per bank write bursts
-system.physmem.perBankRdBursts::14 875 # Per bank write bursts
-system.physmem.perBankRdBursts::15 896 # Per bank write bursts
-system.physmem.perBankWrBursts::0 0 # Per bank write bursts
+system.physmem.bytes_read::cpu.inst 8896 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 68416 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher 1042048 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1119360 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 8896 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 8896 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 73600 # Number of bytes written to this memory
+system.physmem.bytes_written::total 73600 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 139 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1069 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher 16282 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 17490 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1150 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1150 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 154143 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1185457 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher 18055758 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 19395357 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 154143 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 154143 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1275281 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1275281 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1275281 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 154143 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1185457 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher 18055758 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 20670638 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 17490 # Number of read requests accepted
+system.physmem.writeReqs 1150 # Number of write requests accepted
+system.physmem.readBursts 17490 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1150 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 1100032 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue
+system.physmem.bytesWritten 71488 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 1119360 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 73600 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 1094 # Per bank write bursts
+system.physmem.perBankRdBursts::1 953 # Per bank write bursts
+system.physmem.perBankRdBursts::2 1083 # Per bank write bursts
+system.physmem.perBankRdBursts::3 1113 # Per bank write bursts
+system.physmem.perBankRdBursts::4 1125 # Per bank write bursts
+system.physmem.perBankRdBursts::5 1235 # Per bank write bursts
+system.physmem.perBankRdBursts::6 1314 # Per bank write bursts
+system.physmem.perBankRdBursts::7 1243 # Per bank write bursts
+system.physmem.perBankRdBursts::8 1060 # Per bank write bursts
+system.physmem.perBankRdBursts::9 962 # Per bank write bursts
+system.physmem.perBankRdBursts::10 1021 # Per bank write bursts
+system.physmem.perBankRdBursts::11 923 # Per bank write bursts
+system.physmem.perBankRdBursts::12 921 # Per bank write bursts
+system.physmem.perBankRdBursts::13 987 # Per bank write bursts
+system.physmem.perBankRdBursts::14 1105 # Per bank write bursts
+system.physmem.perBankRdBursts::15 1049 # Per bank write bursts
+system.physmem.perBankWrBursts::0 72 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
-system.physmem.perBankWrBursts::2 0 # Per bank write bursts
-system.physmem.perBankWrBursts::3 0 # Per bank write bursts
-system.physmem.perBankWrBursts::4 0 # Per bank write bursts
-system.physmem.perBankWrBursts::5 0 # Per bank write bursts
-system.physmem.perBankWrBursts::6 0 # Per bank write bursts
-system.physmem.perBankWrBursts::7 0 # Per bank write bursts
-system.physmem.perBankWrBursts::8 0 # Per bank write bursts
+system.physmem.perBankWrBursts::2 62 # Per bank write bursts
+system.physmem.perBankWrBursts::3 19 # Per bank write bursts
+system.physmem.perBankWrBursts::4 14 # Per bank write bursts
+system.physmem.perBankWrBursts::5 111 # Per bank write bursts
+system.physmem.perBankWrBursts::6 193 # Per bank write bursts
+system.physmem.perBankWrBursts::7 122 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
-system.physmem.perBankWrBursts::10 0 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 0 # Per bank write bursts
-system.physmem.perBankWrBursts::13 0 # Per bank write bursts
-system.physmem.perBankWrBursts::14 0 # Per bank write bursts
-system.physmem.perBankWrBursts::15 0 # Per bank write bursts
+system.physmem.perBankWrBursts::10 68 # Per bank write bursts
+system.physmem.perBankWrBursts::11 20 # Per bank write bursts
+system.physmem.perBankWrBursts::12 15 # Per bank write bursts
+system.physmem.perBankWrBursts::13 94 # Per bank write bursts
+system.physmem.perBankWrBursts::14 168 # Per bank write bursts
+system.physmem.perBankWrBursts::15 110 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 26367229500 # Total gap between requests
+system.physmem.totGap 57712604500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 15507 # Read request sizes (log2)
+system.physmem.readPktSize::6 17490 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 9831 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 5064 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 594 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1150 # Write request sizes (log2)
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+system.physmem.rdQLenPdf::1 2508 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::7 392 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::9 120 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::17 59 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 61 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::20 63 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 63 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 66 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 66 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 66 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 66 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 68 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 70 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 68 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 63 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 63 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 63 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1349 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 734.553002 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 545.014262 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 382.702300 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 137 10.16% 10.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 142 10.53% 20.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 57 4.23% 24.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 62 4.60% 29.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 68 5.04% 34.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 37 2.74% 37.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 30 2.22% 39.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 28 2.08% 41.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 788 58.41% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1349 # Bytes accessed per row activation
-system.physmem.totQLat 76352250 # Total ticks spent queuing
-system.physmem.totMemAccLat 367108500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 77535000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 4923.73 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 2975 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 393.336471 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 197.951950 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 413.488148 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 1360 45.71% 45.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 404 13.58% 59.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 131 4.40% 63.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 68 2.29% 65.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 81 2.72% 68.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 67 2.25% 70.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 54 1.82% 72.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 34 1.14% 73.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 776 26.08% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 2975 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 63 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 272.444444 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean 27.585882 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 1910.173610 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511 62 98.41% 98.41% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14848-15359 1 1.59% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 63 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 63 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.730159 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.698769 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.080716 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 12 19.05% 19.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 1 1.59% 20.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 46 73.02% 93.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 3 4.76% 98.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 1 1.59% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 63 # Writes before turning the bus around for reads
+system.physmem.totQLat 228948216 # Total ticks spent queuing
+system.physmem.totMemAccLat 551223216 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 85940000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 13320.24 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 23673.73 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 37.64 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 37.64 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 32070.24 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 19.06 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.24 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 19.40 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.28 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.29 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 14147 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 91.23 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 1700343.68 # Average gap between requests
-system.physmem.pageHitRate 91.23 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 23819655750 # Time in different power states
-system.physmem.memoryStateTime::REF 880360000 # Time in different power states
+system.physmem.busUtil 0.16 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.15 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 14.66 # Average write queue length when enqueuing
+system.physmem.readRowHits 14950 # Number of row buffer hits during reads
+system.physmem.writeRowHits 375 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 86.98 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 32.72 # Row buffer hit rate for writes
+system.physmem.avgGap 3096169.77 # Average gap between requests
+system.physmem.pageHitRate 83.59 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 51355249007 # Time in different power states
+system.physmem.memoryStateTime::REF 1927120000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 1664500500 # Time in different power states
+system.physmem.memoryStateTime::ACT 4429633993 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 37639227 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 969 # Transaction distribution
-system.membus.trans_dist::ReadResp 969 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 3 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 3 # Transaction distribution
-system.membus.trans_dist::ReadExReq 14538 # Transaction distribution
-system.membus.trans_dist::ReadExResp 14538 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31020 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 31020 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992448 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 992448 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 992448 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 18431500 # Layer occupancy (ticks)
+system.membus.trans_dist::ReadReq 17158 # Transaction distribution
+system.membus.trans_dist::ReadResp 17158 # Transaction distribution
+system.membus.trans_dist::Writeback 1150 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
+system.membus.trans_dist::ReadExReq 332 # Transaction distribution
+system.membus.trans_dist::ReadExResp 332 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 36134 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 36134 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1192960 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1192960 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 18642 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 18642 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 18642 # Request fanout histogram
+system.membus.reqLayer0.occupancy 32019899 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 144905497 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
+system.membus.respLayer1.occupancy 163550691 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 29708806 # Number of BP lookups
-system.cpu.branchPred.condPredicted 24486950 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 848073 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 12459505 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 12380967 # Number of BTB hits
+system.cpu.branchPred.lookups 28272297 # Number of BP lookups
+system.cpu.branchPred.condPredicted 23289786 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 837936 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 11858499 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 11790100 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 99.369654 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 77225 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 105 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 99.423207 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 75765 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
-system.cpu.numCycles 52734771 # number of cpu cycles simulated
+system.cpu.numCycles 115425565 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 15504828 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 141696019 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 29708806 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 12458192 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 36323119 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1712998 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 10 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 5 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 15157439 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 317484 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 52684513 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.702798 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.249702 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 745807 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 135034231 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 28272297 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 11865865 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 113822766 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1679444 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 53 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.IcacheWaitRetryStallCycles 259 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 32316581 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 456 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 115408607 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.175345 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.320714 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 25447326 48.30% 48.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3927834 7.46% 55.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2643597 5.02% 60.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1975703 3.75% 64.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2124397 4.03% 68.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2942984 5.59% 74.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1825722 3.47% 77.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1288988 2.45% 80.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 10507962 19.95% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 57851940 50.13% 50.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 13925142 12.07% 62.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 9174755 7.95% 70.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 34456770 29.86% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 52684513 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.563363 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.686956 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 11541183 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 18148303 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 18363246 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3783966 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 847815 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 4787740 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 8797 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 133953704 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 39951 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 847815 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 13130783 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 7261973 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 198650 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 20259912 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 10985380 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 130534992 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 3194 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 4661957 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 5208173 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 864876 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 151632066 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 568616751 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 140291234 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 824 # Number of floating rename lookups
+system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 115408607 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.244940 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.169881 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 8865132 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 63135589 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 33034927 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 9545475 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 827484 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 4101291 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 12346 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 114392929 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 1987160 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 827484 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 15218972 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 49233807 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 108012 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 35472939 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 14547393 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 110855235 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 1413432 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 11041669 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1056479 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 1457795 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 455993 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 129914313 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 483072528 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 119436601 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 420 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 44319147 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 4700 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 4700 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 18678634 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 31297749 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 5707560 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 2464961 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1558957 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 125335435 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 8504 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 107771373 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 19311 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 34045700 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 86545264 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 286 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 52684513 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.045599 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.948200 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 22601394 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 4364 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 21215231 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 26814209 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 5348913 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 553765 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 291016 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 109685133 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 101428277 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1059458 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 18454529 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 41507183 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 115408607 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.878862 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.000028 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 15278150 29.00% 29.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 10252049 19.46% 48.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 8069131 15.32% 63.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6193349 11.76% 75.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 6619102 12.56% 88.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3132844 5.95% 94.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1926333 3.66% 97.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 606051 1.15% 98.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 607504 1.15% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 54542432 47.26% 47.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 30109521 26.09% 73.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 22147517 19.19% 92.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7413143 6.42% 98.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 1195677 1.04% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 317 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 52684513 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 115408607 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 313366 33.84% 33.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 27 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 287772 31.08% 64.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 324774 35.08% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 9750275 48.86% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 50 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 9493870 47.57% 96.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 712253 3.57% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 76600270 71.08% 71.08% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 10764 0.01% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 144 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 193 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 20 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 25964378 24.09% 95.18% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 5195603 4.82% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 71987588 70.97% 70.97% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 10708 0.01% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 56 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 125 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.98% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 24380841 24.04% 95.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 5048955 4.98% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 107771373 # Type of FU issued
-system.cpu.iq.rate 2.043649 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 925939 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.008592 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 269171739 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 159396970 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 104914190 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 770 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1077 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 346 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 108696926 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 386 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 461125 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 101428277 # Type of FU issued
+system.cpu.iq.rate 0.878733 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 19956461 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.196754 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 339280619 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 128148692 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 99657487 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 461 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 607 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 120 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 121384498 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 285190 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 8821838 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 5647 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 8949 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 962716 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4338298 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 1479 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 1420 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 604069 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 15326 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 231326 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 7565 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 130354 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 847815 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 5127616 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 500104 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 125356607 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 320162 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 31297749 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 5707560 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 4616 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 66442 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 385113 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 8949 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 454051 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 452935 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 906986 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 106740965 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25734173 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1030408 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 827484 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 8008710 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 730406 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 109706046 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 26814209 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 5348913 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 187279 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 360662 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 1420 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 436360 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 412881 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 849241 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 100145631 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 23824107 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1282646 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 12668 # number of nop insts executed
-system.cpu.iew.exec_refs 30844738 # number of memory reference insts executed
-system.cpu.iew.exec_branches 21924000 # Number of branches executed
-system.cpu.iew.exec_stores 5110565 # Number of stores executed
-system.cpu.iew.exec_rate 2.024110 # Inst execution rate
-system.cpu.iew.wb_sent 105227967 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 104914536 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 63175597 # num instructions producing a value
-system.cpu.iew.wb_consumers 106448562 # num instructions consuming a value
+system.cpu.iew.exec_nop 12666 # number of nop insts executed
+system.cpu.iew.exec_refs 28742996 # number of memory reference insts executed
+system.cpu.iew.exec_branches 20629033 # Number of branches executed
+system.cpu.iew.exec_stores 4918889 # Number of stores executed
+system.cpu.iew.exec_rate 0.867621 # Inst execution rate
+system.cpu.iew.wb_sent 99755826 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 99657607 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 59710820 # num instructions producing a value
+system.cpu.iew.wb_consumers 95563157 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.989476 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.593485 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.863393 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.624831 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 34317785 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 17390640 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 839389 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 47813008 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.904370 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.590937 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 825698 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 112714742 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.807824 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.745908 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 19048029 39.84% 39.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 12579538 26.31% 66.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4065916 8.50% 74.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 3224325 6.74% 81.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1531590 3.20% 84.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 701376 1.47% 86.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1004304 2.10% 88.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 253211 0.53% 88.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5404719 11.30% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 76462569 67.84% 67.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 18443635 16.36% 84.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 7118441 6.32% 90.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 3374531 2.99% 93.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1758227 1.56% 95.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 536893 0.48% 95.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 726177 0.64% 96.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 179059 0.16% 96.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 4115210 3.65% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 47813008 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 112714742 # Number of insts commited each cycle
system.cpu.commit.committedInsts 90602407 # Number of instructions committed
system.cpu.commit.committedOps 91053638 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction
-system.cpu.commit.bw_lim_events 5404719 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 4115210 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 167773978 # The number of ROB reads
-system.cpu.rob.rob_writes 255639290 # The number of ROB writes
-system.cpu.timesIdled 522 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 50258 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 217038076 # The number of ROB reads
+system.cpu.rob.rob_writes 219583064 # The number of ROB writes
+system.cpu.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 16958 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 90589798 # Number of Instructions Simulated
system.cpu.committedOps 91041029 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.582127 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.582127 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.717838 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.717838 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 115515398 # number of integer regfile reads
-system.cpu.int_regfile_writes 62074294 # number of integer regfile writes
-system.cpu.fp_regfile_reads 287 # number of floating regfile reads
-system.cpu.fp_regfile_writes 460 # number of floating regfile writes
-system.cpu.cc_regfile_reads 391234324 # number of cc regfile reads
-system.cpu.cc_regfile_writes 61185455 # number of cc regfile writes
-system.cpu.misc_regfile_reads 29410043 # number of misc regfile reads
+system.cpu.cpi 1.274156 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.274156 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.784833 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.784833 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 108123919 # number of integer regfile reads
+system.cpu.int_regfile_writes 58738896 # number of integer regfile writes
+system.cpu.fp_regfile_reads 58 # number of floating regfile reads
+system.cpu.fp_regfile_writes 100 # number of floating regfile writes
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+system.cpu.cc_regfile_writes 58698459 # number of cc regfile writes
+system.cpu.misc_regfile_reads 28460470 # number of misc regfile reads
system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 4590653188 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 911002 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 911001 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 942911 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 37393 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 37393 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1448 # Packet count per connected master and slave (bytes)
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-system.cpu.toL2Bus.pkt_count::total 2839705 # Packet count per connected master and slave (bytes)
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-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120997056 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 121043200 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 121043200 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 320 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 1888566500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 7.2 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1205249 # Layer occupancy (ticks)
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+system.cpu.toL2Bus.pkt_size::total 697270080 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 28370 # Total snoops (count)
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+system.cpu.toL2Bus.snoop_fanout::mean 5.002597 # Request fanout histogram
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+system.cpu.toL2Bus.snoop_fanout::total 10923218 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 10854591744 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks)
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system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
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-system.cpu.toL2Bus.respLayer1.utilization 5.4 # Layer utilization (%)
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-system.cpu.icache.tags.tagsinuse 624.324849 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 15156433 # Total number of references to valid blocks.
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system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.icache.ReadReq_miss_latency::total 68127998 # number of ReadReq miss cycles
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-system.cpu.icache.demand_avg_miss_latency::total 67721.667992 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 67721.667992 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 67721.667992 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 475 # number of cycles access was blocked
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+system.cpu.icache.ReadReq_accesses::cpu.inst 32316579 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.icache.overall_mshr_hits::total 279 # number of overall MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses::total 727 # number of ReadReq MSHR misses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69398.211829 # average ReadReq mshr miss latency
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-system.cpu.icache.demand_avg_mshr_miss_latency::total 69398.211829 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69398.211829 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 69398.211829 # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19487.706332 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 19487.706332 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 10760.665120 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 1837803 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 15490 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 118.644480 # Average number of references to valid blocks.
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+system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 13933 # number of hwpf that were already in mshr
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+system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 738007 # number of hwpf that were already in the prefetch queue
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+system.cpu.l2cache.tags.replacements 1672 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 12558.688532 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 10641390 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 17530 # Sample count of references to valid blocks.
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.dcache.ReadReq_avg_miss_latency::total 9073.389719 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10479.564718 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 10479.564718 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20232.142857 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20232.142857 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 9126.652876 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 9126.652876 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 9126.645552 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 9126.645552 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 301384 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 67125 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 120500 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 12183 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.501112 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 5.509727 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 942911 # number of writebacks
-system.cpu.dcache.writebacks::total 942911 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 274687 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 274687 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 139679 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 139679 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 414366 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 414366 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 414366 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 414366 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 910261 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 910261 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 37392 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 37392 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 20 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 20 # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 947653 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 947653 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 947673 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 947673 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10074295509 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 10074295509 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1254962842 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1254962842 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1219250 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1219250 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11329258351 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 11329258351 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11330477601 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 11330477601 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036412 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036412 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007897 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007897 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.029985 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.029985 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031871 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.031871 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031871 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.031871 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11067.480106 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11067.480106 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33562.335312 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33562.335312 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 60962.500000 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 60962.500000 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11955.070422 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11955.070422 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11956.104691 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11956.104691 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 5407164 # number of writebacks
+system.cpu.dcache.writebacks::total 5407164 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4328464 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 4328464 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154855 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 154855 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 4483319 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 4483319 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 4483319 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 4483319 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5263966 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 5263966 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222792 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 222792 # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 5 # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 5486758 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 5486758 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 5486763 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 5486763 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38232328002 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 38232328002 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2158774283 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2158774283 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 284500 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 284500 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40391102285 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 40391102285 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40391386785 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 40391386785 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.224016 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.224016 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047052 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047052 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.009434 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.009434 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.194338 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.194338 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.194334 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.194334 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7263.027155 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7263.027155 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9689.640036 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9689.640036 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56900 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56900 # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7361.560740 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 7361.560740 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7361.605884 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 7361.605884 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 54141000000 # Number of ticks simulated
final_tick 54141000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1737374 # Simulator instruction rate (inst/s)
-host_op_rate 1746027 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1038196846 # Simulator tick rate (ticks/s)
-host_mem_usage 439336 # Number of bytes of host memory used
-host_seconds 52.15 # Real time elapsed on the host
+host_inst_rate 2068738 # Simulator instruction rate (inst/s)
+host_op_rate 2079040 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1236208278 # Simulator tick rate (ticks/s)
+host_mem_usage 428768 # Number of bytes of host memory used
+host_seconds 43.80 # Real time elapsed on the host
sim_insts 90602407 # Number of instructions simulated
sim_ops 91053638 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7966662603 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2011871521 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9978534124 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 9978534124 # Throughput (bytes/s)
-system.membus.data_through_bus 540247816 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 130287905 # Transaction distribution
+system.membus.trans_dist::ReadResp 130291792 # Transaction distribution
+system.membus.trans_dist::WriteReq 4734981 # Transaction distribution
+system.membus.trans_dist::WriteResp 4734981 # Transaction distribution
+system.membus.trans_dist::SoftPFReq 510 # Transaction distribution
+system.membus.trans_dist::SoftPFResp 510 # Transaction distribution
+system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution
+system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution
+system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661540 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 270062340 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323080 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 540247816 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 135031170 # Request fanout histogram
+system.membus.snoop_fanout::mean 4.798562 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::4 27200400 20.14% 20.14% # Request fanout histogram
+system.membus.snoop_fanout::5 107830770 79.86% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 4 # Request fanout histogram
+system.membus.snoop_fanout::max_value 5 # Request fanout histogram
+system.membus.snoop_fanout::total 135031170 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
sim_ticks 147041218000 # Number of ticks simulated
final_tick 147041218000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1067718 # Simulator instruction rate (inst/s)
-host_op_rate 1073024 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1733318334 # Simulator tick rate (ticks/s)
-host_mem_usage 449084 # Number of bytes of host memory used
-host_seconds 84.83 # Real time elapsed on the host
+host_inst_rate 1130471 # Simulator instruction rate (inst/s)
+host_op_rate 1136089 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1835190843 # Simulator tick rate (ticks/s)
+host_mem_usage 438268 # Number of bytes of host memory used
+host_seconds 80.12 # Real time elapsed on the host
sim_insts 90576861 # Number of instructions simulated
sim_ops 91026990 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 251576 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 6425192 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6676767 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 6676767 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 792 # Transaction distribution
system.membus.trans_dist::ReadResp 792 # Transaction distribution
system.membus.trans_dist::ReadExReq 14548 # Transaction distribution
system.membus.trans_dist::ReadExResp 14548 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 981760 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 15340 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 15340 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 15340 # Request fanout histogram
system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 138323000 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11655.109643 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11655.109643 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 822509400 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 900788 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1198 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2835930 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2837128 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38336 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 120942784 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38336 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 1889731 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 1889731 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 1889731 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks)
sim_ticks 122215823500 # Number of ticks simulated
final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2362566 # Simulator instruction rate (inst/s)
-host_op_rate 2362664 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1184221154 # Simulator tick rate (ticks/s)
-host_mem_usage 397240 # Number of bytes of host memory used
-host_seconds 103.20 # Real time elapsed on the host
+host_inst_rate 2069444 # Simulator instruction rate (inst/s)
+host_op_rate 2069529 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1037295392 # Simulator tick rate (ticks/s)
+host_mem_usage 412436 # Number of bytes of host memory used
+host_seconds 117.82 # Real time elapsed on the host
sim_insts 243825150 # Number of instructions simulated
sim_ops 243835265 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3438835373 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11438503207 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 11438757576 # Throughput (bytes/s)
-system.membus.data_through_bus 1397997177 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 326641931 # Transaction distribution
+system.membus.trans_dist::ReadResp 326641931 # Transaction distribution
+system.membus.trans_dist::WriteReq 22901951 # Transaction distribution
+system.membus.trans_dist::WriteResp 22901951 # Transaction distribution
+system.membus.trans_dist::SwapReq 3886 # Transaction distribution
+system.membus.trans_dist::SwapResp 3886 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 488842996 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 210252540 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 699095536 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 977685992 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 420311185 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1397997177 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 349547768 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.699251 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.458584 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 105126270 30.07% 30.07% # Request fanout histogram
+system.membus.snoop_fanout::1 244421498 69.93% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 349547768 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 443 # Number of system calls
system.cpu.numCycles 244431648 # number of cpu cycles simulated
sim_ticks 361488530000 # Number of ticks simulated
final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1070091 # Simulator instruction rate (inst/s)
-host_op_rate 1070135 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1586487053 # Simulator tick rate (ticks/s)
-host_mem_usage 406976 # Number of bytes of host memory used
-host_seconds 227.85 # Real time elapsed on the host
+host_inst_rate 1379749 # Simulator instruction rate (inst/s)
+host_op_rate 1379806 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2045576865 # Simulator tick rate (ticks/s)
+host_mem_usage 421936 # Number of bytes of host memory used
+host_seconds 176.72 # Real time elapsed on the host
sim_insts 243825150 # Number of instructions simulated
sim_ops 243835265 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 2762444 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 1036 # Transaction distribution
system.membus.trans_dist::ReadResp 1036 # Transaction distribution
system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 998592 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 15603 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 15603 # Request fanout histogram
system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 140427000 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 332088036 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 893739 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1764 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814408 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2816172 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 120046016 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 1875719 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 1875719 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 1875719 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 1873125500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks)
sim_ticks 61857343500 # Number of ticks simulated
final_tick 61857343500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 85967 # Simulator instruction rate (inst/s)
-host_op_rate 151374 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 33658728 # Simulator tick rate (ticks/s)
-host_mem_usage 393056 # Number of bytes of host memory used
-host_seconds 1837.78 # Real time elapsed on the host
+host_inst_rate 115241 # Simulator instruction rate (inst/s)
+host_op_rate 202921 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 45120347 # Simulator tick rate (ticks/s)
+host_mem_usage 449832 # Number of bytes of host memory used
+host_seconds 1370.94 # Real time elapsed on the host
sim_insts 157988547 # Number of instructions simulated
sim_ops 278192464 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.wrPerTurnAround::18 7 70.00% 90.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 1 10.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 10 # Writes before turning the bus around for reads
-system.physmem.totQLat 130872750 # Total ticks spent queuing
-system.physmem.totMemAccLat 700329000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 131010750 # Total ticks spent queuing
+system.physmem.totMemAccLat 700467000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 151855000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 4309.14 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 4313.68 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 23059.14 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 23063.68 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 31.42 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.18 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 31.52 # Average system read bandwidth in MiByte/s
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 4171276250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 31718918 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 1465 # Transaction distribution
system.membus.trans_dist::ReadResp 1462 # Transaction distribution
system.membus.trans_dist::Writeback 197 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61120 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61120 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 61120 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1962048 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1962048 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 1962048 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 1962048 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1962048 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1962048 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1962048 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 30660 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 30660 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 30660 # Request fanout histogram
system.membus.reqLayer0.occupancy 43500000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 291787250 # Layer occupancy (ticks)
system.cpu.cc_regfile_writes 64568807 # number of cc regfile writes
system.cpu.misc_regfile_reads 196282104 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 4287758914 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 1995493 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 1995490 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 2066654 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2052 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219715 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 6221767 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65664 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265163712 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 265229376 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 265229376 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65664 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265163712 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 265229376 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 4144212 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 4144212 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 4144212 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4138760000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1710750 # Layer occupancy (ticks)
sim_ticks 168950040000 # Number of ticks simulated
final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1054637 # Simulator instruction rate (inst/s)
-host_op_rate 1857047 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1127809594 # Simulator tick rate (ticks/s)
-host_mem_usage 414920 # Number of bytes of host memory used
-host_seconds 149.80 # Real time elapsed on the host
+host_inst_rate 1180838 # Simulator instruction rate (inst/s)
+host_op_rate 2079266 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1262766288 # Simulator tick rate (ticks/s)
+host_mem_usage 436624 # Number of bytes of host memory used
+host_seconds 133.79 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
sim_ops 278192465 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 15992825110 # Throughput (bytes/s)
-system.membus.data_through_bus 2701988442 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 308475611 # Transaction distribution
+system.membus.trans_dist::ReadResp 308475611 # Transaction distribution
+system.membus.trans_dist::WriteReq 31439752 # Transaction distribution
+system.membus.trans_dist::WriteResp 31439752 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::total 435392328 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::total 244438398 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 679830726 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::total 1741569312 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::total 960419130 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 2701988442 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 339915363 # Request fanout histogram
+system.membus.snoop_fanout::mean 2.640442 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.479871 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::2 122219199 35.96% 35.96% # Request fanout histogram
+system.membus.snoop_fanout::3 217696164 64.04% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 2 # Request fanout histogram
+system.membus.snoop_fanout::max_value 3 # Request fanout histogram
+system.membus.snoop_fanout::total 339915363 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 444 # Number of system calls
sim_ticks 365989065000 # Number of ticks simulated
final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 596728 # Simulator instruction rate (inst/s)
-host_op_rate 1050742 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1382352440 # Simulator tick rate (ticks/s)
-host_mem_usage 424660 # Number of bytes of host memory used
-host_seconds 264.76 # Real time elapsed on the host
+host_inst_rate 756908 # Simulator instruction rate (inst/s)
+host_op_rate 1332794 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1753418925 # Simulator tick rate (ticks/s)
+host_mem_usage 446124 # Number of bytes of host memory used
+host_seconds 208.73 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
sim_ops 278192465 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 5272114 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 1025 # Transaction distribution
system.membus.trans_dist::ReadResp 1025 # Transaction distribution
system.membus.trans_dist::Writeback 100 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 1929536 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 30149 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 30149 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 30149 # Request fanout histogram
system.membus.reqLayer0.occupancy 30980000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 270472000 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 722228529 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1616 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196142 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 6197758 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264276032 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 264327744 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264276032 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 4130121 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 4130121 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 4130121 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks)
---------- Begin Simulation Statistics ----------
-sim_seconds 0.409289 # Number of seconds simulated
-sim_ticks 409289296500 # Number of ticks simulated
-final_tick 409289296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.409380 # Number of seconds simulated
+sim_ticks 409379703500 # Number of ticks simulated
+final_tick 409379703500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 309220 # Simulator instruction rate (inst/s)
-host_op_rate 309220 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 206831646 # Simulator tick rate (ticks/s)
-host_mem_usage 269756 # Number of bytes of host memory used
-host_seconds 1978.85 # Real time elapsed on the host
+host_inst_rate 330737 # Simulator instruction rate (inst/s)
+host_op_rate 330737 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 221272474 # Simulator tick rate (ticks/s)
+host_mem_usage 294228 # Number of bytes of host memory used
+host_seconds 1850.12 # Real time elapsed on the host
sim_insts 611901617 # Number of instructions simulated
sim_ops 611901617 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 24320576 # Number of bytes read from this memory
-system.physmem.bytes_read::total 24320576 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 171008 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 171008 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 18723776 # Number of bytes written to this memory
-system.physmem.bytes_written::total 18723776 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 380009 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 380009 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 292559 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 292559 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 59421481 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 59421481 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 417817 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 417817 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 45747045 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 45747045 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 45747045 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 59421481 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 105168526 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 380009 # Number of read requests accepted
-system.physmem.writeReqs 292559 # Number of write requests accepted
-system.physmem.readBursts 380009 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 292559 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 24298624 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 21952 # Total number of bytes read from write queue
-system.physmem.bytesWritten 18721984 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 24320576 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 18723776 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 343 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst 24321024 # Number of bytes read from this memory
+system.physmem.bytes_read::total 24321024 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 170880 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 170880 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 18723904 # Number of bytes written to this memory
+system.physmem.bytes_written::total 18723904 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 380016 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 380016 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 292561 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 292561 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 59409452 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 59409452 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 417412 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 417412 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 45737255 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 45737255 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 45737255 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 59409452 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 105146708 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 380016 # Number of read requests accepted
+system.physmem.writeReqs 292561 # Number of write requests accepted
+system.physmem.readBursts 380016 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 292561 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 24297984 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 23040 # Total number of bytes read from write queue
+system.physmem.bytesWritten 18722304 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 24321024 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 18723904 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 360 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 23736 # Per bank write bursts
-system.physmem.perBankRdBursts::1 23211 # Per bank write bursts
-system.physmem.perBankRdBursts::2 23514 # Per bank write bursts
-system.physmem.perBankRdBursts::3 24530 # Per bank write bursts
-system.physmem.perBankRdBursts::4 25475 # Per bank write bursts
-system.physmem.perBankRdBursts::5 23585 # Per bank write bursts
-system.physmem.perBankRdBursts::6 23686 # Per bank write bursts
-system.physmem.perBankRdBursts::7 23976 # Per bank write bursts
-system.physmem.perBankRdBursts::8 23181 # Per bank write bursts
+system.physmem.perBankRdBursts::0 23733 # Per bank write bursts
+system.physmem.perBankRdBursts::1 23212 # Per bank write bursts
+system.physmem.perBankRdBursts::2 23513 # Per bank write bursts
+system.physmem.perBankRdBursts::3 24527 # Per bank write bursts
+system.physmem.perBankRdBursts::4 25463 # Per bank write bursts
+system.physmem.perBankRdBursts::5 23584 # Per bank write bursts
+system.physmem.perBankRdBursts::6 23682 # Per bank write bursts
+system.physmem.perBankRdBursts::7 23974 # Per bank write bursts
+system.physmem.perBankRdBursts::8 23187 # Per bank write bursts
system.physmem.perBankRdBursts::9 23951 # Per bank write bursts
-system.physmem.perBankRdBursts::10 24677 # Per bank write bursts
-system.physmem.perBankRdBursts::11 22749 # Per bank write bursts
-system.physmem.perBankRdBursts::12 23715 # Per bank write bursts
-system.physmem.perBankRdBursts::13 24413 # Per bank write bursts
-system.physmem.perBankRdBursts::14 22806 # Per bank write bursts
-system.physmem.perBankRdBursts::15 22461 # Per bank write bursts
-system.physmem.perBankWrBursts::0 17754 # Per bank write bursts
+system.physmem.perBankRdBursts::10 24675 # Per bank write bursts
+system.physmem.perBankRdBursts::11 22741 # Per bank write bursts
+system.physmem.perBankRdBursts::12 23717 # Per bank write bursts
+system.physmem.perBankRdBursts::13 24415 # Per bank write bursts
+system.physmem.perBankRdBursts::14 22809 # Per bank write bursts
+system.physmem.perBankRdBursts::15 22473 # Per bank write bursts
+system.physmem.perBankWrBursts::0 17752 # Per bank write bursts
system.physmem.perBankWrBursts::1 17434 # Per bank write bursts
system.physmem.perBankWrBursts::2 17902 # Per bank write bursts
-system.physmem.perBankWrBursts::3 18770 # Per bank write bursts
+system.physmem.perBankWrBursts::3 18771 # Per bank write bursts
system.physmem.perBankWrBursts::4 19442 # Per bank write bursts
system.physmem.perBankWrBursts::5 18539 # Per bank write bursts
-system.physmem.perBankWrBursts::6 18677 # Per bank write bursts
-system.physmem.perBankWrBursts::7 18570 # Per bank write bursts
+system.physmem.perBankWrBursts::6 18683 # Per bank write bursts
+system.physmem.perBankWrBursts::7 18574 # Per bank write bursts
system.physmem.perBankWrBursts::8 18353 # Per bank write bursts
system.physmem.perBankWrBursts::9 18833 # Per bank write bursts
-system.physmem.perBankWrBursts::10 19131 # Per bank write bursts
-system.physmem.perBankWrBursts::11 17963 # Per bank write bursts
-system.physmem.perBankWrBursts::12 18220 # Per bank write bursts
-system.physmem.perBankWrBursts::13 18694 # Per bank write bursts
+system.physmem.perBankWrBursts::10 19130 # Per bank write bursts
+system.physmem.perBankWrBursts::11 17961 # Per bank write bursts
+system.physmem.perBankWrBursts::12 18219 # Per bank write bursts
+system.physmem.perBankWrBursts::13 18693 # Per bank write bursts
system.physmem.perBankWrBursts::14 17148 # Per bank write bursts
-system.physmem.perBankWrBursts::15 17101 # Per bank write bursts
+system.physmem.perBankWrBursts::15 17102 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 409289215500 # Total gap between requests
+system.physmem.totGap 409379622500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 380009 # Read request sizes (log2)
+system.physmem.readPktSize::6 380016 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 292559 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 378276 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1375 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 292561 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 378259 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 1382 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 6993 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 7538 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 16933 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 17310 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 17382 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 17417 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 17401 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 17377 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::24 17387 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 17377 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 17385 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 17562 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 17443 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 17429 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 17559 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 17324 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 17269 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 32 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 13 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::34 33 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 25 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 23 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 17 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 15 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::42 9 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::46 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 141842 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 303.284612 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 179.855968 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 325.125721 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 50699 35.74% 35.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 38599 27.21% 62.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 13098 9.23% 72.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 8031 5.66% 77.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 5875 4.14% 81.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 3794 2.67% 84.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 3041 2.14% 86.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 2492 1.76% 88.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 16213 11.43% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 141842 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 17249 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 22.009624 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 229.029888 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 17238 99.94% 99.94% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 141528 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 303.959754 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 180.049332 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 326.018132 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 50528 35.70% 35.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 38641 27.30% 63.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 12939 9.14% 72.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 7964 5.63% 77.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 5792 4.09% 81.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 3807 2.69% 84.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 3019 2.13% 86.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 2550 1.80% 88.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 16288 11.51% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 141528 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 17267 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 21.986332 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 228.214102 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 17257 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 7 0.04% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 17249 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 17249 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.959302 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.888033 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 2.754923 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 17045 98.82% 98.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 155 0.90% 99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 27 0.16% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 7 0.04% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 2 0.01% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 1 0.01% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 2 0.01% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 2 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 1 0.01% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 2 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 17267 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 17267 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.941912 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.866733 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 2.774183 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 17056 98.78% 98.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 152 0.88% 99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 31 0.18% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 11 0.06% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 2 0.01% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 1 0.01% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 1 0.01% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 1 0.01% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 2 0.01% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 1 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 2 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 1 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 1 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 17249 # Writes before turning the bus around for reads
-system.physmem.totQLat 4014686000 # Total ticks spent queuing
-system.physmem.totMemAccLat 11133423500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1898330000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10574.26 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::168-171 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 17267 # Writes before turning the bus around for reads
+system.physmem.totQLat 4096707750 # Total ticks spent queuing
+system.physmem.totMemAccLat 11215257750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1898280000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 10790.58 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29324.26 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 59.37 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 45.74 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 59.42 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 45.75 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 29540.58 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 59.35 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 45.73 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 59.41 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 45.74 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.82 # Data bus utilization in percentage
system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 20.36 # Average write queue length when enqueuing
-system.physmem.readRowHits 314933 # Number of row buffer hits during reads
-system.physmem.writeRowHits 215412 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.95 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.63 # Row buffer hit rate for writes
-system.physmem.avgGap 608546.97 # Average gap between requests
-system.physmem.pageHitRate 78.89 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 275084055500 # Time in different power states
-system.physmem.memoryStateTime::REF 13666900000 # Time in different power states
+system.physmem.avgWrQLen 21.14 # Average write queue length when enqueuing
+system.physmem.readRowHits 314853 # Number of row buffer hits during reads
+system.physmem.writeRowHits 215803 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.93 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.76 # Row buffer hit rate for writes
+system.physmem.avgGap 608673.24 # Average gap between requests
+system.physmem.pageHitRate 78.94 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 275372649250 # Time in different power states
+system.physmem.memoryStateTime::REF 13670020000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 120533549500 # Time in different power states
+system.physmem.memoryStateTime::ACT 120335301000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 105168526 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 173388 # Transaction distribution
-system.membus.trans_dist::ReadResp 173388 # Transaction distribution
-system.membus.trans_dist::Writeback 292559 # Transaction distribution
-system.membus.trans_dist::ReadExReq 206621 # Transaction distribution
-system.membus.trans_dist::ReadExResp 206621 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052577 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1052577 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044352 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 43044352 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 43044352 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 3204296000 # Layer occupancy (ticks)
+system.membus.trans_dist::ReadReq 173391 # Transaction distribution
+system.membus.trans_dist::ReadResp 173391 # Transaction distribution
+system.membus.trans_dist::Writeback 292561 # Transaction distribution
+system.membus.trans_dist::ReadExReq 206625 # Transaction distribution
+system.membus.trans_dist::ReadExResp 206625 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052593 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1052593 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044928 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 43044928 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 672577 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 672577 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 672577 # Request fanout histogram
+system.membus.reqLayer0.occupancy 3204370000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3607299000 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 3607409500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 123707695 # Number of BP lookups
-system.cpu.branchPred.condPredicted 87624621 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 6388553 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 71411167 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 67224113 # Number of BTB hits
+system.cpu.branchPred.lookups 123709339 # Number of BP lookups
+system.cpu.branchPred.condPredicted 87626566 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 6391113 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 71478402 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 67228425 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 94.136696 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 14930801 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1120545 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 94.054180 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 14930713 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1120398 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 149298209 # DTB read hits
-system.cpu.dtb.read_misses 537277 # DTB read misses
+system.cpu.dtb.read_hits 149300115 # DTB read hits
+system.cpu.dtb.read_misses 537223 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 149835486 # DTB read accesses
-system.cpu.dtb.write_hits 57314081 # DTB write hits
-system.cpu.dtb.write_misses 66749 # DTB write misses
+system.cpu.dtb.read_accesses 149837338 # DTB read accesses
+system.cpu.dtb.write_hits 57314034 # DTB write hits
+system.cpu.dtb.write_misses 66532 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 57380830 # DTB write accesses
-system.cpu.dtb.data_hits 206612290 # DTB hits
-system.cpu.dtb.data_misses 604026 # DTB misses
+system.cpu.dtb.write_accesses 57380566 # DTB write accesses
+system.cpu.dtb.data_hits 206614149 # DTB hits
+system.cpu.dtb.data_misses 603755 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 207216316 # DTB accesses
-system.cpu.itb.fetch_hits 225738536 # ITB hits
+system.cpu.dtb.data_accesses 207217904 # DTB accesses
+system.cpu.itb.fetch_hits 225746689 # ITB hits
system.cpu.itb.fetch_misses 48 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 225738584 # ITB accesses
+system.cpu.itb.fetch_accesses 225746737 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 485 # Number of system calls
-system.cpu.numCycles 818578593 # number of cpu cycles simulated
+system.cpu.numCycles 818759407 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 611901617 # Number of instructions committed
system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 13144034 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 13148655 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.337762 # CPI: cycles per instruction
-system.cpu.ipc 0.747517 # IPC: instructions per cycle
-system.cpu.tickCycles 736835501 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 81743092 # Total number of cycles that the object has spent stopped
-system.cpu.icache.tags.replacements 3168 # number of replacements
-system.cpu.icache.tags.tagsinuse 1116.143798 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 225733539 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 4997 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 45173.812087 # Average number of references to valid blocks.
+system.cpu.cpi 1.338057 # CPI: cycles per instruction
+system.cpu.ipc 0.747352 # IPC: instructions per cycle
+system.cpu.tickCycles 736857348 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 81902059 # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements 3155 # number of replacements
+system.cpu.icache.tags.tagsinuse 1116.246910 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 225741705 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 4984 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 45293.279494 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1116.143798 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.544992 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.544992 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 1116.246910 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.545042 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.545042 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 76 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 77 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1590 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 451482069 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 451482069 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 225733539 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 225733539 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 225733539 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 225733539 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 225733539 # number of overall hits
-system.cpu.icache.overall_hits::total 225733539 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 4997 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 4997 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 4997 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 4997 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 4997 # number of overall misses
-system.cpu.icache.overall_misses::total 4997 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 227649750 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 227649750 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 227649750 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 227649750 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 227649750 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 227649750 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 225738536 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 225738536 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 225738536 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 225738536 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 225738536 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 225738536 # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses 451498362 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 451498362 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 225741705 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 225741705 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 225741705 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 225741705 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 225741705 # number of overall hits
+system.cpu.icache.overall_hits::total 225741705 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 4984 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 4984 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 4984 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 4984 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 4984 # number of overall misses
+system.cpu.icache.overall_misses::total 4984 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 227159500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 227159500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 227159500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 227159500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 227159500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 227159500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 225746689 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 225746689 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 225746689 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 225746689 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 225746689 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 225746689 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
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-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20230.943045 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20230.943045 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20230.943045 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17126.056964 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17126.056964 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27407.936902 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27407.936902 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20263.107420 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20263.107420 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20263.107420 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20263.107420 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.361826 # Number of seconds simulated
-sim_ticks 361826015500 # Number of ticks simulated
-final_tick 361826015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.361881 # Number of seconds simulated
+sim_ticks 361880862500 # Number of ticks simulated
+final_tick 361880862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 231274 # Simulator instruction rate (inst/s)
-host_op_rate 250500 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 165186980 # Simulator tick rate (ticks/s)
-host_mem_usage 321304 # Number of bytes of host memory used
-host_seconds 2190.40 # Real time elapsed on the host
+host_inst_rate 239591 # Simulator instruction rate (inst/s)
+host_op_rate 259509 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 171154005 # Simulator tick rate (ticks/s)
+host_mem_usage 311472 # Number of bytes of host memory used
+host_seconds 2114.36 # Real time elapsed on the host
sim_insts 506582155 # Number of instructions simulated
sim_ops 548695378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 9220736 # Number of bytes read from this memory
-system.physmem.bytes_read::total 9220736 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 221440 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 221440 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6177024 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6177024 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 144074 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 144074 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 96516 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 96516 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 25483894 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 25483894 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 612007 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 612007 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 17071807 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 17071807 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 17071807 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 25483894 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 42555702 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 144074 # Number of read requests accepted
-system.physmem.writeReqs 96516 # Number of write requests accepted
-system.physmem.readBursts 144074 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 96516 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 9213952 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue
-system.physmem.bytesWritten 6175488 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 9220736 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 6177024 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst 9221824 # Number of bytes read from this memory
+system.physmem.bytes_read::total 9221824 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6177344 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6177344 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 144091 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 144091 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 96521 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 96521 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 25483039 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 25483039 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 612622 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 612622 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 17070104 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 17070104 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 17070104 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 25483039 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 42553143 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 144091 # Number of read requests accepted
+system.physmem.writeReqs 96521 # Number of write requests accepted
+system.physmem.readBursts 144091 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 96521 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 9215168 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue
+system.physmem.bytesWritten 6176128 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 9221824 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 6177344 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 9331 # Per bank write bursts
-system.physmem.perBankRdBursts::1 8974 # Per bank write bursts
-system.physmem.perBankRdBursts::2 8995 # Per bank write bursts
-system.physmem.perBankRdBursts::3 8704 # Per bank write bursts
+system.physmem.perBankRdBursts::0 9338 # Per bank write bursts
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system.physmem.perBankRdBursts::4 9445 # Per bank write bursts
-system.physmem.perBankRdBursts::5 9338 # Per bank write bursts
-system.physmem.perBankRdBursts::6 8941 # Per bank write bursts
-system.physmem.perBankRdBursts::7 8096 # Per bank write bursts
-system.physmem.perBankRdBursts::8 8562 # Per bank write bursts
-system.physmem.perBankRdBursts::9 8674 # Per bank write bursts
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system.physmem.perBankRdBursts::10 8773 # Per bank write bursts
-system.physmem.perBankRdBursts::11 9481 # Per bank write bursts
-system.physmem.perBankRdBursts::12 9368 # Per bank write bursts
-system.physmem.perBankRdBursts::13 9509 # Per bank write bursts
-system.physmem.perBankRdBursts::14 8709 # Per bank write bursts
-system.physmem.perBankRdBursts::15 9068 # Per bank write bursts
-system.physmem.perBankWrBursts::0 6188 # Per bank write bursts
-system.physmem.perBankWrBursts::1 6094 # Per bank write bursts
-system.physmem.perBankWrBursts::2 6004 # Per bank write bursts
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-system.physmem.perBankWrBursts::4 6158 # Per bank write bursts
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-system.physmem.perBankWrBursts::6 6012 # Per bank write bursts
-system.physmem.perBankWrBursts::7 5489 # Per bank write bursts
-system.physmem.perBankWrBursts::8 5725 # Per bank write bursts
-system.physmem.perBankWrBursts::9 5819 # Per bank write bursts
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system.physmem.perBankWrBursts::10 5961 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6448 # Per bank write bursts
-system.physmem.perBankWrBursts::12 6304 # Per bank write bursts
-system.physmem.perBankWrBursts::13 6266 # Per bank write bursts
-system.physmem.perBankWrBursts::14 5996 # Per bank write bursts
-system.physmem.perBankWrBursts::15 6043 # Per bank write bursts
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+system.physmem.perBankWrBursts::14 5992 # Per bank write bursts
+system.physmem.perBankWrBursts::15 6041 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 361825986500 # Total gap between requests
+system.physmem.totGap 361880833500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 144074 # Read request sizes (log2)
+system.physmem.readPktSize::6 144091 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 96516 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 143606 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 344 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 96521 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 143620 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 348 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::33 13 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 64715 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 237.790435 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 157.392081 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 243.201287 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 24444 37.77% 37.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 18161 28.06% 65.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6768 10.46% 76.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 7845 12.12% 88.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2212 3.42% 91.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1114 1.72% 93.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 793 1.23% 94.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 596 0.92% 95.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 2782 4.30% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 64715 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5568 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 25.855065 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 382.360630 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 5564 99.93% 99.93% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 64681 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 237.949073 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 157.463319 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 243.404639 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 24397 37.72% 37.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 18169 28.09% 65.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 6808 10.53% 76.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 7802 12.06% 88.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2168 3.35% 91.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1166 1.80% 93.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 777 1.20% 94.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 613 0.95% 95.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 2781 4.30% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 64681 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 5584 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 25.784921 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 381.788967 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 5580 99.93% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5568 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5568 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.329741 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.226111 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 2.490816 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17 2624 47.13% 47.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19 2801 50.31% 97.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21 48 0.86% 98.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23 25 0.45% 98.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25 21 0.38% 99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27 12 0.22% 99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29 8 0.14% 99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31 6 0.11% 99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33 3 0.05% 99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35 4 0.07% 99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37 1 0.02% 99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38-39 5 0.09% 99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-41 2 0.04% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50-51 1 0.02% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-53 1 0.02% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-57 1 0.02% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::58-59 1 0.02% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-69 2 0.04% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::70-71 1 0.02% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-81 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5568 # Writes before turning the bus around for reads
-system.physmem.totQLat 1536727500 # Total ticks spent queuing
-system.physmem.totMemAccLat 4236127500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 719840000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10674.09 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 5584 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 5584 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.281877 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.171400 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 2.885179 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 5428 97.21% 97.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 84 1.50% 98.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 28 0.50% 99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 20 0.36% 99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 9 0.16% 99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 7 0.13% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 2 0.04% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 1 0.02% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 2 0.04% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 1 0.02% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 1 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 5584 # Writes before turning the bus around for reads
+system.physmem.totQLat 1580318000 # Total ticks spent queuing
+system.physmem.totMemAccLat 4280074250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 719935000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 10975.42 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29424.09 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 25.47 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 29725.42 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 25.46 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 17.07 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 25.48 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 17.07 # Average system write bandwidth in MiByte/s
system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 19.41 # Average write queue length when enqueuing
-system.physmem.readRowHits 111270 # Number of row buffer hits during reads
-system.physmem.writeRowHits 64468 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 77.29 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 66.80 # Row buffer hit rate for writes
-system.physmem.avgGap 1503911.16 # Average gap between requests
-system.physmem.pageHitRate 73.08 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 254085865250 # Time in different power states
-system.physmem.memoryStateTime::REF 12081940000 # Time in different power states
+system.physmem.avgWrQLen 20.42 # Average write queue length when enqueuing
+system.physmem.readRowHits 111153 # Number of row buffer hits during reads
+system.physmem.writeRowHits 64649 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 77.20 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 66.98 # Row buffer hit rate for writes
+system.physmem.avgGap 1504001.60 # Average gap between requests
+system.physmem.pageHitRate 73.10 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 254039828500 # Time in different power states
+system.physmem.memoryStateTime::REF 12083760000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 95653103250 # Time in different power states
+system.physmem.memoryStateTime::ACT 95752175500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 42555702 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 43212 # Transaction distribution
-system.membus.trans_dist::ReadResp 43212 # Transaction distribution
-system.membus.trans_dist::Writeback 96516 # Transaction distribution
-system.membus.trans_dist::ReadExReq 100862 # Transaction distribution
-system.membus.trans_dist::ReadExResp 100862 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384664 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 384664 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15397760 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 15397760 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 15397760 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1075054000 # Layer occupancy (ticks)
+system.membus.trans_dist::ReadReq 43225 # Transaction distribution
+system.membus.trans_dist::ReadResp 43225 # Transaction distribution
+system.membus.trans_dist::Writeback 96521 # Transaction distribution
+system.membus.trans_dist::ReadExReq 100866 # Transaction distribution
+system.membus.trans_dist::ReadExResp 100866 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384703 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 384703 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15399168 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 15399168 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 240612 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 240612 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 240612 # Request fanout histogram
+system.membus.reqLayer0.occupancy 1075136000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1362559750 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 1362650250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 132256489 # Number of BP lookups
-system.cpu.branchPred.condPredicted 98266035 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 6550672 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 68852239 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 64692489 # Number of BTB hits
+system.cpu.branchPred.lookups 132262855 # Number of BP lookups
+system.cpu.branchPred.condPredicted 98270441 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 6551317 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 68771118 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 64694090 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 93.958439 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 9992276 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 17882 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 94.071598 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 9992883 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 17801 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
-system.cpu.numCycles 723652031 # number of cpu cycles simulated
+system.cpu.numCycles 723761725 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 506582155 # Number of instructions committed
system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 14122871 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 14127209 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.428499 # CPI: cycles per instruction
-system.cpu.ipc 0.700036 # IPC: instructions per cycle
-system.cpu.tickCycles 687771211 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 35880820 # Total number of cycles that the object has spent stopped
-system.cpu.icache.tags.replacements 17660 # number of replacements
-system.cpu.icache.tags.tagsinuse 1187.686040 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 200323378 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 19531 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 10256.688239 # Average number of references to valid blocks.
+system.cpu.cpi 1.428715 # CPI: cycles per instruction
+system.cpu.ipc 0.699929 # IPC: instructions per cycle
+system.cpu.tickCycles 687792337 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 35969388 # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements 17682 # number of replacements
+system.cpu.icache.tags.tagsinuse 1187.679119 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 200328523 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 19553 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 10245.411088 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1187.686040 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.579925 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.579925 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 1187.679119 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.579921 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.579921 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1871 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 1404 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 304 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 400705349 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 400705349 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 200323378 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 200323378 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 200323378 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 200323378 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 200323378 # number of overall hits
-system.cpu.icache.overall_hits::total 200323378 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 19531 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 19531 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 19531 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 19531 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 19531 # number of overall misses
-system.cpu.icache.overall_misses::total 19531 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 466485747 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 466485747 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 466485747 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 466485747 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 466485747 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 466485747 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 200342909 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 200342909 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 200342909 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 200342909 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 200342909 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 200342909 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23884.375966 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 23884.375966 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 23884.375966 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 23884.375966 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 23884.375966 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 23884.375966 # average overall miss latency
+system.cpu.icache.tags.tag_accesses 400715705 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 400715705 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 200328523 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 200328523 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 200328523 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 200328523 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 200328523 # number of overall hits
+system.cpu.icache.overall_hits::total 200328523 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 19553 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 19553 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 19553 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 19553 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 19553 # number of overall misses
+system.cpu.icache.overall_misses::total 19553 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 468017498 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 468017498 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 468017498 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 468017498 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 468017498 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 468017498 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 200348076 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 200348076 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 200348076 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 200348076 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 200348076 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 200348076 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000098 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000098 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000098 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000098 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000098 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000098 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23935.840945 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 23935.840945 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 23935.840945 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 23935.840945 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 23935.840945 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 23935.840945 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19531 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 19531 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 19531 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 19531 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 19531 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 19531 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 426041253 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 426041253 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 426041253 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 426041253 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 426041253 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 426041253 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21813.591368 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21813.591368 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21813.591368 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 21813.591368 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21813.591368 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 21813.591368 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19553 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 19553 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 19553 # number of demand (read+write) MSHR misses
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.195021 # Number of seconds simulated
-sim_ticks 195020773000 # Number of ticks simulated
-final_tick 195020773000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.231519 # Number of seconds simulated
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+final_tick 231518815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 105873 # Simulator instruction rate (inst/s)
-host_op_rate 114698 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 40866801 # Simulator tick rate (ticks/s)
-host_mem_usage 257276 # Number of bytes of host memory used
-host_seconds 4772.11 # Real time elapsed on the host
+host_inst_rate 126327 # Simulator instruction rate (inst/s)
+host_op_rate 136857 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 57887815 # Simulator tick rate (ticks/s)
+host_mem_usage 321348 # Number of bytes of host memory used
+host_seconds 3999.44 # Real time elapsed on the host
sim_insts 505237723 # Number of instructions simulated
sim_ops 547350944 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
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-system.physmem.bytes_read::cpu.data 9274560 # Number of bytes read from this memory
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-system.physmem.bytes_inst_read::total 207936 # Number of instructions bytes read from this memory
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-system.physmem.num_writes::total 97556 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1066225 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 47556780 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_inst_read::total 1066225 # Instruction read bandwidth from this memory (bytes/s)
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-system.physmem.bw_write::total 32014969 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 32014969 # Total bandwidth to/from this memory (bytes/s)
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-system.physmem.writeReqs 97556 # Number of write requests accepted
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-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 9 # Number of requests that are neither read nor write
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+system.physmem.bw_inst_read::cpu.inst 585214 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 585214 # Instruction read bandwidth from this memory (bytes/s)
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+system.physmem.bytesReadDRAM 28559360 # Total number of bytes read from DRAM
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 195020664000 # Total gap between requests
+system.physmem.totGap 231518762500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 148164 # Read request sizes (log2)
+system.physmem.readPktSize::6 448618 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 65254 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 240.825329 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 153.977579 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 256.120796 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 26634 40.82% 40.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 17090 26.19% 67.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6012 9.21% 76.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 6427 9.85% 86.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 3020 4.63% 90.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1342 2.06% 92.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 838 1.28% 94.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 692 1.06% 95.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 3199 4.90% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 65254 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5732 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 25.824669 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 376.283766 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 5727 99.91% 99.91% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 4 0.07% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5732 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5732 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.014829 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.919448 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 2.243342 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17 3608 62.94% 62.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19 1943 33.90% 96.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21 77 1.34% 98.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23 32 0.56% 98.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25 17 0.30% 99.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27 19 0.33% 99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29 11 0.19% 99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31 3 0.05% 99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33 2 0.03% 99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35 6 0.10% 99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37 2 0.03% 99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38-39 3 0.05% 99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-41 2 0.03% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42-43 1 0.02% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-49 1 0.02% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50-51 3 0.05% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-61 1 0.02% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-77 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5732 # Writes before turning the bus around for reads
-system.physmem.totQLat 1847546250 # Total ticks spent queuing
-system.physmem.totMemAccLat 4623183750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 740170000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 12480.55 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 319369 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 150.306987 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 104.535813 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 187.171349 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 189945 59.48% 59.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 84511 26.46% 85.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 17715 5.55% 91.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 8285 2.59% 94.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 5483 1.72% 95.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2730 0.85% 96.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1944 0.61% 97.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1733 0.54% 97.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 7023 2.20% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 319369 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 17997 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 24.795133 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 115.387055 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511 17996 99.99% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::15360-15871 1 0.01% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 17997 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 17997 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.881758 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.836627 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.284458 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 11076 61.54% 61.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 293 1.63% 63.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 5463 30.36% 93.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 684 3.80% 97.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 201 1.12% 98.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 109 0.61% 99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 62 0.34% 99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 46 0.26% 99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 32 0.18% 99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 17 0.09% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 10 0.06% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27 2 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28 2 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 17997 # Writes before turning the bus around for reads
+system.physmem.totQLat 10651839911 # Total ticks spent queuing
+system.physmem.totMemAccLat 19018839911 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2231200000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 23870.20 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 31230.55 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 48.58 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 32.01 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 48.62 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 32.01 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 42620.20 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 123.36 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 83.99 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 124.01 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 83.99 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.63 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.25 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 19.21 # Average write queue length when enqueuing
-system.physmem.readRowHits 116004 # Number of row buffer hits during reads
-system.physmem.writeRowHits 64298 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 78.36 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 65.91 # Row buffer hit rate for writes
-system.physmem.avgGap 793670.29 # Average gap between requests
-system.physmem.pageHitRate 73.42 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 115260013250 # Time in different power states
-system.physmem.memoryStateTime::REF 6511960000 # Time in different power states
+system.physmem.busUtil 1.62 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.96 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.66 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.28 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 21.96 # Average write queue length when enqueuing
+system.physmem.readRowHits 331076 # Number of row buffer hits during reads
+system.physmem.writeRowHits 99609 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 74.19 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 32.78 # Row buffer hit rate for writes
+system.physmem.avgGap 307679.62 # Average gap between requests
+system.physmem.pageHitRate 57.42 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 82440834065 # Time in different power states
+system.physmem.memoryStateTime::REF 7730840000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 73245775250 # Time in different power states
+system.physmem.memoryStateTime::ACT 141344957185 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 80637974 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 46897 # Transaction distribution
-system.membus.trans_dist::ReadResp 46897 # Transaction distribution
-system.membus.trans_dist::Writeback 97556 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 9 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 9 # Transaction distribution
-system.membus.trans_dist::ReadExReq 101267 # Transaction distribution
-system.membus.trans_dist::ReadExResp 101267 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393902 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 393902 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15726080 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 15726080 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 15726080 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1079373000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1394503741 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
+system.membus.trans_dist::ReadReq 445006 # Transaction distribution
+system.membus.trans_dist::ReadResp 445005 # Transaction distribution
+system.membus.trans_dist::Writeback 303849 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4 # Transaction distribution
+system.membus.trans_dist::ReadExReq 3612 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3612 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1201092 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1201092 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 48157824 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 48157824 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 752471 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 752471 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 752471 # Request fanout histogram
+system.membus.reqLayer0.occupancy 3332077149 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4185038226 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 1.8 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 200189098 # Number of BP lookups
-system.cpu.branchPred.condPredicted 149602484 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 7338467 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 107397070 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 96034676 # Number of BTB hits
+system.cpu.branchPred.lookups 175071152 # Number of BP lookups
+system.cpu.branchPred.condPredicted 131322715 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 7444793 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 90519847 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 83861329 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 89.420201 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 14381720 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 112950 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 92.644135 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 12106556 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 104156 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
-system.cpu.numCycles 390041547 # number of cpu cycles simulated
+system.cpu.numCycles 463037632 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 129697358 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 835224616 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 200189098 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 110416396 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 251952283 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 16305676 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 54 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 725 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 54 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 125022986 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 2819221 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 389803312 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.324321 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.986703 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 7744945 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 731737281 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 175071152 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 95967885 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 447534266 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 14941834 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 1659 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 92 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 5427 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 236688876 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 32715 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 462757306 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.712462 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.175357 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 204497213 52.46% 52.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 16740879 4.29% 56.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 25096143 6.44% 63.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 25406235 6.52% 69.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 22255484 5.71% 75.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 19361790 4.97% 80.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 11228649 2.88% 83.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 12061789 3.09% 86.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 53155130 13.64% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 90876963 19.64% 19.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 132670365 28.67% 48.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 57846045 12.50% 60.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 181363933 39.19% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 389803312 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.513251 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.141373 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 103986680 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 118578898 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 144750042 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 14406980 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 8080712 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 27470111 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 74706 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 847095448 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 284101 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 8080712 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 110645607 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 38128402 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 58728570 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 152416718 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 21803303 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 812473012 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 12287 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 7169304 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 5481410 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 7159011 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 991790845 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3569028243 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 858899446 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 368 # Number of floating rename lookups
+system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 462757306 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.378093 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.580298 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 32282524 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 114399962 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 287068107 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 22024470 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 6982243 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 24051856 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 496503 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 715776548 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 29996318 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 6982243 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 63336368 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 51265821 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 40318949 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 276671864 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 24182061 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 686555121 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 13345686 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 9390411 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 2448056 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 1886350 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 1781676 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 830967104 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3019014961 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 723882014 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 337667094 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2298389 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 3025745 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 46474458 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 165564895 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 77029612 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 33913346 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 24718127 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 764294822 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 3785962 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 654447179 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 456586 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 218477687 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 578622397 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 808330 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 389803312 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.678916 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.824028 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 176843353 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1544699 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1534843 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 42245148 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 143514956 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 67977247 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 12906743 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 11318799 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 668118132 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2978327 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 610228240 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 5853948 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 122686035 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 319113529 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 695 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 462757306 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.318679 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.100986 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 146772690 37.65% 37.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 67318590 17.27% 54.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 64772838 16.62% 71.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 47064670 12.07% 83.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 29521584 7.57% 91.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 16702188 4.28% 95.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 11171964 2.87% 98.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 4070461 1.04% 99.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 2408327 0.62% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 146182906 31.59% 31.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 100038869 21.62% 53.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 146348422 31.63% 84.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 63256392 13.67% 98.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 6930234 1.50% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 483 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 389803312 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 462757306 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 1532664 16.20% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 4929602 52.11% 68.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2998000 31.69% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 71302550 52.76% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 30 0.00% 52.76% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 44544615 32.96% 85.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 19303772 14.28% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 441248731 67.42% 67.42% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 435633 0.07% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 147725739 22.57% 90.06% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 65037073 9.94% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 413152046 67.70% 67.70% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 351776 0.06% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 134203526 21.99% 89.75% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 62520889 10.25% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 654447179 # Type of FU issued
-system.cpu.iq.rate 1.677891 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 9460266 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.014455 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1708614343 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 987386046 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 633379143 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 179 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 280 # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total 610228240 # Type of FU issued
+system.cpu.iq.rate 1.317880 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 135150967 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.221476 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1824218408 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 793810560 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 594959757 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 663907354 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 91 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 7666119 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses 745379030 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 7280442 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 49680139 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 29913 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 831675 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 20169135 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 27630200 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 25086 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 28806 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 11116770 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 1622994 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 4397 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 223121 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 19597 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 8080712 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 32831376 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 2550941 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 769700415 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 729466 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 165564895 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 77029612 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 2297420 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 241239 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 2243400 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 831675 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 4474207 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4147009 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 8621216 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 645315428 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 144284542 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 9131751 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 6982243 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 22081514 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 631252 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 672583080 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 143514956 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 67977247 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1489785 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 250111 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 248516 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 28806 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 3822828 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 3734625 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 7557453 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 599378907 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 129568453 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 10849333 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1619631 # number of nop insts executed
-system.cpu.iew.exec_refs 207974195 # number of memory reference insts executed
-system.cpu.iew.exec_branches 141482846 # Number of branches executed
-system.cpu.iew.exec_stores 63689653 # Number of stores executed
-system.cpu.iew.exec_rate 1.654479 # Inst execution rate
-system.cpu.iew.wb_sent 638544011 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 633379159 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 371951295 # num instructions producing a value
-system.cpu.iew.wb_consumers 631497340 # num instructions consuming a value
+system.cpu.iew.exec_nop 1486621 # number of nop insts executed
+system.cpu.iew.exec_refs 190517594 # number of memory reference insts executed
+system.cpu.iew.exec_branches 131372634 # Number of branches executed
+system.cpu.iew.exec_stores 60949141 # Number of stores executed
+system.cpu.iew.exec_rate 1.294450 # Inst execution rate
+system.cpu.iew.wb_sent 596258031 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 594959773 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 349881958 # num instructions producing a value
+system.cpu.iew.wb_consumers 570306345 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.623876 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.588999 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.284906 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.613498 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 221053017 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 109964782 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 7266341 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 357986400 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.532725 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.266212 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 161840085 45.21% 45.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 93598872 26.15% 71.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 31669454 8.85% 80.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 16147172 4.51% 84.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 14656641 4.09% 88.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 6778711 1.89% 90.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 6277378 1.75% 92.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3013551 0.84% 93.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 24004536 6.71% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 217106456 48.72% 48.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 116021912 26.03% 74.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 43540852 9.77% 84.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 23444090 5.26% 89.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 10918152 2.45% 92.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 8056532 1.81% 94.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 8490018 1.91% 95.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 4239418 0.95% 96.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 13835955 3.10% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 357986400 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 445653385 # Number of insts commited each cycle
system.cpu.commit.committedInsts 506581607 # Number of instructions committed
system.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction
-system.cpu.commit.bw_lim_events 24004536 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 13835955 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1103722571 # The number of ROB reads
-system.cpu.rob.rob_writes 1571491093 # The number of ROB writes
-system.cpu.timesIdled 5225 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 238235 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 1090469902 # The number of ROB reads
+system.cpu.rob.rob_writes 1334452491 # The number of ROB writes
+system.cpu.timesIdled 9125 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 280326 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 505237723 # Number of Instructions Simulated
system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.771996 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.771996 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.295343 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.295343 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 652860530 # number of integer regfile reads
-system.cpu.int_regfile_writes 354600440 # number of integer regfile writes
+system.cpu.cpi 0.916475 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.916475 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.091137 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.091137 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 611059108 # number of integer regfile reads
+system.cpu.int_regfile_writes 328109228 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.cc_regfile_reads 2339325657 # number of cc regfile reads
-system.cpu.cc_regfile_writes 397666160 # number of cc regfile writes
-system.cpu.misc_regfile_reads 231739115 # number of misc regfile reads
+system.cpu.cc_regfile_reads 2170105339 # number of cc regfile reads
+system.cpu.cc_regfile_writes 376537944 # number of cc regfile writes
+system.cpu.misc_regfile_reads 217957701 # number of misc regfile reads
system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 764614178 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 866616 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 866616 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 1114497 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 52 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 52 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 348819 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 348819 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30021 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3515389 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 3545410 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 958720 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 148153024 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 149111744 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 149111744 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 3904 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 2279489000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 23116485 # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::ReadReq 2375912 # Transaction distribution
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+system.cpu.toL2Bus.trans_dist::HardPFReq 453182 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
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+system.cpu.toL2Bus.trans_dist::ReadExResp 521741 # Transaction distribution
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+system.cpu.toL2Bus.pkt_size::total 335773440 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 453214 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 5699735 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5.079509 # Request fanout histogram
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+system.cpu.toL2Bus.snoopLayer0.occupancy 1500 # Layer occupancy (ticks)
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system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
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-system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
-system.cpu.icache.tags.replacements 13145 # number of replacements
-system.cpu.icache.tags.tagsinuse 1062.088688 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 125003617 # Total number of references to valid blocks.
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-system.cpu.icache.overall_miss_rate::total 0.000155 # miss rate for overall accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::total 27129.891717 # average ReadReq miss latency
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-system.cpu.icache.blocked_cycles::no_mshrs 1332 # number of cycles access was blocked
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-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu.icache.tags.sampled_refs 74050 # Sample count of references to valid blocks.
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system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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-system.cpu.icache.overall_mshr_hits::total 4325 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15041 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 15041 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 15041 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 15041 # number of demand (read+write) MSHR misses
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-system.cpu.icache.overall_mshr_misses::total 15041 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 373138014 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 373138014 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 373138014 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 373138014 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 373138014 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 373138014 # number of overall MSHR miss cycles
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-system.cpu.dcache.overall_miss_latency::cpu.data 102796861168 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 102796861168 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 131993221 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 131993221 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data 166675573 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 166675573 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 166678355 # number of overall hits
+system.cpu.dcache.overall_hits::total 166678355 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 4800209 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 4800209 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2248788 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2248788 # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 7048997 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 7048997 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 7049008 # number of overall misses
+system.cpu.dcache.overall_misses::total 7049008 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 52407946970 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 52407946970 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 17171706952 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 17171706952 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1091500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 1091500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 69579653922 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 69579653922 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 69579653922 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 69579653922 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 119485264 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 119485264 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 3948 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 3948 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488896 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 1488896 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 2793 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total 2793 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488622 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 1488622 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 186232527 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 186232527 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 186236475 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 186236475 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012993 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.012993 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.061974 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.061974 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.019250 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.019250 # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000027 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000027 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.027259 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.027259 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.027258 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.027258 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17116.473316 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17116.473316 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21848.389178 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 21848.389178 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15900 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15900 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 20249.769458 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 20249.769458 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 20249.466302 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 20249.466302 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 21467 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 55050 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 2269 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.460996 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 83.282905 # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 173724570 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 173724570 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 173727363 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 173727363 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040174 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.040174 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041460 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.041460 # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003938 # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.003938 # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.040576 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.040576 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.040575 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.040575 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10917.846904 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 10917.846904 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7635.983006 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 7635.983006 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16537.878788 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16537.878788 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 9870.858779 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 9870.858779 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 9870.843376 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 9870.843376 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 90 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 457811 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 10298 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 18 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 44.456302 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1114497 # number of writebacks
-system.cpu.dcache.writebacks::total 1114497 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 862982 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 862982 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3013069 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 3013069 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3876051 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3876051 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3876051 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3876051 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 852033 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 852033 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348362 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 348362 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 51 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 51 # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1200395 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1200395 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1200446 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1200446 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12334131763 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 12334131763 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10183047234 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 10183047234 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2581000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2581000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22517178997 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 22517178997 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22519759997 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 22519759997 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006455 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006455 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.012918 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.012918 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006446 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.006446 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006446 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.006446 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14476.119778 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14476.119778 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29231.222791 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29231.222791 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50607.843137 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50607.843137 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18758.141276 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 18758.141276 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18759.494385 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 18759.494385 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 2348838 # number of writebacks
+system.cpu.dcache.writebacks::total 2348838 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2496542 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 2496542 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1728863 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1728863 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 4225405 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 4225405 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 4225405 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 4225405 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2303667 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 2303667 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519925 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 519925 # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2823592 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2823592 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2823602 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2823602 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24988772774 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 24988772774 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4018318990 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4018318990 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 655000 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 655000 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29007091764 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 29007091764 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29007746764 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 29007746764 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019280 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019280 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009586 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009586 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003580 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003580 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016253 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.016253 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016253 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.016253 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10847.389303 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10847.389303 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7728.651229 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7728.651229 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 65500 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 65500 # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10273.117279 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 10273.117279 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10273.312869 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 10273.312869 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 279362297500 # Number of ticks simulated
final_tick 279362297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1833232 # Simulator instruction rate (inst/s)
-host_op_rate 1985632 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1010964168 # Simulator tick rate (ticks/s)
-host_mem_usage 309500 # Number of bytes of host memory used
-host_seconds 276.33 # Real time elapsed on the host
+host_inst_rate 2087081 # Simulator instruction rate (inst/s)
+host_op_rate 2260585 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1150953174 # Simulator tick rate (ticks/s)
+host_mem_usage 299952 # Number of bytes of host memory used
+host_seconds 242.72 # Real time elapsed on the host
sim_insts 506581607 # Number of instructions simulated
sim_ops 548694828 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7397009255 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2287067119 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9684076374 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 9684076374 # Throughput (bytes/s)
-system.membus.data_through_bus 2705365825 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 630711790 # Transaction distribution
+system.membus.trans_dist::ReadResp 632200331 # Transaction distribution
+system.membus.trans_dist::WriteReq 54239306 # Transaction distribution
+system.membus.trans_dist::WriteResp 54239306 # Transaction distribution
+system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution
+system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution
+system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution
+system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution
+system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033222750 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342638748 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1375861498 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066445500 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 2705365825 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 687930749 # Request fanout histogram
+system.membus.snoop_fanout::mean 4.750964 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::4 171319374 24.90% 24.90% # Request fanout histogram
+system.membus.snoop_fanout::5 516611375 75.10% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 4 # Request fanout histogram
+system.membus.snoop_fanout::max_value 5 # Request fanout histogram
+system.membus.snoop_fanout::total 687930749 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
sim_ticks 707539023000 # Number of ticks simulated
final_tick 707539023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1172742 # Simulator instruction rate (inst/s)
-host_op_rate 1270027 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1643133313 # Simulator tick rate (ticks/s)
-host_mem_usage 319240 # Number of bytes of host memory used
-host_seconds 430.60 # Real time elapsed on the host
+host_inst_rate 1199909 # Simulator instruction rate (inst/s)
+host_op_rate 1299448 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1681197618 # Simulator tick rate (ticks/s)
+host_mem_usage 309428 # Number of bytes of host memory used
+host_seconds 420.85 # Real time elapsed on the host
sim_insts 504986853 # Number of instructions simulated
sim_ops 546878104 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 250559 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 12652667 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 21582595 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 21582595 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 41855 # Transaction distribution
system.membus.trans_dist::ReadResp 41855 # Transaction distribution
system.membus.trans_dist::Writeback 95953 # Transaction distribution
system.membus.trans_dist::ReadExResp 100794 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 15270528 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 238603 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 238603 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 238603 # Request fanout histogram
system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 200387557 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23042 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3342741 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 3365783 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 141782016 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 2215344 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 2215344 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 2215344 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks)
---------- Begin Simulation Statistics ----------
-sim_seconds 0.451995 # Number of seconds simulated
-sim_ticks 451994820000 # Number of ticks simulated
-final_tick 451994820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.451764 # Number of seconds simulated
+sim_ticks 451764406000 # Number of ticks simulated
+final_tick 451764406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 140398 # Simulator instruction rate (inst/s)
-host_op_rate 259611 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 76745378 # Simulator tick rate (ticks/s)
-host_mem_usage 366028 # Number of bytes of host memory used
-host_seconds 5889.54 # Real time elapsed on the host
+host_inst_rate 99375 # Simulator instruction rate (inst/s)
+host_op_rate 183755 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 54293474 # Simulator tick rate (ticks/s)
+host_mem_usage 421524 # Number of bytes of host memory used
+host_seconds 8320.79 # Real time elapsed on the host
sim_insts 826877109 # Number of instructions simulated
sim_ops 1528988701 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 225600 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24537408 # Number of bytes read from this memory
-system.physmem.bytes_read::total 24763008 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 225600 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 225600 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 18819200 # Number of bytes written to this memory
-system.physmem.bytes_written::total 18819200 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3525 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 383397 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 386922 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 294050 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 294050 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 499121 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 54286923 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 54786044 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 499121 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 499121 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 41635875 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 41635875 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 41635875 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 499121 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 54286923 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 96421919 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 386922 # Number of read requests accepted
-system.physmem.writeReqs 294050 # Number of write requests accepted
-system.physmem.readBursts 386922 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 294050 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 24741248 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 21760 # Total number of bytes read from write queue
-system.physmem.bytesWritten 18817856 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 24763008 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 18819200 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 340 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst 224064 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24540544 # Number of bytes read from this memory
+system.physmem.bytes_read::total 24764608 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 224064 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 224064 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 18820736 # Number of bytes written to this memory
+system.physmem.bytes_written::total 18820736 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 3501 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 383446 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 386947 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 294074 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 294074 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 495975 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 54321553 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 54817528 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 495975 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 495975 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 41660511 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 41660511 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 41660511 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 495975 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 54321553 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 96478039 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 386948 # Number of read requests accepted
+system.physmem.writeReqs 294074 # Number of write requests accepted
+system.physmem.readBursts 386948 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 294074 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 24743168 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 21504 # Total number of bytes read from write queue
+system.physmem.bytesWritten 18819072 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 24764672 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 18820736 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 336 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 187441 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 24125 # Per bank write bursts
-system.physmem.perBankRdBursts::1 26507 # Per bank write bursts
-system.physmem.perBankRdBursts::2 24686 # Per bank write bursts
-system.physmem.perBankRdBursts::3 24623 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 179060 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 24122 # Per bank write bursts
+system.physmem.perBankRdBursts::1 26505 # Per bank write bursts
+system.physmem.perBankRdBursts::2 24681 # Per bank write bursts
+system.physmem.perBankRdBursts::3 24611 # Per bank write bursts
system.physmem.perBankRdBursts::4 23302 # Per bank write bursts
-system.physmem.perBankRdBursts::5 23746 # Per bank write bursts
-system.physmem.perBankRdBursts::6 24462 # Per bank write bursts
-system.physmem.perBankRdBursts::7 24273 # Per bank write bursts
-system.physmem.perBankRdBursts::8 23635 # Per bank write bursts
-system.physmem.perBankRdBursts::9 23973 # Per bank write bursts
-system.physmem.perBankRdBursts::10 24803 # Per bank write bursts
-system.physmem.perBankRdBursts::11 24077 # Per bank write bursts
-system.physmem.perBankRdBursts::12 23354 # Per bank write bursts
-system.physmem.perBankRdBursts::13 22972 # Per bank write bursts
-system.physmem.perBankRdBursts::14 24056 # Per bank write bursts
-system.physmem.perBankRdBursts::15 23988 # Per bank write bursts
-system.physmem.perBankWrBursts::0 18554 # Per bank write bursts
-system.physmem.perBankWrBursts::1 19852 # Per bank write bursts
-system.physmem.perBankWrBursts::2 18949 # Per bank write bursts
-system.physmem.perBankWrBursts::3 18947 # Per bank write bursts
-system.physmem.perBankWrBursts::4 18033 # Per bank write bursts
-system.physmem.perBankWrBursts::5 18442 # Per bank write bursts
-system.physmem.perBankWrBursts::6 18997 # Per bank write bursts
-system.physmem.perBankWrBursts::7 18979 # Per bank write bursts
-system.physmem.perBankWrBursts::8 18544 # Per bank write bursts
-system.physmem.perBankWrBursts::9 18172 # Per bank write bursts
-system.physmem.perBankWrBursts::10 18845 # Per bank write bursts
-system.physmem.perBankWrBursts::11 17739 # Per bank write bursts
-system.physmem.perBankWrBursts::12 17374 # Per bank write bursts
-system.physmem.perBankWrBursts::13 16976 # Per bank write bursts
-system.physmem.perBankWrBursts::14 17812 # Per bank write bursts
-system.physmem.perBankWrBursts::15 17814 # Per bank write bursts
+system.physmem.perBankRdBursts::5 23732 # Per bank write bursts
+system.physmem.perBankRdBursts::6 24448 # Per bank write bursts
+system.physmem.perBankRdBursts::7 24311 # Per bank write bursts
+system.physmem.perBankRdBursts::8 23620 # Per bank write bursts
+system.physmem.perBankRdBursts::9 23937 # Per bank write bursts
+system.physmem.perBankRdBursts::10 24812 # Per bank write bursts
+system.physmem.perBankRdBursts::11 24076 # Per bank write bursts
+system.physmem.perBankRdBursts::12 23393 # Per bank write bursts
+system.physmem.perBankRdBursts::13 22985 # Per bank write bursts
+system.physmem.perBankRdBursts::14 24096 # Per bank write bursts
+system.physmem.perBankRdBursts::15 23981 # Per bank write bursts
+system.physmem.perBankWrBursts::0 18558 # Per bank write bursts
+system.physmem.perBankWrBursts::1 19850 # Per bank write bursts
+system.physmem.perBankWrBursts::2 18948 # Per bank write bursts
+system.physmem.perBankWrBursts::3 18946 # Per bank write bursts
+system.physmem.perBankWrBursts::4 18040 # Per bank write bursts
+system.physmem.perBankWrBursts::5 18437 # Per bank write bursts
+system.physmem.perBankWrBursts::6 18993 # Per bank write bursts
+system.physmem.perBankWrBursts::7 18991 # Per bank write bursts
+system.physmem.perBankWrBursts::8 18543 # Per bank write bursts
+system.physmem.perBankWrBursts::9 18160 # Per bank write bursts
+system.physmem.perBankWrBursts::10 18841 # Per bank write bursts
+system.physmem.perBankWrBursts::11 17736 # Per bank write bursts
+system.physmem.perBankWrBursts::12 17380 # Per bank write bursts
+system.physmem.perBankWrBursts::13 16967 # Per bank write bursts
+system.physmem.perBankWrBursts::14 17832 # Per bank write bursts
+system.physmem.perBankWrBursts::15 17826 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 451994795000 # Total gap between requests
+system.physmem.totGap 451764392500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 386922 # Read request sizes (log2)
+system.physmem.readPktSize::6 386948 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 294050 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 381621 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4565 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 350 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 294074 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 381637 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 4588 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 337 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 6304 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 6696 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 16856 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 17449 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 17548 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 17578 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 17578 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 17585 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 17629 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 17625 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 17630 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 17600 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 17764 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 17623 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 17600 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 17825 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 17512 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 17461 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 42 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 30 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 22 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 15 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 6121 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 6527 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 16919 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 17478 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 17566 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 17579 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 17557 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 17583 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 17609 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 17628 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 17613 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 17619 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 17776 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 17688 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 17635 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 17848 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 17586 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 17479 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 44 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 21 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 18 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 26 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 26 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 21 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::47 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 147161 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 295.990160 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 174.516116 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 323.823787 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 54586 37.09% 37.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 40330 27.41% 64.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 13573 9.22% 73.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 7350 4.99% 78.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 5242 3.56% 82.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 3782 2.57% 84.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 3105 2.11% 86.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 2774 1.89% 88.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 16419 11.16% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 147161 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 17431 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 22.177500 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 209.580978 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 17417 99.92% 99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 147402 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 295.521852 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 174.115334 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 323.715133 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 54829 37.20% 37.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 40372 27.39% 64.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 13383 9.08% 73.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 7515 5.10% 78.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 5234 3.55% 82.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 3732 2.53% 84.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 3157 2.14% 86.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 2805 1.90% 88.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 16375 11.11% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 147402 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 17447 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 22.158537 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 209.201153 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 17434 99.93% 99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 17431 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 17431 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.868166 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.795967 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 2.664820 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 17240 98.90% 98.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 139 0.80% 99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 22 0.13% 99.83% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 17447 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 17447 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.853786 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.774474 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 2.995315 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 17244 98.84% 98.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 149 0.85% 99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 24 0.14% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 7 0.04% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 7 0.04% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 1 0.01% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 4 0.02% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 4 0.02% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 2 0.01% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 2 0.01% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 1 0.01% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 2 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 1 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 1 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::248-251 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 17431 # Writes before turning the bus around for reads
-system.physmem.totQLat 4215540250 # Total ticks spent queuing
-system.physmem.totMemAccLat 11463952750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1932910000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10904.65 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 2 0.01% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 1 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 1 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 1 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 1 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 1 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 17447 # Writes before turning the bus around for reads
+system.physmem.totQLat 4338654000 # Total ticks spent queuing
+system.physmem.totMemAccLat 11587629000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1933060000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 11222.24 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29654.65 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 54.74 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 41.63 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 54.79 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 41.64 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 29972.24 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 54.77 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 41.66 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 54.82 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 41.66 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.75 # Data bus utilization in percentage
system.physmem.busUtilRead 0.43 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.33 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 21.68 # Average write queue length when enqueuing
-system.physmem.readRowHits 317951 # Number of row buffer hits during reads
-system.physmem.writeRowHits 215487 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.28 # Row buffer hit rate for writes
-system.physmem.avgGap 663749.46 # Average gap between requests
-system.physmem.pageHitRate 78.37 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 313004335000 # Time in different power states
-system.physmem.memoryStateTime::REF 15093000000 # Time in different power states
+system.physmem.avgWrQLen 21.93 # Average write queue length when enqueuing
+system.physmem.readRowHits 317693 # Number of row buffer hits during reads
+system.physmem.writeRowHits 215552 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.17 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.30 # Row buffer hit rate for writes
+system.physmem.avgGap 663362.41 # Average gap between requests
+system.physmem.pageHitRate 78.34 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 312439483250 # Time in different power states
+system.physmem.memoryStateTime::REF 15085200000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 123894751250 # Time in different power states
+system.physmem.memoryStateTime::ACT 124235187750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 96421919 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 179924 # Transaction distribution
-system.membus.trans_dist::ReadResp 179924 # Transaction distribution
-system.membus.trans_dist::Writeback 294050 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 187441 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 187441 # Transaction distribution
-system.membus.trans_dist::ReadExReq 206998 # Transaction distribution
-system.membus.trans_dist::ReadExResp 206998 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1442776 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1442776 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1442776 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43582208 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43582208 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 43582208 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 43582208 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 3478883000 # Layer occupancy (ticks)
+system.membus.trans_dist::ReadReq 179971 # Transaction distribution
+system.membus.trans_dist::ReadResp 179970 # Transaction distribution
+system.membus.trans_dist::Writeback 294074 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 179060 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 179060 # Transaction distribution
+system.membus.trans_dist::ReadExReq 206977 # Transaction distribution
+system.membus.trans_dist::ReadExResp 206977 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1426089 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1426089 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1426089 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43585344 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43585344 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 43585344 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 860082 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 860082 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 860082 # Request fanout histogram
+system.membus.reqLayer0.occupancy 3467694500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4009907869 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 3995364517 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 231904597 # Number of BP lookups
-system.cpu.branchPred.condPredicted 231904597 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 9750550 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 132080719 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 129337939 # Number of BTB hits
+system.cpu.branchPred.lookups 231811700 # Number of BP lookups
+system.cpu.branchPred.condPredicted 231811700 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 9749774 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 132043202 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 129334985 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.923406 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 28018771 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1471173 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 97.948992 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 28034260 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1466603 # Number of incorrect RAS predictions.
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 551 # Number of system calls
-system.cpu.numCycles 903989670 # number of cpu cycles simulated
+system.cpu.numCycles 903528833 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 186228043 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1278728730 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 231904597 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 157356710 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 706545798 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 20232368 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 1261 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 97161 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 819145 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 1413 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 33 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 180562981 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 2742944 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 903809038 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.631393 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.340645 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 186193866 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1278658073 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 231811700 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 157369245 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 706106364 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 20239876 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 1021 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 98431 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 825605 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 1885 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 180561661 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 2733230 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 903347128 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.632355 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.341099 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 493137827 54.56% 54.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 34022388 3.76% 58.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 33226150 3.68% 62.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 33639943 3.72% 65.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 27288864 3.02% 68.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 27888530 3.09% 71.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 37359921 4.13% 75.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 33838464 3.74% 79.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 183406951 20.29% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 492680103 54.54% 54.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 34123521 3.78% 58.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 33275891 3.68% 62.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 33627770 3.72% 65.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 27182272 3.01% 68.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 27855831 3.08% 71.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 37310737 4.13% 75.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 33828820 3.74% 79.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 183462183 20.31% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 903809038 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.256535 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.414539 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 127644706 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 443195641 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 240140806 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 82711701 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 10116184 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2234020290 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 10116184 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 159943307 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 227345077 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 31762 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 285830207 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 220542501 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2184066361 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 187446 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 141210134 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 24116907 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 44409056 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 2289283449 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5527269614 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3515022878 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 52095 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 903347128 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.256563 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.415182 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 127724228 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 442644539 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 240143304 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 82715119 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 10119938 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 2233772257 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 10119938 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 159908050 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 227395701 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 31553 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 285948747 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 219943139 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2183809979 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 169165 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 140088736 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 23988102 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 45039827 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 2289176453 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5526365527 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3514194402 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 52054 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 675242595 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2439 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2426 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 427926698 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 530815140 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 210460978 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 240742093 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 72507120 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2112837832 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 25371 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1829122546 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 418643 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 579202583 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1008004721 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 24819 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 903809038 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.023793 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.068035 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 675135599 # Number of HB maps that are undone due to squashing
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+system.cpu.rename.tempSerializingInsts 2290 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 426537147 # count of insts added to the skid buffer
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+system.cpu.memDep0.conflictingStores 72173678 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2112785390 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 25204 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1829110925 # Number of instructions issued
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+system.cpu.iq.iqSquashedInstsExamined 579120624 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1007560279 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 24652 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::1 130796714 14.47% 49.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 120566882 13.34% 63.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 111745228 12.36% 75.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 90951236 10.06% 85.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 61425555 6.80% 92.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 43081513 4.77% 97.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 19099237 2.11% 99.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 7354991 0.81% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 319005991 35.31% 35.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 130297139 14.42% 49.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 120325805 13.32% 63.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 111338872 12.33% 75.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 91295017 10.11% 85.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 61401299 6.80% 92.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 43188488 4.78% 97.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 19128067 2.12% 99.18% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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+system.cpu.iq.issued_per_cycle::total 903347128 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 11301614 42.50% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 12240522 46.03% 88.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 3051129 11.47% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 11298417 42.44% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 12271176 46.10% 88.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 3050228 11.46% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 2716130 0.15% 0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1212914034 66.31% 66.46% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 390088 0.02% 66.48% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 3880828 0.21% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 131 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 435498208 23.81% 90.50% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 173723127 9.50% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 2719541 0.15% 0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1212963557 66.31% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 389902 0.02% 66.48% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 3881002 0.21% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 122 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 435438564 23.81% 90.50% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 173718237 9.50% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1829122546 # Type of FU issued
-system.cpu.iq.rate 2.023389 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 26593265 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.014539 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4589034997 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2692332475 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1799432823 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 31041 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 65517 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 6732 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1852985406 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 14275 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 184951720 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1829110925 # Type of FU issued
+system.cpu.iq.rate 2.024408 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 26619821 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.014553 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4588595925 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2692200263 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1799476115 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 30390 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 66120 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 6655 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1852997149 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 14056 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 185108157 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 146715422 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 214760 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 386957 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 61300792 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 146685050 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 212835 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 388917 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 61249864 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 19364 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 985 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 18586 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 815 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 10116184 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 166422776 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 10091675 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2112863203 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 400666 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 530817579 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 210460978 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 7795 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 4446284 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3513204 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 386957 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 5751076 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4630882 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 10381958 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1808023539 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 429432372 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 21099007 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 10119938 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 166724787 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 10164048 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2112810594 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 401170 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 530787207 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 210410050 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 7737 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 4462758 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3568650 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 388917 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 5751622 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 4609702 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 10361324 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1807989007 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 429368726 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 21121918 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 599547125 # number of memory reference insts executed
-system.cpu.iew.exec_branches 171962867 # Number of branches executed
-system.cpu.iew.exec_stores 170114753 # Number of stores executed
-system.cpu.iew.exec_rate 2.000049 # Inst execution rate
-system.cpu.iew.wb_sent 1804768043 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1799439555 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1369592486 # num instructions producing a value
-system.cpu.iew.wb_consumers 2093220611 # num instructions consuming a value
+system.cpu.iew.exec_refs 599512830 # number of memory reference insts executed
+system.cpu.iew.exec_branches 171944433 # Number of branches executed
+system.cpu.iew.exec_stores 170144104 # Number of stores executed
+system.cpu.iew.exec_rate 2.001031 # Inst execution rate
+system.cpu.iew.wb_sent 1804759601 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1799482770 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1369602342 # num instructions producing a value
+system.cpu.iew.wb_consumers 2093301343 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.990553 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.654299 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.991616 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.654279 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 584100413 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 584047933 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 9836004 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 824637269 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.854135 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.503267 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 9837228 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 824173639 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.855178 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.504108 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 355822450 43.15% 43.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 175430054 21.27% 64.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 57247046 6.94% 71.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 86422444 10.48% 81.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 27139119 3.29% 85.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 27033560 3.28% 88.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 9709039 1.18% 89.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 8849743 1.07% 90.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 76983814 9.34% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 355774645 43.17% 43.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 174944190 21.23% 64.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 57267566 6.95% 71.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 86311577 10.47% 81.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 27168668 3.30% 85.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 27065091 3.28% 88.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 9878369 1.20% 89.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 8803957 1.07% 90.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 76959576 9.34% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 824637269 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 824173639 # Number of insts commited each cycle
system.cpu.commit.committedInsts 826877109 # Number of instructions committed
system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction
-system.cpu.commit.bw_lim_events 76983814 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 76959576 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 2860742569 # The number of ROB reads
-system.cpu.rob.rob_writes 4305535749 # The number of ROB writes
-system.cpu.timesIdled 2688 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 180632 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 2860250697 # The number of ROB reads
+system.cpu.rob.rob_writes 4305432555 # The number of ROB writes
+system.cpu.timesIdled 2603 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 181705 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 826877109 # Number of Instructions Simulated
system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.093258 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.093258 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.914698 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.914698 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 2763635866 # number of integer regfile reads
-system.cpu.int_regfile_writes 1467536960 # number of integer regfile writes
-system.cpu.fp_regfile_reads 6799 # number of floating regfile reads
-system.cpu.fp_regfile_writes 207 # number of floating regfile writes
-system.cpu.cc_regfile_reads 600939716 # number of cc regfile reads
-system.cpu.cc_regfile_writes 409698109 # number of cc regfile writes
-system.cpu.misc_regfile_reads 991748256 # number of misc regfile reads
+system.cpu.cpi 1.092700 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.092700 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.915164 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.915164 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 2763452160 # number of integer regfile reads
+system.cpu.int_regfile_writes 1467518123 # number of integer regfile writes
+system.cpu.fp_regfile_reads 6756 # number of floating regfile reads
+system.cpu.fp_regfile_writes 202 # number of floating regfile writes
+system.cpu.cc_regfile_reads 600952146 # number of cc regfile reads
+system.cpu.cc_regfile_writes 409697644 # number of cc regfile writes
+system.cpu.misc_regfile_reads 991728878 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 717782102 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 1964869 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 1964868 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 2332907 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 189308 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 189308 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 771503 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 771503 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 206675 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7788165 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 7994840 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 551936 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311758592 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 312310528 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 312310528 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 12123264 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 4978085168 # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::ReadReq 1956687 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 1956686 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 2333034 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 180860 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 180860 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 771518 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 771518 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 198212 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7771975 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 7970187 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 551552 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311785216 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 312336768 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 180976 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 5242099 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 5242099 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 5242099 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 4970549506 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 297561992 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 284884490 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3985022632 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 3981162622 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
-system.cpu.icache.tags.replacements 6996 # number of replacements
-system.cpu.icache.tags.tagsinuse 1078.278361 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 180359326 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 8602 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 20967.138572 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 7001 # number of replacements
+system.cpu.icache.tags.tagsinuse 1081.953602 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 180366705 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 8614 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 20938.786278 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1078.278361 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.526503 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.526503 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 1606 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 301 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 1173 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.784180 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 361324012 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 361324012 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 180362453 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 180362453 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 180362453 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 180362453 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 180362453 # number of overall hits
-system.cpu.icache.overall_hits::total 180362453 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 200528 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 200528 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 200528 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 200528 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 200528 # number of overall misses
-system.cpu.icache.overall_misses::total 200528 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 1221704738 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 1221704738 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 1221704738 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 1221704738 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 1221704738 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 1221704738 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 180562981 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 787132235 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 787132235 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 240408250 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 240408250 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 148181290 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 148181290 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 388589540 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 388589540 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 388589540 # number of overall hits
-system.cpu.dcache.overall_hits::total 388589540 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2728505 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2728505 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 978912 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 978912 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 3707417 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3707417 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3707417 # number of overall misses
-system.cpu.dcache.overall_misses::total 3707417 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 55514293617 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 55514293617 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 27913016377 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 27913016377 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 83427309994 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 83427309994 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 83427309994 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 83427309994 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 243136755 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 243136755 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses 786699916 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 786699916 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 240205034 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 240205034 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 148189734 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 148189734 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 388394768 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 388394768 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 388394768 # number of overall hits
+system.cpu.dcache.overall_hits::total 388394768 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 2715417 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 2715417 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 970468 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 970468 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 3685885 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3685885 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3685885 # number of overall misses
+system.cpu.dcache.overall_misses::total 3685885 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 55284847940 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 55284847940 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 27786671624 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 27786671624 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 83071519564 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 83071519564 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 83071519564 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 83071519564 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 242920451 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 242920451 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 392296957 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 392296957 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 392296957 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 392296957 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011222 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.011222 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006563 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.006563 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.009451 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.009451 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.009451 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.009451 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20346.047970 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 20346.047970 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28514.326494 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 28514.326494 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22502.812603 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22502.812603 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22502.812603 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22502.812603 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 9167 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 150 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1009 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.085233 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 37.500000 # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 392080653 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 392080653 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 392080653 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 392080653 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011178 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.011178 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006506 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.006506 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.009401 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.009401 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.009401 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.009401 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20359.616199 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 20359.616199 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28632.238903 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 28632.238903 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22537.740479 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22537.740479 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22537.740479 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22537.740479 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 8578 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 67 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 914 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 5 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.385120 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 13.400000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 2332907 # number of writebacks
-system.cpu.dcache.writebacks::total 2332907 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 961470 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 961470 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18318 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 18318 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 979788 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 979788 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 979788 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 979788 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767035 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1767035 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 960594 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 960594 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2727629 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2727629 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2727629 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2727629 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30608716000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 30608716000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25669918867 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 25669918867 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56278634867 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 56278634867 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56278634867 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 56278634867 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007268 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007268 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006440 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006440 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006953 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.006953 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006953 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.006953 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17322.076812 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17322.076812 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26722.963986 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26722.963986 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20632.804119 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20632.804119 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20632.804119 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20632.804119 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 2333034 # number of writebacks
+system.cpu.dcache.writebacks::total 2333034 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 948123 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 948123 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 966414 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 966414 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 966414 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 966414 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767294 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1767294 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 952177 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 952177 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2719471 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2719471 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2719471 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2719471 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30652377753 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 30652377753 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25560484625 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 25560484625 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56212862378 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 56212862378 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56212862378 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 56212862378 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007275 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007275 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006384 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006384 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006936 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.006936 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006936 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.006936 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17344.243659 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17344.243659 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26844.257554 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26844.257554 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20670.513632 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20670.513632 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20670.513632 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20670.513632 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 885229328000 # Number of ticks simulated
final_tick 885229328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1112999 # Simulator instruction rate (inst/s)
-host_op_rate 2058060 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1191542406 # Simulator tick rate (ticks/s)
-host_mem_usage 288080 # Number of bytes of host memory used
-host_seconds 742.93 # Real time elapsed on the host
+host_inst_rate 1229934 # Simulator instruction rate (inst/s)
+host_op_rate 2274285 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1316729165 # Simulator tick rate (ticks/s)
+host_mem_usage 308776 # Number of bytes of host memory used
+host_seconds 672.29 # Real time elapsed on the host
sim_insts 826877110 # Number of instructions simulated
sim_ops 1528988702 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 9654872754 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3702436212 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13357308966 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 13357308966 # Throughput (bytes/s)
-system.membus.data_through_bus 11824281640 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 1452449251 # Transaction distribution
+system.membus.trans_dist::ReadResp 1452449251 # Transaction distribution
+system.membus.trans_dist::WriteReq 149160202 # Transaction distribution
+system.membus.trans_dist::WriteResp 149160202 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136694130 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::total 2136694130 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066524776 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::total 1066524776 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 3203218906 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546776520 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::total 8546776520 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277505120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::total 3277505120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 11824281640 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 1601609453 # Request fanout histogram
+system.membus.snoop_fanout::mean 2.667046 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::2 533262388 33.30% 33.30% # Request fanout histogram
+system.membus.snoop_fanout::3 1068347065 66.70% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 2 # Request fanout histogram
+system.membus.snoop_fanout::max_value 3 # Request fanout histogram
+system.membus.snoop_fanout::total 1601609453 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 551 # Number of system calls
sim_ticks 1647872849000 # Number of ticks simulated
final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 654522 # Simulator instruction rate (inst/s)
-host_op_rate 1210285 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1304389188 # Simulator tick rate (ticks/s)
-host_mem_usage 297832 # Number of bytes of host memory used
-host_seconds 1263.33 # Real time elapsed on the host
+host_inst_rate 845545 # Simulator instruction rate (inst/s)
+host_op_rate 1563508 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1685075999 # Simulator tick rate (ticks/s)
+host_mem_usage 318276 # Number of bytes of host memory used
+host_seconds 977.92 # Real time elapsed on the host
sim_insts 826877110 # Number of instructions simulated
sim_ops 1528988702 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 26154600 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 174452 # Transaction distribution
system.membus.trans_dist::ReadResp 174452 # Transaction distribution
system.membus.trans_dist::Writeback 292286 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 43099456 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 673429 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 673429 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 673429 # Request fanout histogram
system.membus.reqLayer0.occupancy 3011737000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 3430300500 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 188161896 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 1730228 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5628 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7360439 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7366067 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 180096 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309886784 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 310066880 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 310066880 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 180096 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309886784 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 310066880 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 4844795 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 4844795 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 4844795 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks)
sim_ticks 220941341500 # Number of ticks simulated
final_tick 220941341500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 303038 # Simulator instruction rate (inst/s)
-host_op_rate 303038 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 167944827 # Simulator tick rate (ticks/s)
-host_mem_usage 273400 # Number of bytes of host memory used
-host_seconds 1315.56 # Real time elapsed on the host
+host_inst_rate 328458 # Simulator instruction rate (inst/s)
+host_op_rate 328458 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 182032431 # Simulator tick rate (ticks/s)
+host_mem_usage 297876 # Number of bytes of host memory used
+host_seconds 1213.75 # Real time elapsed on the host
sim_insts 398664665 # Number of instructions simulated
sim_ops 398664665 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 6820 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 972 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 6821 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 971 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.bytesPerActivate::896-1023 28 1.84% 87.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 190 12.52% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1518 # Bytes accessed per row activation
-system.physmem.totQLat 52730250 # Total ticks spent queuing
-system.physmem.totMemAccLat 200386500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 53358500 # Total ticks spent queuing
+system.physmem.totMemAccLat 201014750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 39375000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 6695.90 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 6775.68 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 25445.90 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 25525.68 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.28 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.28 # Average system read bandwidth in MiByte/s
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 1721627750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 2281148 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 4737 # Transaction distribution
system.membus.trans_dist::ReadResp 4737 # Transaction distribution
system.membus.trans_dist::ReadExReq 3138 # Transaction distribution
system.membus.trans_dist::ReadExResp 3138 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15750 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 15750 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 504000 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 504000 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 504000 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 9511500 # Layer occupancy (ticks)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 504000 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 504000 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 7875 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 7875 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 7875 # Request fanout histogram
+system.membus.reqLayer0.occupancy 9512000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 74010500 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 74011500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 46221231 # Number of BP lookups
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.108407 # CPI: cycles per instruction
system.cpu.ipc 0.902196 # IPC: instructions per cycle
-system.cpu.tickCycles 437732113 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 4150570 # Total number of cycles that the object has spent stopped
+system.cpu.tickCycles 437732110 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 4150573 # Total number of cycles that the object has spent stopped
system.cpu.icache.tags.replacements 3195 # number of replacements
-system.cpu.icache.tags.tagsinuse 1919.708567 # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse 1919.708570 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 98237130 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 5173 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 18990.359559 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1919.708567 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst 1919.708570 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.937358 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.937358 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id
system.cpu.icache.demand_misses::total 5173 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 5173 # number of overall misses
system.cpu.icache.overall_misses::total 5173 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 293554750 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 293554750 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 293554750 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 293554750 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 293554750 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 293554750 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 293560000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 293560000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 293560000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 293560000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 293560000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 293560000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 98242303 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 98242303 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 98242303 # number of demand (read+write) accesses
system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56747.486951 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 56747.486951 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 56747.486951 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 56747.486951 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 56747.486951 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 56747.486951 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56748.501836 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 56748.501836 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56748.501836 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 56748.501836 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56748.501836 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 56748.501836 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 5173 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 5173 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281585250 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 281585250 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281585250 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 281585250 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281585250 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 281585250 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281592000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 281592000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281592000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 281592000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281592000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 281592000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54433.645853 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54433.645853 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54433.645853 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 54433.645853 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54433.645853 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 54433.645853 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54434.950706 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54434.950706 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54434.950706 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54434.950706 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54434.950706 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54434.950706 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 2894379 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 6139 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 6139 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10346 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8984 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 19330 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331072 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 639488 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 639488 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331072 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 639488 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 9992 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 9992 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 9992 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 5650000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 8571250 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 8570500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 6974750 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 6975500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 4427.627395 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 4427.627399 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1491 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 5274 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.282708 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 373.083919 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 4054.543476 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 4054.543479 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.011386 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123735 # Average percentage of cache occupancy
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 771 # number of replacements
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system.cpu.dcache.tags.total_refs 168007181 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 40337.858583 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 69651704000 # Number of ticks simulated
final_tick 69651704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 185769 # Simulator instruction rate (inst/s)
-host_op_rate 185769 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 34451530 # Simulator tick rate (ticks/s)
-host_mem_usage 243176 # Number of bytes of host memory used
-host_seconds 2021.73 # Real time elapsed on the host
+host_inst_rate 258321 # Simulator instruction rate (inst/s)
+host_op_rate 258321 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 47906543 # Simulator tick rate (ticks/s)
+host_mem_usage 298148 # Number of bytes of host memory used
+host_seconds 1453.91 # Real time elapsed on the host
sim_insts 375574808 # Number of instructions simulated
sim_ops 375574808 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 4229 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 4226 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1956 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 918 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 291 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 293 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 63 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1354 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 350.251108 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 208.626324 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 348.782669 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 425 31.39% 31.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 330 24.37% 55.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 151 11.15% 66.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 84 6.20% 73.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 54 3.99% 77.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 42 3.10% 80.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 39 2.88% 83.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 25 1.85% 84.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 204 15.07% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1354 # Bytes accessed per row activation
-system.physmem.totQLat 65436750 # Total ticks spent queuing
-system.physmem.totMemAccLat 205274250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples 1353 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 350.509978 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 208.823320 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 348.868335 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 424 31.34% 31.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 330 24.39% 55.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 151 11.16% 66.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 84 6.21% 73.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 54 3.99% 77.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 42 3.10% 80.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 39 2.88% 83.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 25 1.85% 84.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 204 15.08% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1353 # Bytes accessed per row activation
+system.physmem.totQLat 66704750 # Total ticks spent queuing
+system.physmem.totMemAccLat 206542250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 37290000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 8774.03 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 8944.05 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 27524.03 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 27694.05 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 6.85 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 6.85 # Average system read bandwidth in MiByte/s
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 6095 # Number of row buffer hits during reads
+system.physmem.readRowHits 6096 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.72 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 81.74 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 9339181.35 # Average gap between requests
-system.physmem.pageHitRate 81.72 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 66207100500 # Time in different power states
+system.physmem.pageHitRate 81.74 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 66207575500 # Time in different power states
system.physmem.memoryStateTime::REF 2325700000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 1115479500 # Time in different power states
+system.physmem.memoryStateTime::ACT 1115004500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 6852840 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 4328 # Transaction distribution
system.membus.trans_dist::ReadResp 4328 # Transaction distribution
system.membus.trans_dist::ReadExReq 3130 # Transaction distribution
system.membus.trans_dist::ReadExResp 3130 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14916 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 14916 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477312 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 477312 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 477312 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 9424500 # Layer occupancy (ticks)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477312 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 477312 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 7458 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 7458 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 7458 # Request fanout histogram
+system.membus.reqLayer0.occupancy 9424000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 69714000 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 69710500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 51167476 # Number of BP lookups
system.cpu.numCycles 139303411 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 52063836 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 52063861 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 457094552 # Number of instructions fetch has processed
system.cpu.fetch.Branches 51167476 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 32952094 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 85692293 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.Cycles 85692225 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2532764 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 51277823 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 545280 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 139036498 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 3.287587 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 139036455 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 3.287588 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.344928 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 58307253 41.94% 41.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 58307210 41.94% 41.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4519217 3.25% 45.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 7280822 5.24% 50.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 5545601 3.99% 54.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 139036498 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 139036455 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.367310 # Number of branch fetches per cycle
system.cpu.fetch.rate 3.281288 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 45112294 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 16348159 # Number of cycles decode is blocked
+system.cpu.decode.IdleCycles 45112319 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 16348091 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 71786999 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 4526862 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1262184 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 451283163 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 14200 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1262184 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 47010937 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 5663540 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 519055 # count of cycles rename stalled for serializing inst
+system.cpu.rename.IdleCycles 47010962 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 5663544 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 518995 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 74309214 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 10271568 # Number of cycles rename is unblocking
+system.cpu.rename.UnblockCycles 10271556 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 447721649 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 439815 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 2540100 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 2926498 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 3600584 # Number of times rename has blocked due to SQ full
+system.cpu.rename.SQFullEvents 3600572 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 292278306 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 589607782 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 419965282 # Number of integer rename lookups
system.cpu.iq.iqSquashedInstsExamined 38878487 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 18208108 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 139036498 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.926684 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.221929 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 139036455 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.926685 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.221928 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 23891417 17.18% 17.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 19616673 14.11% 31.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 22677490 16.31% 47.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 23891375 17.18% 17.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 19616672 14.11% 31.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 22677489 16.31% 47.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 18900240 13.59% 61.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 19609415 14.10% 75.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 14153869 10.18% 85.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 9626408 6.92% 92.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 19609416 14.10% 75.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 14153870 10.18% 85.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 9626407 6.92% 92.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 6209798 4.47% 96.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 4351188 3.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 139036498 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 139036455 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 258477 1.29% 1.29% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 1 0.00% 1.29% # attempts to use FU when none available
system.cpu.iq.rate 2.921076 # Inst issue rate
system.cpu.iq.fu_busy_cnt 19986240 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.049116 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 625896967 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 625896924 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 265989715 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 237228630 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 347441639 # Number of floating instruction queue reads
system.cpu.iew.lsq.thread0.cacheBlocked 4486 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1262184 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 4471522 # Number of cycles IEW is blocking
+system.cpu.iew.iewBlockCycles 4471526 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 139226 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 439574480 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 145285 # Number of squashed instructions skipped by dispatch
system.cpu.iew.exec_rate 2.894098 # Inst execution rate
system.cpu.iew.wb_sent 401401506 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 400567895 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 198000447 # num instructions producing a value
-system.cpu.iew.wb_consumers 283955601 # num instructions consuming a value
+system.cpu.iew.wb_producers 198000445 # num instructions producing a value
+system.cpu.iew.wb_consumers 283955599 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.875507 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.697294 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 40912072 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1208897 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 133310645 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.990493 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 133310602 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.990494 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 3.213946 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 48555640 36.42% 36.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 18055919 13.54% 49.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 9630862 7.22% 57.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 48555591 36.42% 36.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 18055922 13.54% 49.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 9630864 7.22% 57.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 8737321 6.55% 63.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 6426213 4.82% 68.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 6426217 4.82% 68.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 4404757 3.30% 71.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 4988495 3.74% 75.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 2616134 1.96% 77.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 29895304 22.43% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 2616133 1.96% 77.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 29895302 22.43% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 133310645 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 133310602 # Number of insts commited each cycle
system.cpu.commit.committedInsts 398664583 # Number of instructions committed
system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction
-system.cpu.commit.bw_lim_events 29895304 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 29895302 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 542989019 # The number of ROB reads
+system.cpu.rob.rob_reads 542988978 # The number of ROB reads
system.cpu.rob.rob_writes 884890973 # The number of ROB writes
-system.cpu.timesIdled 3471 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 266913 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.timesIdled 3472 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 266956 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 375574808 # Number of Instructions Simulated
system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 0.370907 # CPI: Cycles Per Instruction
system.cpu.fp_regfile_writes 105579710 # number of floating regfile writes
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 8238478 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 5089 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 5089 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 674 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8182 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9076 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 17258 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261824 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312000 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 573824 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 573824 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261824 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312000 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 573824 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 8966 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 8966 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 8966 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 5157000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 6787250 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 6787000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 6699750 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 6700000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.icache.tags.replacements 2164 # number of replacements
-system.cpu.icache.tags.tagsinuse 1832.364341 # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse 1832.364308 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 51272145 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 4091 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 12532.912491 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1832.364341 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst 1832.364308 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.894709 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.894709 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id
system.cpu.icache.demand_misses::total 5678 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 5678 # number of overall misses
system.cpu.icache.overall_misses::total 5678 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 339990499 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 339990499 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 339990499 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 339990499 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 339990499 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 339990499 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 340036249 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 340036249 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 340036249 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 340036249 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 340036249 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 340036249 # number of overall miss cycles
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_mshr_misses::total 4201 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4201 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4201 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67699250 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 67699250 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 236024500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 236024500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 303723750 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 303723750 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 303723750 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 303723750 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67663750 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 67663750 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 235941750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 235941750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 303605500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 303605500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 303605500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 303605500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67834.919840 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67834.919840 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73688.573213 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73688.573213 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72297.964770 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 72297.964770 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72297.964770 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 72297.964770 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67799.348697 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67799.348697 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73662.738058 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73662.738058 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72269.816710 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 72269.816710 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72269.816710 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 72269.816710 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 199332411500 # Number of ticks simulated
final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3159999 # Simulator instruction rate (inst/s)
-host_op_rate 3159998 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1579999901 # Simulator tick rate (ticks/s)
-host_mem_usage 261616 # Number of bytes of host memory used
-host_seconds 126.16 # Real time elapsed on the host
+host_inst_rate 2820224 # Simulator instruction rate (inst/s)
+host_op_rate 2820224 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1410112599 # Simulator tick rate (ticks/s)
+host_mem_usage 285836 # Number of bytes of host memory used
+host_seconds 141.36 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7999996548 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5793368275 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13793364824 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 13793364824 # Throughput (bytes/s)
-system.membus.data_through_bus 2749464673 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 493419140 # Transaction distribution
+system.membus.trans_dist::ReadResp 493419140 # Transaction distribution
+system.membus.trans_dist::WriteReq 73520729 # Transaction distribution
+system.membus.trans_dist::WriteResp 73520729 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 797329302 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336550436 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1133879738 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1594658604 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1154806069 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 2749464673 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 566939869 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.703187 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.456853 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 168275218 29.68% 29.68% # Request fanout histogram
+system.membus.snoop_fanout::1 398664651 70.32% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 566939869 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
sim_ticks 567335093000 # Number of ticks simulated
final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1556013 # Simulator instruction rate (inst/s)
-host_op_rate 1556013 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2214344764 # Simulator tick rate (ticks/s)
-host_mem_usage 270340 # Number of bytes of host memory used
-host_seconds 256.21 # Real time elapsed on the host
+host_inst_rate 1606485 # Simulator instruction rate (inst/s)
+host_op_rate 1606484 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2286169690 # Simulator tick rate (ticks/s)
+host_mem_usage 295576 # Number of bytes of host memory used
+host_seconds 248.16 # Real time elapsed on the host
sim_insts 398664609 # Number of instructions simulated
sim_ops 398664609 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 361550 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 447735 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 809285 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 809285 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 4032 # Transaction distribution
system.membus.trans_dist::ReadResp 4032 # Transaction distribution
system.membus.trans_dist::ReadExReq 3142 # Transaction distribution
system.membus.trans_dist::ReadExResp 3142 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 459136 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 7174 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 7174 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 7174 # Request fanout histogram
system.membus.reqLayer0.occupancy 7174000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 64566000 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 955936 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 4623 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7346 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8953 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 16299 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 235072 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 542336 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 542336 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 235072 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 542336 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 8474 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 8474 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 8474 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4886000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 5509500 # Layer occupancy (ticks)
sim_ticks 212377413000 # Number of ticks simulated
final_tick 212377413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 166098 # Simulator instruction rate (inst/s)
-host_op_rate 199419 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 129195965 # Simulator tick rate (ticks/s)
-host_mem_usage 326468 # Number of bytes of host memory used
-host_seconds 1643.84 # Real time elapsed on the host
+host_inst_rate 164145 # Simulator instruction rate (inst/s)
+host_op_rate 197075 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 127677508 # Simulator tick rate (ticks/s)
+host_mem_usage 316656 # Number of bytes of host memory used
+host_seconds 1663.39 # Real time elapsed on the host
sim_insts 273037856 # Number of instructions simulated
sim_ops 327812213 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bytesPerActivate::896-1023 33 2.20% 88.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 175 11.68% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1498 # Bytes accessed per row activation
-system.physmem.totQLat 52122500 # Total ticks spent queuing
-system.physmem.totMemAccLat 194303750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 52768250 # Total ticks spent queuing
+system.physmem.totMemAccLat 194949500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 6873.60 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 6958.76 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 25623.60 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 25708.76 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 2441586750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 2285139 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 4730 # Transaction distribution
system.membus.trans_dist::ReadResp 4730 # Transaction distribution
system.membus.trans_dist::ReadExReq 2853 # Transaction distribution
system.membus.trans_dist::ReadExResp 2853 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 485312 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 8812000 # Layer occupancy (ticks)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 7583 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 7583 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 7583 # Request fanout histogram
+system.membus.reqLayer0.occupancy 8812500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 70869000 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 70869750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 33146135 # Number of BP lookups
+system.cpu.branchPred.lookups 33146132 # Number of BP lookups
system.cpu.branchPred.condPredicted 17115100 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1582628 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 18038083 # Number of BTB lookups
+system.cpu.branchPred.BTBLookups 18038080 # Number of BTB lookups
system.cpu.branchPred.BTBHits 15622031 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 86.605827 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 86.605842 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 6627212 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 273037856 # Number of instructions committed
system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 4318160 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 4318159 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.555663 # CPI: cycles per instruction
system.cpu.ipc 0.642813 # IPC: instructions per cycle
-system.cpu.tickCycles 420995897 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 3758929 # Total number of cycles that the object has spent stopped
+system.cpu.tickCycles 420995875 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 3758951 # Total number of cycles that the object has spent stopped
system.cpu.icache.tags.replacements 36952 # number of replacements
-system.cpu.icache.tags.tagsinuse 1924.941242 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 73208047 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 1924.941243 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 73208046 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 38889 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 1882.487259 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 1882.487233 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941242 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941243 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.939913 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.939913 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1488 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 146532763 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 146532763 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 73208047 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 73208047 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 73208047 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 73208047 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 73208047 # number of overall hits
-system.cpu.icache.overall_hits::total 73208047 # number of overall hits
+system.cpu.icache.tags.tag_accesses 146532761 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 146532761 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 73208046 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 73208046 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 73208046 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 73208046 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 73208046 # number of overall hits
+system.cpu.icache.overall_hits::total 73208046 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 38890 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 38890 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 38890 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 38890 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 38890 # number of overall misses
system.cpu.icache.overall_misses::total 38890 # number of overall misses
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+system.cpu.dcache.demand_miss_latency::cpu.inst 486008458 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 486008458 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst 486008458 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 486008458 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.inst 86707364 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 86707364 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61600.100726 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 61600.100726 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68666.475316 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 68666.475316 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 66665.095049 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 66665.095049 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61583.030508 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 61583.030508 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68664.274780 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 68664.274780 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 66658.683034 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 66658.683034 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_misses::total 4510 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.inst 4510 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4510 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100713040 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 100713040 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197262500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 197262500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297975540 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 297975540 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297975540 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 297975540 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100686290 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 100686290 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197251750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 197251750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297938040 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 297938040 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297938040 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 297938040 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61372.967703 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61372.967703 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68756.535378 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68756.535378 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61356.666667 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61356.666667 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68752.788428 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68752.788428 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.058843 # Number of seconds simulated
-sim_ticks 58842982000 # Number of ticks simulated
-final_tick 58842982000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.112541 # Number of seconds simulated
+sim_ticks 112540655000 # Number of ticks simulated
+final_tick 112540655000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 157851 # Simulator instruction rate (inst/s)
-host_op_rate 189517 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 34018873 # Simulator tick rate (ticks/s)
-host_mem_usage 327492 # Number of bytes of host memory used
-host_seconds 1729.72 # Real time elapsed on the host
-sim_insts 273036656 # Number of instructions simulated
-sim_ops 327810999 # Number of ops (including micro ops) simulated
+host_inst_rate 123771 # Simulator instruction rate (inst/s)
+host_op_rate 148600 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 51015836 # Simulator tick rate (ticks/s)
+host_mem_usage 322668 # Number of bytes of host memory used
+host_seconds 2205.99 # Real time elapsed on the host
+sim_insts 273037219 # Number of instructions simulated
+sim_ops 327811601 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 189376 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 272128 # Number of bytes read from this memory
-system.physmem.bytes_read::total 461504 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 189376 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 189376 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 2959 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 4252 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 7211 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 3218328 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 4624647 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 7842974 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 3218328 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 3218328 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 3218328 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4624647 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7842974 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 7211 # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst 30592 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 80768 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher 512320 # Number of bytes read from this memory
+system.physmem.bytes_read::total 623680 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 30592 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 30592 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 478 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1262 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher 8005 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 9745 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 271831 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 717678 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher 4552310 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 5541820 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 271831 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 271831 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 271831 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 717678 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher 4552310 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 5541820 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 9745 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 7211 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 9745 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 461504 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 623680 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 461504 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 623680 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 11 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 592 # Per bank write bursts
-system.physmem.perBankRdBursts::1 792 # Per bank write bursts
-system.physmem.perBankRdBursts::2 603 # Per bank write bursts
-system.physmem.perBankRdBursts::3 519 # Per bank write bursts
-system.physmem.perBankRdBursts::4 437 # Per bank write bursts
-system.physmem.perBankRdBursts::5 342 # Per bank write bursts
-system.physmem.perBankRdBursts::6 159 # Per bank write bursts
-system.physmem.perBankRdBursts::7 228 # Per bank write bursts
-system.physmem.perBankRdBursts::8 208 # Per bank write bursts
-system.physmem.perBankRdBursts::9 292 # Per bank write bursts
-system.physmem.perBankRdBursts::10 317 # Per bank write bursts
-system.physmem.perBankRdBursts::11 409 # Per bank write bursts
-system.physmem.perBankRdBursts::12 526 # Per bank write bursts
-system.physmem.perBankRdBursts::13 671 # Per bank write bursts
-system.physmem.perBankRdBursts::14 612 # Per bank write bursts
-system.physmem.perBankRdBursts::15 504 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 803 # Per bank write bursts
+system.physmem.perBankRdBursts::1 999 # Per bank write bursts
+system.physmem.perBankRdBursts::2 769 # Per bank write bursts
+system.physmem.perBankRdBursts::3 645 # Per bank write bursts
+system.physmem.perBankRdBursts::4 618 # Per bank write bursts
+system.physmem.perBankRdBursts::5 484 # Per bank write bursts
+system.physmem.perBankRdBursts::6 251 # Per bank write bursts
+system.physmem.perBankRdBursts::7 363 # Per bank write bursts
+system.physmem.perBankRdBursts::8 300 # Per bank write bursts
+system.physmem.perBankRdBursts::9 432 # Per bank write bursts
+system.physmem.perBankRdBursts::10 486 # Per bank write bursts
+system.physmem.perBankRdBursts::11 534 # Per bank write bursts
+system.physmem.perBankRdBursts::12 696 # Per bank write bursts
+system.physmem.perBankRdBursts::13 850 # Per bank write bursts
+system.physmem.perBankRdBursts::14 782 # Per bank write bursts
+system.physmem.perBankRdBursts::15 733 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 58842848000 # Total gap between requests
+system.physmem.totGap 112540488500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 7211 # Read request sizes (log2)
+system.physmem.readPktSize::6 9745 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 4240 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 2012 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 646 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 244 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 2266 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 1763 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 1065 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 847 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 758 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 667 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 627 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 603 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 528 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 248 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 140 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 95 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 46 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 36 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 31 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 25 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1405 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 327.288256 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 191.332764 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 342.731237 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 492 35.02% 35.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 350 24.91% 59.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 132 9.40% 69.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 82 5.84% 75.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 53 3.77% 78.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 47 3.35% 82.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 27 1.92% 84.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 22 1.57% 85.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 200 14.23% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1405 # Bytes accessed per row activation
-system.physmem.totQLat 59614750 # Total ticks spent queuing
-system.physmem.totMemAccLat 194821000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 36055000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 8267.20 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 1235 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 501.635628 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 310.924046 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 394.932906 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 290 23.48% 23.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 197 15.95% 39.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 103 8.34% 47.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 73 5.91% 53.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 78 6.32% 60.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 75 6.07% 66.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 32 2.59% 68.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 38 3.08% 71.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 349 28.26% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1235 # Bytes accessed per row activation
+system.physmem.totQLat 248191131 # Total ticks spent queuing
+system.physmem.totMemAccLat 430909881 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 48725000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 25468.56 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 27017.20 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 7.84 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 44218.56 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 5.54 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 7.84 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 5.54 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.06 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads
+system.physmem.busUtil 0.04 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 5798 # Number of row buffer hits during reads
+system.physmem.readRowHits 8500 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 80.40 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 87.22 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 8160150.88 # Average gap between requests
-system.physmem.pageHitRate 80.40 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 55121576750 # Time in different power states
-system.physmem.memoryStateTime::REF 1964820000 # Time in different power states
+system.physmem.avgGap 11548536.53 # Average gap between requests
+system.physmem.pageHitRate 87.22 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 107209849499 # Time in different power states
+system.physmem.memoryStateTime::REF 3757780000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 1754568250 # Time in different power states
+system.physmem.memoryStateTime::ACT 1567991501 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 7842974 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 4381 # Transaction distribution
-system.membus.trans_dist::ReadResp 4381 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 11 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 11 # Transaction distribution
-system.membus.trans_dist::ReadExReq 2830 # Transaction distribution
-system.membus.trans_dist::ReadExResp 2830 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14444 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 14444 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 461504 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 461504 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 461504 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 8714000 # Layer occupancy (ticks)
+system.membus.trans_dist::ReadReq 9170 # Transaction distribution
+system.membus.trans_dist::ReadResp 9170 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 1 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 1 # Transaction distribution
+system.membus.trans_dist::ReadExReq 575 # Transaction distribution
+system.membus.trans_dist::ReadExResp 575 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 19492 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 19492 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 623680 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 623680 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 9746 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 9746 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 9746 # Request fanout histogram
+system.membus.reqLayer0.occupancy 11064261 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 67059990 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 88934700 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 36678579 # Number of BP lookups
-system.cpu.branchPred.condPredicted 19369962 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1628976 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 19217639 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 17291098 # Number of BTB hits
+system.cpu.branchPred.lookups 37763717 # Number of BP lookups
+system.cpu.branchPred.condPredicted 20179624 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1746237 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 18664531 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 17302092 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 89.975142 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 7036393 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 5252 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 92.700384 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 7228871 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
-system.cpu.numCycles 117685965 # number of cpu cycles simulated
+system.cpu.numCycles 225081311 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 40172132 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 329927106 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 36678579 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 24327491 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 75600101 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 3327960 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 175 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 2800 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 38768855 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 530996 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 117439229 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 3.389931 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.437439 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 12228964 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 334152318 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 37763717 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 24530963 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 210956137 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 3511516 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 130 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 514 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 89111612 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 21313 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 224941514 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.801835 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.228393 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 46731814 39.79% 39.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 7329854 6.24% 46.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 6574514 5.60% 51.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 6398088 5.45% 57.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 4252484 3.62% 60.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 5520861 4.70% 65.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 3987559 3.40% 68.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 3254311 2.77% 71.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 33389744 28.43% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 51202945 22.76% 22.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 42808370 19.03% 41.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 30291484 13.47% 55.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 100638715 44.74% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 117439229 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.311665 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.803453 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 34271331 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 16148849 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 61039844 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 4384832 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1594373 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 7530126 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 70364 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 389722126 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 437543 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1594373 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 37031203 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 5569218 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 387986 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 62601924 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 10254525 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 382340457 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 4583661 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 2043172 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 2989050 # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents 65700 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 432935056 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 2729953830 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 376601971 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 209126886 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 372229219 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 60705837 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 14453 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 15060 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 19856485 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 96101144 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 93882304 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 9920575 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 10878783 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 370378331 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 25182 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 358744041 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1234352 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 42331510 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 132428138 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 3062 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 117439229 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 3.054721 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.223263 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 224941514 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.167778 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.484585 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 27726149 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 64007988 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 108311612 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 23274772 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1620993 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 6880386 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 135232 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 363491063 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 6273375 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1620993 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 45185790 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 13191872 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 337791 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 113472399 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 51132669 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 355733781 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 2913620 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 6683703 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 151097 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 7653475 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 21162184 # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents 7934136 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 403386511 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 2533827094 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 350198229 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 194873795 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 31156460 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 17017 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 17054 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 55398119 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 92429190 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 88465233 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1673754 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1845335 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 353207304 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 28026 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 346267862 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 2344729 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 24807728 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 73571108 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 5906 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 224941514 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.539368 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.101787 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 21274018 18.11% 18.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 14280801 12.16% 30.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 14869023 12.66% 42.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 13830819 11.78% 54.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 20620243 17.56% 72.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 15076681 12.84% 85.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 10030176 8.54% 93.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 4472440 3.81% 97.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 2985028 2.54% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 40716883 18.10% 18.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 78348178 34.83% 52.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 60751241 27.01% 79.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 34738398 15.44% 95.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 9740749 4.33% 99.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 637378 0.28% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 8687 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 117439229 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 224941514 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 30566 0.13% 0.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 5035 0.02% 0.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 218902 0.91% 1.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 207576 0.86% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 15328 0.06% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 1824 0.01% 1.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 338916 1.41% 3.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 30886 0.13% 3.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 130712 0.54% 4.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 13684069 56.78% 60.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 9438097 39.16% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 9315738 7.51% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 7336 0.01% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 233465 0.19% 7.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 152519 0.12% 7.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 103426 0.08% 7.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 37180 0.03% 7.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 820096 0.66% 8.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 318386 0.26% 8.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 687826 0.55% 9.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 53407084 43.05% 52.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 58973857 47.54% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 114997382 32.06% 32.06% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 2177572 0.61% 32.66% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 6789188 1.89% 34.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 8562613 2.39% 36.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 3491505 0.97% 37.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 1605361 0.45% 38.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 21185799 5.91% 44.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 7196318 2.01% 46.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147739 1.99% 48.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 183217 0.05% 48.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 95472748 26.61% 74.93% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 89934599 25.07% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 110648843 31.95% 31.95% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 2148167 0.62% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 6796997 1.96% 34.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 8667397 2.50% 37.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 3331873 0.96% 38.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 1592437 0.46% 38.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 20937214 6.05% 44.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 7180794 2.07% 46.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147102 2.06% 48.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.70% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 91783348 26.51% 75.20% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 85858404 24.80% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 358744041 # Type of FU issued
-system.cpu.iq.rate 3.048316 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 24101911 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.067184 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 600140343 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 274631052 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 231134438 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 260123231 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 138160310 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 119811956 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 246702850 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 136143102 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 13691987 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 346267862 # Type of FU issued
+system.cpu.iq.rate 1.538412 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 124056913 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.358269 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 756613481 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 251259921 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 223227498 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 287265399 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 126793827 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 117417697 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 302953956 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 167370819 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 5034316 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 10368919 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 114059 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 68397 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 11506726 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 6696915 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 13655 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 10694 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 6089616 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 1395971 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 850 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 151174 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 488913 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1594373 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 4558099 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 129859 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 370404619 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1080086 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 96101144 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 93882304 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 14149 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 21825 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 109033 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 68397 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1241378 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 435662 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1677040 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 354745077 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 94263609 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 3998964 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 1620993 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 2123091 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 319754 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 353236194 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 92429190 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 88465233 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 16993 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 8080 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 327488 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 10694 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1220289 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 438322 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1658611 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 342304940 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 90585369 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 3962922 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1106 # number of nop insts executed
-system.cpu.iew.exec_refs 182843438 # number of memory reference insts executed
-system.cpu.iew.exec_branches 32405794 # Number of branches executed
-system.cpu.iew.exec_stores 88579829 # Number of stores executed
-system.cpu.iew.exec_rate 3.014336 # Inst execution rate
-system.cpu.iew.wb_sent 352024494 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 350946394 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 175212964 # num instructions producing a value
-system.cpu.iew.wb_consumers 355804607 # num instructions consuming a value
+system.cpu.iew.exec_nop 864 # number of nop insts executed
+system.cpu.iew.exec_refs 175168098 # number of memory reference insts executed
+system.cpu.iew.exec_branches 31752179 # Number of branches executed
+system.cpu.iew.exec_stores 84582729 # Number of stores executed
+system.cpu.iew.exec_rate 1.520806 # Inst execution rate
+system.cpu.iew.wb_sent 340904975 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 340645195 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 153543382 # num instructions producing a value
+system.cpu.iew.wb_consumers 265817565 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.982058 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.492442 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.513432 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.577627 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 42598489 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 23000910 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1559369 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 111323846 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.944667 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.904010 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1611472 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 221213350 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.481883 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.053410 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 29334492 26.35% 26.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 21002495 18.87% 45.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 12438899 11.17% 56.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 8843852 7.94% 64.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 8943359 8.03% 72.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 5286497 4.75% 77.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 3580965 3.22% 80.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3438245 3.09% 83.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 18455042 16.58% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 87832177 39.70% 39.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 69867778 31.58% 71.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 20927331 9.46% 80.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 13474141 6.09% 86.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 8800060 3.98% 90.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 4584952 2.07% 92.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 2913270 1.32% 94.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 2446398 1.11% 95.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 10367243 4.69% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 111323846 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 273037268 # Number of instructions committed
-system.cpu.commit.committedOps 327811611 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 221213350 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 273037831 # Number of instructions committed
+system.cpu.commit.committedOps 327812213 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 168107803 # Number of memory references committed
-system.cpu.commit.loads 85732225 # Number of loads committed
+system.cpu.commit.refs 168107892 # Number of memory references committed
+system.cpu.commit.loads 85732275 # Number of loads committed
system.cpu.commit.membars 11033 # Number of memory barriers committed
-system.cpu.commit.branches 30563485 # Number of branches committed
+system.cpu.commit.branches 30563525 # Number of branches committed
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 258331174 # Number of committed integer instructions.
-system.cpu.commit.function_calls 6225112 # Number of function calls committed.
+system.cpu.commit.int_insts 258331704 # Number of committed integer instructions.
+system.cpu.commit.function_calls 6225114 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 104312045 31.82% 31.82% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 2145845 0.65% 32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 104312486 31.82% 31.82% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 85732225 26.15% 74.87% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 82375578 25.13% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 327811611 # Class of committed instruction
-system.cpu.commit.bw_lim_events 18455042 # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total 327812213 # Class of committed instruction
+system.cpu.commit.bw_lim_events 10367243 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 463276381 # The number of ROB reads
-system.cpu.rob.rob_writes 746948197 # The number of ROB writes
-system.cpu.timesIdled 5570 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 246736 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 273036656 # Number of Instructions Simulated
-system.cpu.committedOps 327810999 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.431026 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.431026 # CPI: Total CPI of All Threads
-system.cpu.ipc 2.320044 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 2.320044 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 344698387 # number of integer regfile reads
-system.cpu.int_regfile_writes 141985623 # number of integer regfile writes
-system.cpu.fp_regfile_reads 189510679 # number of floating regfile reads
-system.cpu.fp_regfile_writes 134618624 # number of floating regfile writes
-system.cpu.cc_regfile_reads 1340695625 # number of cc regfile reads
-system.cpu.cc_regfile_writes 80827327 # number of cc regfile writes
-system.cpu.misc_regfile_reads 1216328122 # number of misc regfile reads
+system.cpu.rob.rob_reads 561656707 # The number of ROB reads
+system.cpu.rob.rob_writes 705358338 # The number of ROB writes
+system.cpu.timesIdled 49342 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 139797 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 273037219 # Number of Instructions Simulated
+system.cpu.committedOps 327811601 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 0.824361 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.824361 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.213060 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.213060 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 331187238 # number of integer regfile reads
+system.cpu.int_regfile_writes 136909181 # number of integer regfile writes
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+system.cpu.cc_regfile_writes 80246596 # number of cc regfile writes
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system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 23209157 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 17471 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 17471 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 1022 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 12 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 12 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 2846 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 2846 # Transaction distribution
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-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10234 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 41666 # Packet count per connected master and slave (bytes)
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-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 359424 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 1364800 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 1364800 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 896 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 11697999 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 24104992 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 7380470 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.icache.tags.replacements 13841 # number of replacements
-system.cpu.icache.tags.tagsinuse 1830.861112 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 38751311 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 15711 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 2466.508243 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1830.861112 # Average occupied blocks per requestor
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-system.cpu.icache.tags.age_task_id_blocks_1024::4 1522 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.913086 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 77553427 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 77553427 # Number of data accesses
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-system.cpu.icache.ReadReq_hits::total 38751328 # number of ReadReq hits
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-system.cpu.icache.demand_hits::total 38751328 # number of demand (read+write) hits
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-system.cpu.icache.overall_hits::total 38751328 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 17524 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 17524 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 17524 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 17524 # number of overall misses
-system.cpu.icache.overall_misses::total 17524 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 439561740 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 439561740 # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::total 439561740 # number of demand (read+write) miss cycles
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-system.cpu.icache.overall_miss_latency::total 439561740 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 38768852 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 38768852 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total 38768852 # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total 38768852 # number of overall (read+write) accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::total 25083.413604 # average ReadReq miss latency
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-system.cpu.icache.demand_avg_miss_latency::total 25083.413604 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 25083.413604 # average overall miss latency
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+system.cpu.toL2Bus.snoops 50213 # Total snoops (count)
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+system.cpu.toL2Bus.snoop_fanout::total 3265775 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 2574531466 # Layer occupancy (ticks)
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+system.cpu.toL2Bus.respLayer0.occupancy 1074172389 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%)
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+system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%)
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+system.cpu.icache.tags.tagsinuse 511.871967 # Cycle average of tags in use
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+system.cpu.icache.tags.sampled_refs 715880 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 123.472951 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 275609500 # Cycle when the warmup percentage was hit.
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system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1801 # number of ReadReq MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses::total 15723 # number of ReadReq MSHR misses
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-system.cpu.icache.overall_mshr_miss_latency::total 350218008 # number of overall MSHR miss cycles
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-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000406 # mshr miss rate for ReadReq accesses
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-system.cpu.icache.demand_mshr_miss_rate::total 0.000406 # mshr miss rate for demand accesses
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-system.cpu.icache.overall_mshr_miss_rate::total 0.000406 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22274.248426 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22274.248426 # average ReadReq mshr miss latency
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-system.cpu.icache.demand_avg_mshr_miss_latency::total 22274.248426 # average overall mshr miss latency
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+system.cpu.icache.ReadReq_mshr_miss_latency::total 4688303087 # number of ReadReq MSHR miss cycles
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+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008034 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 161647490 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 161647490 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 161734575 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 161734575 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000051 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000459 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.000459 # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000180 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000180 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000163 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000163 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000163 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000163 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57825.873861 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 57825.873861 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58078.251000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 58078.251000 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 58039.303437 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 58039.303437 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 57951.171475 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 57951.171475 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 32404 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 1444 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 548 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.131387 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 103.142857 # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 167482805 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 167482805 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 167553253 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 167553253 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.031652 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.031652 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013012 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.013012 # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000270 # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.000270 # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.022520 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.022520 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.022510 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.022510 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7915.462900 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 7915.462900 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7815.826402 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 7815.826402 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32900 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32900 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 7887.259037 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 7887.259037 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 7887.219304 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 7887.219304 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 761243 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 111844 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.500000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 6.806293 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1022 # number of writebacks
-system.cpu.dcache.writebacks::total 1022 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2332 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 2332 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19388 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 19388 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 21720 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 21720 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 21720 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 21720 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1727 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2855 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 2855 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 24 # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 4582 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 4582 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 4606 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 4606 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109924790 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 109924790 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 205574740 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 205574740 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1745000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1745000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 315499530 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 315499530 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317244530 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 317244530 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000276 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000276 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63650.718008 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63650.718008 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72005.162872 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72005.162872 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 72708.333333 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 72708.333333 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68856.292012 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68856.292012 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68876.363439 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68876.363439 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 966282 # number of writebacks
+system.cpu.dcache.writebacks::total 966282 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1390265 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 1390265 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 847147 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 847147 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 2237412 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 2237412 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 2237412 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 2237412 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313761 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1313761 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220488 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 220488 # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1534249 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1534249 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1534260 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1534260 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9295842016 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 9295842016 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1592020910 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 1592020910 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 638250 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 638250 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10887862926 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10887862926 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10888501176 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10888501176 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015378 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015378 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002687 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002687 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009161 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.009161 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009157 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.009157 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7075.748189 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7075.748189 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7220.442428 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7220.442428 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58022.727273 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58022.727273 # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7096.542299 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 7096.542299 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7096.907419 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 7096.907419 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 201717313500 # Number of ticks simulated
final_tick 201717313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1169681 # Simulator instruction rate (inst/s)
-host_op_rate 1404332 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 864148101 # Simulator tick rate (ticks/s)
-host_mem_usage 314684 # Number of bytes of host memory used
-host_seconds 233.43 # Real time elapsed on the host
+host_inst_rate 1306299 # Simulator instruction rate (inst/s)
+host_op_rate 1568357 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 965080142 # Simulator tick rate (ticks/s)
+host_mem_usage 305108 # Number of bytes of host memory used
+host_seconds 209.02 # Real time elapsed on the host
sim_insts 273037594 # Number of instructions simulated
sim_ops 327811949 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 6913839312 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4366293422 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11280132734 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 11280132734 # Throughput (bytes/s)
-system.membus.data_through_bus 2275398071 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 434895827 # Transaction distribution
+system.membus.trans_dist::ReadResp 434906722 # Transaction distribution
+system.membus.trans_dist::WriteReq 82052672 # Transaction distribution
+system.membus.trans_dist::WriteResp 82052672 # Transaction distribution
+system.membus.trans_dist::SoftPFReq 54062 # Transaction distribution
+system.membus.trans_dist::SoftPFResp 54062 # Transaction distribution
+system.membus.trans_dist::LoadLockedReq 10895 # Transaction distribution
+system.membus.trans_dist::StoreCondReq 10895 # Transaction distribution
+system.membus.trans_dist::StoreCondResp 10895 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320546 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1034048702 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641092 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 2275398071 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 517024351 # Request fanout histogram
+system.membus.snoop_fanout::mean 4.674359 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::4 168364078 32.56% 32.56% # Request fanout histogram
+system.membus.snoop_fanout::5 348660273 67.44% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 4 # Request fanout histogram
+system.membus.snoop_fanout::max_value 5 # Request fanout histogram
+system.membus.snoop_fanout::total 517024351 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
sim_ticks 517235411000 # Number of ticks simulated
final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 749544 # Simulator instruction rate (inst/s)
-host_op_rate 899855 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1421469107 # Simulator tick rate (ticks/s)
-host_mem_usage 324416 # Number of bytes of host memory used
-host_seconds 363.87 # Real time elapsed on the host
+host_inst_rate 795879 # Simulator instruction rate (inst/s)
+host_op_rate 955482 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1509341441 # Simulator tick rate (ticks/s)
+host_mem_usage 314596 # Number of bytes of host memory used
+host_seconds 342.69 # Real time elapsed on the host
sim_insts 272739285 # Number of instructions simulated
sim_ops 327433743 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 322824 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 522532 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 845356 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 3976 # Transaction distribution
system.membus.trans_dist::ReadResp 3976 # Transaction distribution
system.membus.trans_dist::ReadExReq 2856 # Transaction distribution
system.membus.trans_dist::ReadExResp 2856 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 437248 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 6833 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 6833 # Request fanout histogram
system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 2608205 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31206 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9954 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 41160 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 1349056 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 21079 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 21079 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 21079 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks)
---------- Begin Simulation Statistics ----------
-sim_seconds 0.555548 # Number of seconds simulated
-sim_ticks 555548307000 # Number of ticks simulated
-final_tick 555548307000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.555533 # Number of seconds simulated
+sim_ticks 555532734000 # Number of ticks simulated
+final_tick 555532734000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 201077 # Simulator instruction rate (inst/s)
-host_op_rate 201077 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 120272803 # Simulator tick rate (ticks/s)
-host_mem_usage 246132 # Number of bytes of host memory used
-host_seconds 4619.07 # Real time elapsed on the host
+host_inst_rate 337976 # Simulator instruction rate (inst/s)
+host_op_rate 337976 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 202152446 # Simulator tick rate (ticks/s)
+host_mem_usage 300884 # Number of bytes of host memory used
+host_seconds 2748.09 # Real time elapsed on the host
sim_insts 928789150 # Number of instructions simulated
sim_ops 928789150 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.num_reads::total 291518 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 33583312 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 33583312 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 336043 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 336043 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 7681982 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 7681982 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 7681982 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 33583312 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 41265294 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 33584253 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 33584253 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 336052 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 336052 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 7682197 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 7682197 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 7682197 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 33584253 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 41266450 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 291518 # Number of read requests accepted
system.physmem.writeReqs 66683 # Number of write requests accepted
system.physmem.readBursts 291518 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 18639168 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 17984 # Total number of bytes read from write queue
-system.physmem.bytesWritten 4266304 # Total number of bytes written to DRAM
+system.physmem.bytesReadDRAM 18640064 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 17088 # Total number of bytes read from write queue
+system.physmem.bytesWritten 4266624 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 18657152 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 281 # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ 267 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 17934 # Per bank write bursts
-system.physmem.perBankRdBursts::1 18286 # Per bank write bursts
+system.physmem.perBankRdBursts::0 17939 # Per bank write bursts
+system.physmem.perBankRdBursts::1 18284 # Per bank write bursts
system.physmem.perBankRdBursts::2 18304 # Per bank write bursts
-system.physmem.perBankRdBursts::3 18252 # Per bank write bursts
-system.physmem.perBankRdBursts::4 18169 # Per bank write bursts
-system.physmem.perBankRdBursts::5 18242 # Per bank write bursts
-system.physmem.perBankRdBursts::6 18316 # Per bank write bursts
-system.physmem.perBankRdBursts::7 18295 # Per bank write bursts
+system.physmem.perBankRdBursts::3 18254 # Per bank write bursts
+system.physmem.perBankRdBursts::4 18163 # Per bank write bursts
+system.physmem.perBankRdBursts::5 18248 # Per bank write bursts
+system.physmem.perBankRdBursts::6 18324 # Per bank write bursts
+system.physmem.perBankRdBursts::7 18299 # Per bank write bursts
system.physmem.perBankRdBursts::8 18226 # Per bank write bursts
-system.physmem.perBankRdBursts::9 18227 # Per bank write bursts
-system.physmem.perBankRdBursts::10 18210 # Per bank write bursts
-system.physmem.perBankRdBursts::11 18385 # Per bank write bursts
-system.physmem.perBankRdBursts::12 18260 # Per bank write bursts
-system.physmem.perBankRdBursts::13 18048 # Per bank write bursts
+system.physmem.perBankRdBursts::9 18226 # Per bank write bursts
+system.physmem.perBankRdBursts::10 18216 # Per bank write bursts
+system.physmem.perBankRdBursts::11 18389 # Per bank write bursts
+system.physmem.perBankRdBursts::12 18256 # Per bank write bursts
+system.physmem.perBankRdBursts::13 18039 # Per bank write bursts
system.physmem.perBankRdBursts::14 17980 # Per bank write bursts
-system.physmem.perBankRdBursts::15 18103 # Per bank write bursts
+system.physmem.perBankRdBursts::15 18104 # Per bank write bursts
system.physmem.perBankWrBursts::0 4125 # Per bank write bursts
system.physmem.perBankWrBursts::1 4164 # Per bank write bursts
system.physmem.perBankWrBursts::2 4223 # Per bank write bursts
system.physmem.perBankWrBursts::6 4262 # Per bank write bursts
system.physmem.perBankWrBursts::7 4226 # Per bank write bursts
system.physmem.perBankWrBursts::8 4233 # Per bank write bursts
-system.physmem.perBankWrBursts::9 4185 # Per bank write bursts
+system.physmem.perBankWrBursts::9 4190 # Per bank write bursts
system.physmem.perBankWrBursts::10 4150 # Per bank write bursts
system.physmem.perBankWrBursts::11 4241 # Per bank write bursts
system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
system.physmem.perBankWrBursts::15 4157 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 555548231500 # Total gap between requests
+system.physmem.totGap 555532658500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 66683 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 290743 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 468 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 290760 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 465 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 970 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 970 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 4046 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 4046 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 4046 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 4046 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 4046 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 4045 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 4045 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 4045 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 4045 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 4045 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 4048 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 981 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 4044 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 4044 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 4044 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 4044 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 4044 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 4044 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 4044 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 4044 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 4044 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 4044 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 4046 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 4045 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 4045 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 4045 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 4045 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 4045 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 4044 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 4044 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 4044 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 4044 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 104858 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 218.415915 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 140.780585 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 268.040689 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 39691 37.85% 37.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 43831 41.80% 79.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 8352 7.97% 87.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 1265 1.21% 88.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 732 0.70% 89.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 905 0.86% 90.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1060 1.01% 91.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 884 0.84% 92.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 8138 7.76% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 104858 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 4045 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 70.322621 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean 36.136998 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 770.555291 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 4038 99.83% 99.83% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-12287 1 0.02% 99.85% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.88% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 105079 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 217.968119 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 139.907625 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 270.030152 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 40113 38.17% 38.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 44071 41.94% 80.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 8455 8.05% 88.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 717 0.68% 88.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 543 0.52% 89.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 672 0.64% 90.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1241 1.18% 91.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1153 1.10% 92.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 8114 7.72% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 105079 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 4044 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 71.423096 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean 36.196398 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 785.521839 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 4037 99.83% 99.83% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-14335 2 0.05% 99.88% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-16383 3 0.07% 99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::16384-18431 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 4045 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 4045 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.479852 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.458537 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.855483 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 3076 76.04% 76.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 966 23.88% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 4045 # Writes before turning the bus around for reads
-system.physmem.totQLat 2434432250 # Total ticks spent queuing
-system.physmem.totMemAccLat 7895126000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1456185000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 8358.94 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 4044 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 4044 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.485163 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.463667 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 0.859123 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 3065 75.79% 75.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 975 24.11% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 4 0.10% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 4044 # Writes before turning the bus around for reads
+system.physmem.totQLat 2419619750 # Total ticks spent queuing
+system.physmem.totMemAccLat 7880576000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1456255000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 8307.68 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 27108.94 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 27057.68 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 33.55 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 7.68 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 33.58 # Average system read bandwidth in MiByte/s
system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing
-system.physmem.readRowHits 202612 # Number of row buffer hits during reads
-system.physmem.writeRowHits 50417 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 69.57 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 75.61 # Row buffer hit rate for writes
-system.physmem.avgGap 1550939.92 # Average gap between requests
-system.physmem.pageHitRate 70.69 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 275426566250 # Time in different power states
-system.physmem.memoryStateTime::REF 18550740000 # Time in different power states
+system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing
+system.physmem.readRowHits 202343 # Number of row buffer hits during reads
+system.physmem.writeRowHits 50484 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 69.47 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 75.71 # Row buffer hit rate for writes
+system.physmem.avgGap 1550896.45 # Average gap between requests
+system.physmem.pageHitRate 70.64 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 275459224750 # Time in different power states
+system.physmem.memoryStateTime::REF 18550220000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 261564123750 # Time in different power states
+system.physmem.memoryStateTime::ACT 261516412250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 41265294 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 224874 # Transaction distribution
system.membus.trans_dist::ReadResp 224874 # Transaction distribution
system.membus.trans_dist::Writeback 66683 # Transaction distribution
system.membus.trans_dist::ReadExResp 66644 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649719 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 649719 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22924864 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 22924864 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 22924864 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 954576500 # Layer occupancy (ticks)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22924864 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 22924864 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 358201 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 358201 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 358201 # Request fanout histogram
+system.membus.reqLayer0.occupancy 954482500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2724054750 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2723745500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 125108663 # Number of BP lookups
-system.cpu.branchPred.condPredicted 80505378 # Number of conditional branches predicted
+system.cpu.branchPred.condPredicted 80505376 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 12157226 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 103330872 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 82874855 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 103330871 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 82874854 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 80.203383 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 18690214 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.usedRAS 18690215 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 9442 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.data_misses 205618 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 336048246 # DTB accesses
-system.cpu.itb.fetch_hits 315070348 # ITB hits
+system.cpu.itb.fetch_hits 315070347 # ITB hits
system.cpu.itb.fetch_misses 120 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 315070468 # ITB accesses
+system.cpu.itb.fetch_accesses 315070467 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 37 # Number of system calls
-system.cpu.numCycles 1111096614 # number of cpu cycles simulated
+system.cpu.numCycles 1111065468 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 928789150 # Number of instructions committed
system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 23870770 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 23870771 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.196285 # CPI: cycles per instruction
-system.cpu.ipc 0.835921 # IPC: instructions per cycle
+system.cpu.cpi 1.196252 # CPI: cycles per instruction
+system.cpu.ipc 0.835945 # IPC: instructions per cycle
system.cpu.tickCycles 1052548202 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 58548412 # Total number of cycles that the object has spent stopped
+system.cpu.idleCycles 58517266 # Total number of cycles that the object has spent stopped
system.cpu.icache.tags.replacements 10608 # number of replacements
-system.cpu.icache.tags.tagsinuse 1686.445112 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 315057997 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 1686.446779 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 315057996 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 12350 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 25510.768988 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 25510.768907 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1686.445112 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst 1686.446779 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.823460 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.823460 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1742 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1572 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 630153046 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 630153046 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 315057997 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 315057997 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 315057997 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 315057997 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 315057997 # number of overall hits
-system.cpu.icache.overall_hits::total 315057997 # number of overall hits
+system.cpu.icache.tags.tag_accesses 630153044 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 630153044 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 315057996 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 315057996 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 315057996 # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::cpu.inst 315057996 # number of overall hits
+system.cpu.icache.overall_hits::total 315057996 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 12351 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 12351 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 12351 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 12351 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 12351 # number of overall misses
system.cpu.icache.overall_misses::total 12351 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 334622500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 334622500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 334622500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 334622500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 334622500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 334622500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 315070348 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 315070348 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 315070348 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 315070348 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 315070348 # number of overall (read+write) accesses
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+system.cpu.icache.overall_miss_latency::cpu.inst 334498250 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 334498250 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 315070347 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000039 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000039 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000039 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000039 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000039 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000039 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27092.745527 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 27092.745527 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 27092.745527 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 27092.745527 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 27092.745527 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 27092.745527 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27082.685613 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 27082.685613 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 27082.685613 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 27082.685613 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 27082.685613 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 27082.685613 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 12351 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 12351 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 12351 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 308669500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 308669500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 308669500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 308669500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 308669500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 308669500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 308545750 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 308545750 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 308545750 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 308545750 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 308545750 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 308545750 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24991.458182 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24991.458182 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24991.458182 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 24991.458182 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24991.458182 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 24991.458182 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24981.438750 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24981.438750 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24981.438750 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 24981.438750 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24981.438750 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 24981.438750 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 101892158 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 723971 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 723970 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 91489 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24701 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652749 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1677450 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790400 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815616 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 56606016 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 56606016 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790400 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815616 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 56606016 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 884470 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 884470 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 884470 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 533724000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 19151500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 19151250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1222065750 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 1221989250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.cpu.l2cache.tags.replacements 258739 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 32601.591220 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 32601.629306 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 523854 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 291475 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 1.797252 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 2866.071604 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.519616 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.087466 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907456 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.994922 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 2865.774027 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.855280 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.087456 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907466 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.994923 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id
system.cpu.l2cache.demand_misses::total 291519 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 291519 # number of overall misses
system.cpu.l2cache.overall_misses::total 291519 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15957253750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 15957253750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4332290500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 4332290500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 20289544250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 20289544250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 20289544250 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 20289544250 # number of overall miss cycles
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+system.cpu.l2cache.demand_miss_latency::total 20274442500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 20274442500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 20274442500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 723971 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 723971 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 91489 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.demand_miss_rate::total 0.367624 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.367624 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.367624 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70960.550306 # average ReadReq miss latency
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system.cpu.dcache.tags.replacements 776534 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4092.879870 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 322859768 # Total number of references to valid blocks.
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system.cpu.dcache.tags.warmup_cycle 839965250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.879870 # Average occupied blocks per requestor
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system.cpu.dcache.tags.occ_percent::total 0.999238 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1254 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1629 # Occupied blocks per task id
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003157 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003157 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002412 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002412 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002412 # mshr miss rate for overall accesses
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.278171 # Number of seconds simulated
-sim_ticks 278170874500 # Number of ticks simulated
-final_tick 278170874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.278139 # Number of seconds simulated
+sim_ticks 278139424500 # Number of ticks simulated
+final_tick 278139424500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 125961 # Simulator instruction rate (inst/s)
-host_op_rate 125961 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 41594749 # Simulator tick rate (ticks/s)
-host_mem_usage 247184 # Number of bytes of host memory used
-host_seconds 6687.64 # Real time elapsed on the host
+host_inst_rate 187672 # Simulator instruction rate (inst/s)
+host_op_rate 187672 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 61966028 # Simulator tick rate (ticks/s)
+host_mem_usage 301896 # Number of bytes of host memory used
+host_seconds 4488.58 # Real time elapsed on the host
sim_insts 842382029 # Number of instructions simulated
sim_ops 842382029 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 176000 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 18476352 # Number of bytes read from this memory
-system.physmem.bytes_read::total 18652352 # Number of bytes read from this memory
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-system.physmem.bytes_inst_read::total 176000 # Number of instructions bytes read from this memory
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+system.physmem.bytes_read::total 18653120 # Number of bytes read from this memory
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+system.physmem.bytes_inst_read::total 175936 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory
system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2750 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 288693 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 291443 # Number of read requests responded to by this memory
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+system.physmem.num_reads::total 291455 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 632705 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 66420872 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 67053576 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 632705 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 632705 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 15342052 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 15342052 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 15342052 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 632705 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 66420872 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 82395628 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 291443 # Number of read requests accepted
+system.physmem.bw_read::cpu.inst 632546 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 66431374 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 67063920 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 632546 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 632546 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 15343787 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 15343787 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 15343787 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 632546 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 66431374 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 82407706 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 291455 # Number of read requests accepted
system.physmem.writeReqs 66683 # Number of write requests accepted
-system.physmem.readBursts 291443 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 291455 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 18634688 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 17664 # Total number of bytes read from write queue
-system.physmem.bytesWritten 4265728 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 18652352 # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM 18634176 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 18944 # Total number of bytes read from write queue
+system.physmem.bytesWritten 4266304 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 18653120 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 276 # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ 296 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 17914 # Per bank write bursts
-system.physmem.perBankRdBursts::1 18261 # Per bank write bursts
-system.physmem.perBankRdBursts::2 18310 # Per bank write bursts
+system.physmem.perBankRdBursts::0 17915 # Per bank write bursts
+system.physmem.perBankRdBursts::1 18264 # Per bank write bursts
+system.physmem.perBankRdBursts::2 18305 # Per bank write bursts
system.physmem.perBankRdBursts::3 18245 # Per bank write bursts
-system.physmem.perBankRdBursts::4 18158 # Per bank write bursts
-system.physmem.perBankRdBursts::5 18234 # Per bank write bursts
-system.physmem.perBankRdBursts::6 18318 # Per bank write bursts
-system.physmem.perBankRdBursts::7 18307 # Per bank write bursts
-system.physmem.perBankRdBursts::8 18230 # Per bank write bursts
-system.physmem.perBankRdBursts::9 18222 # Per bank write bursts
+system.physmem.perBankRdBursts::4 18154 # Per bank write bursts
+system.physmem.perBankRdBursts::5 18231 # Per bank write bursts
+system.physmem.perBankRdBursts::6 18323 # Per bank write bursts
+system.physmem.perBankRdBursts::7 18314 # Per bank write bursts
+system.physmem.perBankRdBursts::8 18231 # Per bank write bursts
+system.physmem.perBankRdBursts::9 18221 # Per bank write bursts
system.physmem.perBankRdBursts::10 18215 # Per bank write bursts
-system.physmem.perBankRdBursts::11 18386 # Per bank write bursts
-system.physmem.perBankRdBursts::12 18247 # Per bank write bursts
-system.physmem.perBankRdBursts::13 18053 # Per bank write bursts
+system.physmem.perBankRdBursts::11 18383 # Per bank write bursts
+system.physmem.perBankRdBursts::12 18244 # Per bank write bursts
+system.physmem.perBankRdBursts::13 18043 # Per bank write bursts
system.physmem.perBankRdBursts::14 17967 # Per bank write bursts
-system.physmem.perBankRdBursts::15 18100 # Per bank write bursts
+system.physmem.perBankRdBursts::15 18104 # Per bank write bursts
system.physmem.perBankWrBursts::0 4125 # Per bank write bursts
system.physmem.perBankWrBursts::1 4164 # Per bank write bursts
system.physmem.perBankWrBursts::2 4223 # Per bank write bursts
system.physmem.perBankWrBursts::6 4262 # Per bank write bursts
system.physmem.perBankWrBursts::7 4226 # Per bank write bursts
system.physmem.perBankWrBursts::8 4233 # Per bank write bursts
-system.physmem.perBankWrBursts::9 4179 # Per bank write bursts
-system.physmem.perBankWrBursts::10 4147 # Per bank write bursts
+system.physmem.perBankWrBursts::9 4185 # Per bank write bursts
+system.physmem.perBankWrBursts::10 4150 # Per bank write bursts
system.physmem.perBankWrBursts::11 4241 # Per bank write bursts
system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
system.physmem.perBankWrBursts::13 4100 # Per bank write bursts
system.physmem.perBankWrBursts::15 4157 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 278170791500 # Total gap between requests
+system.physmem.totGap 278139341500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 291443 # Read request sizes (log2)
+system.physmem.readPktSize::6 291455 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 66683 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 214189 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 46674 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 30117 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 160 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 24 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 211494 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 46714 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 32763 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 157 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 970 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 972 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 2092 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 4176 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 4047 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 4046 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 4384 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 4068 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 4053 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 4075 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 4069 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 4380 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 4593 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 968 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 969 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 2055 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 4173 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 4049 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 4048 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 4397 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 4078 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 4070 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 4080 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 4072 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 4371 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 4578 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 4103 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 4061 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 4256 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 4275 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 4044 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 4265 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 4282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 4047 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 100147 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 228.644373 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 146.919705 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 277.922323 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 35701 35.65% 35.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 41944 41.88% 77.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 10332 10.32% 87.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 643 0.64% 88.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 550 0.55% 89.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 478 0.48% 89.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 606 0.61% 90.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1154 1.15% 91.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 8739 8.73% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 100147 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 4044 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 68.435955 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean 36.134261 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 746.811219 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 4037 99.83% 99.83% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-6143 1 0.02% 99.85% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-14335 2 0.05% 99.90% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-16383 3 0.07% 99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 100451 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 227.952415 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 146.081554 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 279.010577 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 36030 35.87% 35.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 42282 42.09% 77.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 10217 10.17% 88.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 414 0.41% 88.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 384 0.38% 88.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 317 0.32% 89.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 757 0.75% 90.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1270 1.26% 91.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 8780 8.74% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 100451 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 4045 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 70.301854 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean 36.144651 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 769.722850 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 4038 99.83% 99.83% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-12287 1 0.02% 99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.88% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 4044 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 4044 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.481701 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.460271 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.857904 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 3073 75.99% 75.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 965 23.86% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 6 0.15% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 4044 # Writes before turning the bus around for reads
-system.physmem.totQLat 3337058000 # Total ticks spent queuing
-system.physmem.totMemAccLat 8796439250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1455835000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11460.98 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 4045 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 4045 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.479852 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.458498 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 0.856350 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 3077 76.07% 76.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 963 23.81% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 5 0.12% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 4045 # Writes before turning the bus around for reads
+system.physmem.totQLat 3340616250 # Total ticks spent queuing
+system.physmem.totMemAccLat 8799847500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1455795000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 11473.51 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30210.98 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 66.99 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 15.33 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 67.05 # Average system read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 30223.51 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 67.00 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 15.34 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 67.06 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 15.34 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.64 # Data bus utilization in percentage
system.physmem.busUtilRead 0.52 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.12 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing
-system.physmem.readRowHits 207319 # Number of row buffer hits during reads
-system.physmem.writeRowHits 50340 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 71.20 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 75.49 # Row buffer hit rate for writes
-system.physmem.avgGap 776740.01 # Average gap between requests
-system.physmem.pageHitRate 72.00 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 73797472500 # Time in different power states
-system.physmem.memoryStateTime::REF 9288500000 # Time in different power states
+system.physmem.avgWrQLen 24.39 # Average write queue length when enqueuing
+system.physmem.readRowHits 206977 # Number of row buffer hits during reads
+system.physmem.writeRowHits 50379 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 71.09 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 75.55 # Row buffer hit rate for writes
+system.physmem.avgGap 776626.17 # Average gap between requests
+system.physmem.pageHitRate 71.92 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 74109656250 # Time in different power states
+system.physmem.memoryStateTime::REF 9287460000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 195078106500 # Time in different power states
+system.physmem.memoryStateTime::ACT 194735825750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 82395628 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 224814 # Transaction distribution
-system.membus.trans_dist::ReadResp 224814 # Transaction distribution
+system.membus.trans_dist::ReadReq 224829 # Transaction distribution
+system.membus.trans_dist::ReadResp 224829 # Transaction distribution
system.membus.trans_dist::Writeback 66683 # Transaction distribution
-system.membus.trans_dist::ReadExReq 66629 # Transaction distribution
-system.membus.trans_dist::ReadExResp 66629 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649569 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 649569 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22920064 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 22920064 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 22920064 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 964230000 # Layer occupancy (ticks)
+system.membus.trans_dist::ReadExReq 66626 # Transaction distribution
+system.membus.trans_dist::ReadExResp 66626 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649593 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 649593 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22920832 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 22920832 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 358138 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 358138 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 358138 # Request fanout histogram
+system.membus.reqLayer0.occupancy 956225500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2710224500 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2708510750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 192451615 # Number of BP lookups
-system.cpu.branchPred.condPredicted 125635967 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 11884604 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 155866017 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 126935891 # Number of BTB hits
+system.cpu.branchPred.lookups 192497192 # Number of BP lookups
+system.cpu.branchPred.condPredicted 125506208 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 11891081 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 155386216 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 126898467 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 81.439106 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 28844958 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 146 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 81.666489 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 29014222 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 151 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 244501349 # DTB read hits
-system.cpu.dtb.read_misses 309633 # DTB read misses
+system.cpu.dtb.read_hits 244546246 # DTB read hits
+system.cpu.dtb.read_misses 309763 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 244810982 # DTB read accesses
-system.cpu.dtb.write_hits 135678395 # DTB write hits
-system.cpu.dtb.write_misses 31433 # DTB write misses
+system.cpu.dtb.read_accesses 244856009 # DTB read accesses
+system.cpu.dtb.write_hits 135693142 # DTB write hits
+system.cpu.dtb.write_misses 31331 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 135709828 # DTB write accesses
-system.cpu.dtb.data_hits 380179744 # DTB hits
-system.cpu.dtb.data_misses 341066 # DTB misses
+system.cpu.dtb.write_accesses 135724473 # DTB write accesses
+system.cpu.dtb.data_hits 380239388 # DTB hits
+system.cpu.dtb.data_misses 341094 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 380520810 # DTB accesses
-system.cpu.itb.fetch_hits 196843274 # ITB hits
-system.cpu.itb.fetch_misses 340 # ITB misses
+system.cpu.dtb.data_accesses 380580482 # DTB accesses
+system.cpu.itb.fetch_hits 197059053 # ITB hits
+system.cpu.itb.fetch_misses 278 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 196843614 # ITB accesses
+system.cpu.itb.fetch_accesses 197059331 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 37 # Number of system calls
-system.cpu.numCycles 556341750 # number of cpu cycles simulated
+system.cpu.numCycles 556278850 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 202596472 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1648022555 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 192451615 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 155780849 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 341400338 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 24237220 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 65 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 6944 # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles 202390061 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1648021471 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 192497192 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 155912689 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 341534414 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 24250324 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 71 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 163 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 6722 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 196843274 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 6474022 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 556122593 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.963416 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.176362 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 197059053 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 6903560 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 556056617 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.963766 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.176070 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 237070993 42.63% 42.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 30141188 5.42% 48.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 22117288 3.98% 52.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 36437929 6.55% 58.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 67906358 12.21% 70.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 21586506 3.88% 74.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 19299171 3.47% 78.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 3525264 0.63% 78.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 118037896 21.23% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 236849124 42.59% 42.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 30318987 5.45% 48.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 22124224 3.98% 52.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 36449383 6.55% 58.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 67846603 12.20% 70.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 21659642 3.90% 74.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 19297725 3.47% 78.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 3452517 0.62% 78.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 118058412 21.23% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 556122593 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.345923 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.962249 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 168349447 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 89068138 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 273848076 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 12745104 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 12111828 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 15365676 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 7037 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 1585434415 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 25396 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 12111828 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 176490492 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 62059786 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 14189 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 278431125 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 27015173 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 1538086365 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 7791 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 2366498 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 17905765 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 6836076 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 1026692475 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1767991158 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1728209753 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 39781404 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 556056617 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.346044 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.962582 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 168903349 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 88724490 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 273566111 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 12744273 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 12118394 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 15366279 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 7028 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 1583865955 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 25244 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 12118394 # Number of cycles rename is squashing
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+system.cpu.rename.LQFullEvents 17873362 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 6849052 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 1027019192 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1768562187 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1728780266 # Number of integer rename lookups
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system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 387725317 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1423 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 146 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 9582425 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 372570647 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 175396988 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 40822996 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 11172222 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1305164678 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 123 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1015585029 # Number of instructions issued
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-system.cpu.iq.iqSquashedOperandsExamined 428157425 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 86 # Number of squashed non-spec instructions that were removed
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+system.cpu.iq.iqInstsIssued 1015678873 # Number of instructions issued
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+system.cpu.iq.iqSquashedOperandsExamined 427374200 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 10.47% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 10.47% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 15571985 66.15% 76.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 5503822 23.38% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.05% # Type of FU issued
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-system.cpu.iq.FU_type_0::FloatCmp 3826543 0.38% 58.73% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 3339802 0.33% 59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.06% # Type of FU issued
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-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.06% # Type of FU issued
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-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.06% # Type of FU issued
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+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.05% # Type of FU issued
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+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.05% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 276926005 27.27% 86.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 138947884 13.68% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1015585029 # Type of FU issued
-system.cpu.iq.rate 1.825470 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 23540305 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.023179 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 2548815722 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 1726656461 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 939949010 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 70808195 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 41310105 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 34425215 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1002762123 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 36361935 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 50443717 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1015678873 # Type of FU issued
+system.cpu.iq.rate 1.825845 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 23531079 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.023168 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 2548927232 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 1725239923 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 940039301 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 70808456 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 41311588 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 34425282 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1002846638 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 36362038 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 50462240 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 135060050 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 1143240 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 45700 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 77095788 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 134754491 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 1146539 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 45582 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 77131633 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2279 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 4366 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2126 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 4422 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 12111828 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 61105954 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 191244 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1479623370 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 16690 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 372570647 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 175396988 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 121 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 26783 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 176241 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 45700 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 11878414 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 16350 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 11894764 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 976099064 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 244811165 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 39485965 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 12118394 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 60795579 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 183960 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 1478937167 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 16099 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 372265088 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 175432833 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 26971 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 168750 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 45582 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 11885427 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 16182 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 11901609 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 976191371 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 244856188 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 39487502 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 174458569 # number of nop insts executed
-system.cpu.iew.exec_refs 380521398 # number of memory reference insts executed
-system.cpu.iew.exec_branches 129090215 # Number of branches executed
-system.cpu.iew.exec_stores 135710233 # Number of stores executed
-system.cpu.iew.exec_rate 1.754495 # Inst execution rate
-system.cpu.iew.wb_sent 974894086 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 974374225 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 556362190 # num instructions producing a value
-system.cpu.iew.wb_consumers 832682807 # num instructions consuming a value
+system.cpu.iew.exec_nop 174481002 # number of nop insts executed
+system.cpu.iew.exec_refs 380581036 # number of memory reference insts executed
+system.cpu.iew.exec_branches 129104728 # Number of branches executed
+system.cpu.iew.exec_stores 135724848 # Number of stores executed
+system.cpu.iew.exec_rate 1.754860 # Inst execution rate
+system.cpu.iew.wb_sent 974983742 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 974464583 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 556223277 # num instructions producing a value
+system.cpu.iew.wb_consumers 832224680 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.751395 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.668156 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.751756 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.668357 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 543793882 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 543106202 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 11877823 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 483108609 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.922109 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.601347 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 11884314 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 483349873 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.921150 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.600543 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 205236337 42.48% 42.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 102049514 21.12% 63.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 51661331 10.69% 74.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 25803847 5.34% 79.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 21528421 4.46% 84.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 9152086 1.89% 85.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 10413942 2.16% 88.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 6658903 1.38% 89.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 50604228 10.47% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 205286712 42.47% 42.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 102225167 21.15% 63.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 51816081 10.72% 74.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 25666887 5.31% 79.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 21541208 4.46% 84.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 9141976 1.89% 86.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 10432211 2.16% 88.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 6655388 1.38% 89.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 50584243 10.47% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 483108609 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 483349873 # Number of insts commited each cycle
system.cpu.commit.committedInsts 928587628 # Number of instructions committed
system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction
-system.cpu.commit.bw_lim_events 50604228 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 50584243 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1902264753 # The number of ROB reads
-system.cpu.rob.rob_writes 3017778261 # The number of ROB writes
-system.cpu.timesIdled 3284 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 219157 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 1901838322 # The number of ROB reads
+system.cpu.rob.rob_writes 3016095658 # The number of ROB writes
+system.cpu.timesIdled 3295 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 222233 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 842382029 # Number of Instructions Simulated
system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.660439 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.660439 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.514145 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.514145 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1237156032 # number of integer regfile reads
-system.cpu.int_regfile_writes 705771856 # number of integer regfile writes
-system.cpu.fp_regfile_reads 36691388 # number of floating regfile reads
-system.cpu.fp_regfile_writes 24411317 # number of floating regfile writes
+system.cpu.cpi 0.660364 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.660364 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.514316 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.514316 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1237260763 # number of integer regfile reads
+system.cpu.int_regfile_writes 705832198 # number of integer regfile writes
+system.cpu.fp_regfile_reads 36691509 # number of floating regfile reads
+system.cpu.fp_regfile_writes 24411335 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 202299828 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 718925 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 718924 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 91520 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 68836 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 68836 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12807 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1654234 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 1667041 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 409792 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55864128 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 56273920 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 56273920 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 531160500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::ReadReq 718899 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 718898 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 91488 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 68835 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 68835 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12761 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1654194 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 1666955 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 408320 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55861824 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 56270144 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 879222 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 879222 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 879222 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 531099000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 10099250 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 10065500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1208088500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 1207435500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
-system.cpu.icache.tags.replacements 4693 # number of replacements
-system.cpu.icache.tags.tagsinuse 1650.457565 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 196834917 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 6403 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 30741.045916 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 4667 # number of replacements
+system.cpu.icache.tags.tagsinuse 1655.176031 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 197050731 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 6380 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 30885.694514 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1650.457565 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.805887 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.805887 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 1710 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst 1655.176031 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.808191 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.808191 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 1713 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 1543 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.834961 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 393692951 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 393692951 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 196834917 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 196834917 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 196834917 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 196834917 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 196834917 # number of overall hits
-system.cpu.icache.overall_hits::total 196834917 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 8357 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 8357 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 8357 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 8357 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 8357 # number of overall misses
-system.cpu.icache.overall_misses::total 8357 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 329567249 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 329567249 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 329567249 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 329567249 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 329567249 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 329567249 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 196843274 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 196843274 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 196843274 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 196843274 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 196843274 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 196843274 # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 1559 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.836426 # Percentage of cache occupancy per task id
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-system.cpu.dcache.blocked_cycles::no_mshrs 22462 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 55443 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 471 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 516 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.690021 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 107.447674 # average number of cycles each access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 21 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 21 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 292379026 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 292379026 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 292379026 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 292379026 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008126 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.008126 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009337 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.009337 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.008533 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.008533 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.008533 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.008533 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50715.186280 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 50715.186280 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62423.291957 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 62423.291957 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55022.298115 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 55022.298115 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55022.298115 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 55022.298115 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 21941 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 56666 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 465 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 517 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.184946 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 109.605416 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 91520 # number of writebacks
-system.cpu.dcache.writebacks::total 91520 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 866542 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 866542 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 851427 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 851427 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1717969 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1717969 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1717969 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1717969 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712521 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 712521 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68836 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 68836 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 781357 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 781357 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 781357 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 781357 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21863154000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 21863154000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5224164248 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 5224164248 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27087318248 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 27087318248 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27087318248 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 27087318248 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003672 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003672 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks 91488 # number of writebacks
+system.cpu.dcache.writebacks::total 91488 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864626 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 864626 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 849006 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 849006 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1713632 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1713632 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1713632 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1713632 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712518 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 712518 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68835 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 68835 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 781353 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 781353 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 781353 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 781353 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21854414000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 21854414000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5217448748 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5217448748 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27071862748 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 27071862748 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27071862748 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 27071862748 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003671 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003671 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000700 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000700 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002673 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.002673 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002673 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.002673 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30684.224044 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30684.224044 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75892.908478 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75892.908478 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34667.019362 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 34667.019362 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34667.019362 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 34667.019362 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.002672 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.002672 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30672.086881 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30672.086881 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75796.451631 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75796.451631 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34647.416402 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 34647.416402 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34647.416402 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 34647.416402 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 464394627000 # Number of ticks simulated
final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1843860 # Simulator instruction rate (inst/s)
-host_op_rate 1843860 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 922130037 # Simulator tick rate (ticks/s)
-host_mem_usage 234352 # Number of bytes of host memory used
-host_seconds 503.61 # Real time elapsed on the host
+host_inst_rate 2843750 # Simulator instruction rate (inst/s)
+host_op_rate 2843750 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1422183537 # Simulator tick rate (ticks/s)
+host_mem_usage 289848 # Number of bytes of host memory used
+host_seconds 326.54 # Real time elapsed on the host
sim_insts 928587629 # Number of instructions simulated
sim_ops 928587629 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7999999104 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5156832357 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13156831461 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 13156831461 # Throughput (bytes/s)
-system.membus.data_through_bus 6109961839 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 1166299747 # Transaction distribution
+system.membus.trans_dist::ReadResp 1166299747 # Transaction distribution
+system.membus.trans_dist::WriteReq 98301200 # Transaction distribution
+system.membus.trans_dist::WriteResp 98301200 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1857578300 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 671623594 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 2529201894 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 3715156600 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2394805239 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 6109961839 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 1264600947 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.734452 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.441624 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 335811797 26.55% 26.55% # Request fanout histogram
+system.membus.snoop_fanout::1 928789150 73.45% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 1264600947 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
sim_ticks 1286249820000 # Number of ticks simulated
final_tick 1286249820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 839019 # Simulator instruction rate (inst/s)
-host_op_rate 839019 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1162182391 # Simulator tick rate (ticks/s)
-host_mem_usage 244120 # Number of bytes of host memory used
-host_seconds 1106.75 # Real time elapsed on the host
+host_inst_rate 1681245 # Simulator instruction rate (inst/s)
+host_op_rate 1681245 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2328806930 # Simulator tick rate (ticks/s)
+host_mem_usage 298588 # Number of bytes of host memory used
+host_seconds 552.32 # Real time elapsed on the host
sim_insts 928587629 # Number of instructions simulated
sim_ops 928587629 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 107127 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 14356203 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 17781280 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 17781280 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 224031 # Transaction distribution
system.membus.trans_dist::ReadResp 224031 # Transaction distribution
system.membus.trans_dist::Writeback 66683 # Transaction distribution
system.membus.trans_dist::ReadExResp 66648 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 648041 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 648041 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 22871168 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 357362 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 357362 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 357362 # Request fanout histogram
system.membus.reqLayer0.occupancy 890826000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 2616111000 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 43704406 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 717682 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 91660 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12336 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652716 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1665052 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 394752 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55820032 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 56214784 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 56214784 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 394752 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55820032 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 56214784 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 878356 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 878356 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 878356 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 530838000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks)
sim_ticks 537826498500 # Number of ticks simulated
final_tick 537826498500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 114564 # Simulator instruction rate (inst/s)
-host_op_rate 141043 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 96175687 # Simulator tick rate (ticks/s)
-host_mem_usage 263048 # Number of bytes of host memory used
-host_seconds 5592.13 # Real time elapsed on the host
+host_inst_rate 160425 # Simulator instruction rate (inst/s)
+host_op_rate 197504 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 134676016 # Simulator tick rate (ticks/s)
+host_mem_usage 315984 # Number of bytes of host memory used
+host_seconds 3993.48 # Real time elapsed on the host
sim_insts 640655084 # Number of instructions simulated
sim_ops 788730743 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.writeReqs 66098 # Number of write requests accepted
system.physmem.readBursts 290531 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 18574336 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue
-system.physmem.bytesWritten 4229312 # Total number of bytes written to DRAM
+system.physmem.bytesReadDRAM 18574784 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 19200 # Total number of bytes read from write queue
+system.physmem.bytesWritten 4228736 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 18593984 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ 300 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 18283 # Per bank write bursts
-system.physmem.perBankRdBursts::1 18133 # Per bank write bursts
+system.physmem.perBankRdBursts::0 18291 # Per bank write bursts
+system.physmem.perBankRdBursts::1 18140 # Per bank write bursts
system.physmem.perBankRdBursts::2 18223 # Per bank write bursts
-system.physmem.perBankRdBursts::3 18187 # Per bank write bursts
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-system.physmem.perBankRdBursts::5 18313 # Per bank write bursts
-system.physmem.perBankRdBursts::6 18090 # Per bank write bursts
-system.physmem.perBankRdBursts::7 17910 # Per bank write bursts
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-system.physmem.perBankRdBursts::10 18023 # Per bank write bursts
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-system.physmem.perBankRdBursts::12 18159 # Per bank write bursts
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+system.physmem.perBankRdBursts::14 18079 # Per bank write bursts
+system.physmem.perBankRdBursts::15 18262 # Per bank write bursts
system.physmem.perBankWrBursts::0 4174 # Per bank write bursts
system.physmem.perBankWrBursts::1 4102 # Per bank write bursts
system.physmem.perBankWrBursts::2 4137 # Per bank write bursts
system.physmem.perBankWrBursts::4 4225 # Per bank write bursts
system.physmem.perBankWrBursts::5 4225 # Per bank write bursts
system.physmem.perBankWrBursts::6 4171 # Per bank write bursts
-system.physmem.perBankWrBursts::7 4094 # Per bank write bursts
-system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::9 4093 # Per bank write bursts
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-system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
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system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
-system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
system.physmem.perBankWrBursts::15 4138 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 66098 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 289825 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 382 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 111452 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 204.586154 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 132.570788 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 256.465119 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 47032 42.20% 42.20% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::256-383 8758 7.86% 89.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 741 0.66% 89.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 1179 1.06% 90.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1268 1.14% 91.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 550 0.49% 92.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 543 0.49% 92.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 7880 7.07% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 111452 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 4008 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 48.655439 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean 36.051521 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 507.704420 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 4005 99.93% 99.93% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 111650 # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::stdev 255.940958 # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::384-511 837 0.75% 89.75% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1024-1151 7870 7.05% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 111650 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 4008 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 4008 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.487774 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.466259 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.859394 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 3030 75.60% 75.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 3 0.07% 75.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 973 24.28% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 4008 # Writes before turning the bus around for reads
-system.physmem.totQLat 3341298000 # Total ticks spent queuing
-system.physmem.totMemAccLat 8782998000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1451120000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11512.82 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes
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+system.physmem.wrPerTurnAround::mean 16.489643 # Writes before turning the bus around for reads
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+system.physmem.totQLat 3341982750 # Total ticks spent queuing
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30262.82 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 30264.91 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 34.54 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 7.86 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 34.57 # Average system read bandwidth in MiByte/s
system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 29.26 # Average write queue length when enqueuing
-system.physmem.readRowHits 194846 # Number of row buffer hits during reads
-system.physmem.writeRowHits 49995 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 67.14 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 75.64 # Row buffer hit rate for writes
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+system.physmem.readRowHitRate 67.05 # Row buffer hit rate for reads
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system.physmem.avgGap 1508083.78 # Average gap between requests
-system.physmem.pageHitRate 68.71 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 253517983250 # Time in different power states
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system.physmem.memoryStateTime::REF 17958980000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 42437954 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 224439 # Transaction distribution
system.membus.trans_dist::ReadResp 224439 # Transaction distribution
system.membus.trans_dist::Writeback 66098 # Transaction distribution
system.membus.trans_dist::ReadExResp 66092 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647160 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 647160 # Packet count per connected master and slave (bytes)
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-system.membus.tot_pkt_size::total 22824256 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 22824256 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 974430000 # Layer occupancy (ticks)
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+system.membus.snoops 0 # Total snoops (count)
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+system.membus.snoop_fanout::mean 0 # Request fanout histogram
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+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
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+system.membus.reqLayer0.occupancy 974401000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2738631750 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2738560500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 154837020 # Number of BP lookups
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.678989 # CPI: cycles per instruction
system.cpu.ipc 0.595596 # IPC: instructions per cycle
-system.cpu.tickCycles 1020176275 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 55476722 # Total number of cycles that the object has spent stopped
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system.cpu.icache.tags.replacements 23597 # number of replacements
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system.cpu.icache.tags.total_refs 289999264 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 11441.167160 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_task_id_blocks::1024 1750 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id
system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::total 25348 # number of overall misses
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-system.cpu.icache.demand_miss_latency::total 480804246 # number of demand (read+write) miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 290024612 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 290024612 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 290024612 # number of demand (read+write) accesses
system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18968.133423 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 18968.133423 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18968.133423 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18963.695203 # average ReadReq miss latency
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+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18963.695203 # average overall miss latency
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18963.695203 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18963.695203 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 25348 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429006754 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 429006754 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429006754 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 429006754 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429006754 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 429006754 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 428895254 # number of ReadReq MSHR miss cycles
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+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 428895254 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 428895254 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 428895254 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 428895254 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.105558 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31116.105558 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65256.152359 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65256.152359 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 34140.939361 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 34140.939361 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 34140.939361 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 34140.939361 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.297198 # Number of seconds simulated
-sim_ticks 297198275500 # Number of ticks simulated
-final_tick 297198275500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.407884 # Number of seconds simulated
+sim_ticks 407883784500 # Number of ticks simulated
+final_tick 407883784500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 98901 # Simulator instruction rate (inst/s)
-host_op_rate 121761 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 45880544 # Simulator tick rate (ticks/s)
-host_mem_usage 261988 # Number of bytes of host memory used
-host_seconds 6477.65 # Real time elapsed on the host
+host_inst_rate 87874 # Simulator instruction rate (inst/s)
+host_op_rate 108185 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 55946898 # Simulator tick rate (ticks/s)
+host_mem_usage 2562780 # Number of bytes of host memory used
+host_seconds 7290.55 # Real time elapsed on the host
sim_insts 640649298 # Number of instructions simulated
sim_ops 788724957 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 150208 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 18436864 # Number of bytes read from this memory
-system.physmem.bytes_read::total 18587072 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 150208 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 150208 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
-system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2347 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 288076 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 290423 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 505413 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 62035569 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 62540982 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 505413 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 505413 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 14233838 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 14233838 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 14233838 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 505413 # Total bandwidth to/from this memory (bytes/s)
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-system.physmem.bw_total::total 76774820 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 290424 # Number of read requests accepted
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-system.physmem.bytesReadWrQ 21760 # Total number of bytes read from write queue
-system.physmem.bytesWritten 4228224 # Total number of bytes written to DRAM
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-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 2334 # Number of requests that are neither read nor write
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 297198223500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
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-system.physmem.bytesPerActivate::mean 214.227653 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 137.234885 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 270.519636 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 42398 39.85% 39.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 42939 40.36% 80.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 9834 9.24% 89.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 319 0.30% 89.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 247 0.23% 89.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 237 0.22% 90.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 324 0.30% 90.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1664 1.56% 92.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 8428 7.92% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 106390 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 4009 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 48.488651 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean 36.041584 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 505.320352 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 4006 99.93% 99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 4009 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 4009 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.479421 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.458127 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.855088 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 3049 76.05% 76.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 1 0.02% 76.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 956 23.85% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 4009 # Writes before turning the bus around for reads
-system.physmem.totQLat 3531270750 # Total ticks spent queuing
-system.physmem.totMemAccLat 8970345750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1450420000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 12173.27 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 138324 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 178.138053 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 128.082938 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 199.804046 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 55124 39.85% 39.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 58239 42.10% 81.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 14671 10.61% 92.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 966 0.70% 93.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 1420 1.03% 94.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1368 0.99% 95.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1462 1.06% 96.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1224 0.88% 97.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 3850 2.78% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 138324 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 67.829475 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean 35.454654 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 482.917109 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511 3981 99.10% 99.10% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023 15 0.37% 99.48% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1535 5 0.12% 99.60% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-2047 4 0.10% 99.70% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-2559 3 0.07% 99.78% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2560-3071 2 0.05% 99.83% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-3583 1 0.02% 99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4608-5119 1 0.02% 99.88% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::5632-6143 1 0.02% 99.90% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-12799 1 0.02% 99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::13824-14335 2 0.05% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::15872-16383 1 0.02% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 4017 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 4017 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.484690 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.435555 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.421529 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 3367 83.82% 83.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 9 0.22% 84.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 437 10.88% 94.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 79 1.97% 96.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 37 0.92% 97.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 18 0.45% 98.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 15 0.37% 98.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 22 0.55% 99.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 13 0.32% 99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 3 0.07% 99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 6 0.15% 99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27 2 0.05% 99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28 3 0.07% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29 2 0.05% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30 1 0.02% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34 2 0.05% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads
+system.physmem.totQLat 9958454882 # Total ticks spent queuing
+system.physmem.totMemAccLat 15935954882 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1594000000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 31237.31 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30923.27 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 62.47 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 14.23 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 62.54 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 14.23 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 49987.31 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 50.02 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 10.39 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 50.07 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 10.40 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.60 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.49 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.11 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 28.82 # Average write queue length when enqueuing
-system.physmem.readRowHits 199840 # Number of row buffer hits during reads
-system.physmem.writeRowHits 49907 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 68.89 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 75.50 # Row buffer hit rate for writes
-system.physmem.avgGap 833604.16 # Average gap between requests
-system.physmem.pageHitRate 70.12 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 84430805250 # Time in different power states
-system.physmem.memoryStateTime::REF 9923940000 # Time in different power states
+system.physmem.busUtil 0.47 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.39 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.59 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.53 # Average write queue length when enqueuing
+system.physmem.readRowHits 219908 # Number of row buffer hits during reads
+system.physmem.writeRowHits 26785 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 68.98 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 40.43 # Row buffer hit rate for writes
+system.physmem.avgGap 1058335.94 # Average gap between requests
+system.physmem.pageHitRate 64.07 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 155274651966 # Time in different power states
+system.physmem.memoryStateTime::REF 13620100000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 202838904750 # Time in different power states
+system.physmem.memoryStateTime::ACT 238988228034 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 76774820 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 224345 # Transaction distribution
-system.membus.trans_dist::ReadResp 224344 # Transaction distribution
-system.membus.trans_dist::Writeback 66098 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 2334 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 2334 # Transaction distribution
-system.membus.trans_dist::ReadExReq 66079 # Transaction distribution
-system.membus.trans_dist::ReadExResp 66079 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 651613 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 651613 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22817344 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 22817344 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 22817344 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1003041500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2737822416 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
+system.membus.trans_dist::ReadReq 317731 # Transaction distribution
+system.membus.trans_dist::ReadResp 317731 # Transaction distribution
+system.membus.trans_dist::Writeback 66312 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 19 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 19 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1358 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1358 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 704528 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 704528 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24665664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 24665664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 385420 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 385420 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 385420 # Request fanout histogram
+system.membus.reqLayer0.occupancy 968060850 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
+system.membus.respLayer1.occupancy 2930140600 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 271863224 # Number of BP lookups
-system.cpu.branchPred.condPredicted 178425431 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 15415799 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 186524109 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 146250524 # Number of BTB hits
+system.cpu.branchPred.lookups 233961455 # Number of BP lookups
+system.cpu.branchPred.condPredicted 161822903 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 15515021 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 121571694 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 108258179 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 78.408376 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 34625446 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1929978 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 89.048836 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 25034450 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1300530 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 673 # Number of system calls
-system.cpu.numCycles 594396552 # number of cpu cycles simulated
+system.cpu.numCycles 815767570 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 217387549 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1367579713 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 271863224 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 180875970 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 338099313 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 30904558 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 628206 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 6076291 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 107 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 207850438 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 5507154 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 577643745 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.955013 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.177882 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 84062545 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1200075863 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 233961455 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 133292629 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 716015819 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 31064710 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 216 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 1031 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 370072724 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 652087 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 815611997 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.839157 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.161407 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 246926096 42.75% 42.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 22334065 3.87% 46.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 58641984 10.15% 56.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 13805206 2.39% 59.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 49967679 8.65% 67.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 26102781 4.52% 72.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 32011884 5.54% 77.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 19377139 3.35% 81.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 108476911 18.78% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 134572174 16.50% 16.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 222502254 27.28% 43.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 98076609 12.02% 55.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 360460960 44.20% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 577643745 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.457377 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.300787 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 170543616 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 112383913 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 256390493 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 22882666 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 15443057 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 30474424 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 9349 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 1602087744 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 25664 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 15443057 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 180102309 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 80879107 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 304937 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 269061579 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 31852756 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 1553633601 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 27722 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 3084329 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 23262068 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 5400130 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 1588085164 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 7592228001 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1750427089 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 56767331 # Number of floating rename lookups
+system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 815611997 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.286799 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.471100 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 119967047 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 156830594 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 484662032 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 38633655 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 15518669 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 25180757 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 13832 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 1248142745 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 39968083 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 15518669 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 176978211 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 77349013 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 209115 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 464956606 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 80600383 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 1190653187 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 25546667 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 24946830 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 2267986 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 40254462 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 1692453 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 1225396135 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5812466885 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1358185264 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 40876472 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 713306934 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 13108 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 10964 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 53001201 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 494421032 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 283375622 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 38186333 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 81232307 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1474584555 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 16256 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1149612413 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 2320605 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 685767226 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1987453954 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 4102 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 577643745 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.990175 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.969584 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 350617905 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 7272 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 7264 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 108149104 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 366119032 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 236098756 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1753479 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 5371728 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 1168565166 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 12360 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1017100859 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 18396242 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 379746204 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1032205063 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 206 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 815611997 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.247040 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.084974 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 197611085 34.21% 34.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 85639840 14.83% 49.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 74707514 12.93% 61.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 82105787 14.21% 76.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 66954970 11.59% 87.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 40972938 7.09% 94.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 18446421 3.19% 98.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 4764432 0.82% 98.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 6440758 1.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 257903097 31.62% 31.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 228438073 28.01% 59.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 215325690 26.40% 86.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 97769150 11.99% 98.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 16175979 1.98% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 577643745 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 815611997 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 853039 1.90% 1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 10574 0.02% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 27015778 60.17% 62.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 17022674 37.91% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 64512923 19.13% 19.13% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 155504488 46.10% 65.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 116641749 34.58% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 506618209 44.07% 44.07% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 5850863 0.51% 44.58% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 44.58% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 44.58% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 44.58% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 44.58% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 44.58% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 44.58% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 44.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 44.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 44.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 44.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 44.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 44.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 44.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 44.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 44.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 44.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 44.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 44.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 1274977 0.11% 44.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 3188014 0.28% 44.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 2550893 0.22% 45.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 45.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 11539273 1.00% 46.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 46.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 46.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.19% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 402298542 34.99% 81.19% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 216291642 18.81% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 456383765 44.87% 44.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 5195693 0.51% 45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.06% 45.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 2550151 0.25% 46.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 11478998 1.13% 47.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 322094029 31.67% 78.81% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 215573019 21.19% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1149612413 # Type of FU issued
-system.cpu.iq.rate 1.934083 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 44902065 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.039058 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 2861318586 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2106127825 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1031796042 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 62772655 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 54292666 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 30270248 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1162493023 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 32021455 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 23570591 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1017100859 # Type of FU issued
+system.cpu.iq.rate 1.246802 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 337314196 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.331643 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 3143647062 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 1504776491 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 934274751 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 61877091 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 43565761 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 26152451 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1320604680 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 33810375 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 9960281 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 242180094 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 1210 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 685580 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 154395126 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 113878094 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 1252 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 18526 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 107118260 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 29018041 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 192 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2065804 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 23979 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 15443057 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 78194989 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1280631 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1475233939 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 214769 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 494421032 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 283375622 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 10516 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 630754 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 23941 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 685580 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 16670086 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 506202 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 17176288 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1116354859 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 386341523 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 33257554 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 15518669 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 35328826 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 675397 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 1168583078 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 366119032 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 236098756 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 6620 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 121 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 678981 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 18526 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 15437712 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 3784771 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 19222483 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 974757504 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 303300667 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 42343355 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 633128 # number of nop insts executed
-system.cpu.iew.exec_refs 593821006 # number of memory reference insts executed
-system.cpu.iew.exec_branches 162537737 # Number of branches executed
-system.cpu.iew.exec_stores 207479483 # Number of stores executed
-system.cpu.iew.exec_rate 1.878131 # Inst execution rate
-system.cpu.iew.wb_sent 1074811517 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1062066290 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 606518919 # num instructions producing a value
-system.cpu.iew.wb_consumers 1092664472 # num instructions consuming a value
+system.cpu.iew.exec_nop 5552 # number of nop insts executed
+system.cpu.iew.exec_refs 497757295 # number of memory reference insts executed
+system.cpu.iew.exec_branches 150614518 # Number of branches executed
+system.cpu.iew.exec_stores 194456628 # Number of stores executed
+system.cpu.iew.exec_rate 1.194896 # Inst execution rate
+system.cpu.iew.wb_sent 963726633 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 960427202 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 536683301 # num instructions producing a value
+system.cpu.iew.wb_consumers 893293358 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.786798 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.555082 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.177329 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.600792 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 686508704 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 357423726 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 15406577 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 485351634 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.625069 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.327523 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 15501335 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 764789514 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.031303 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.790973 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 210489753 43.37% 43.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 125850152 25.93% 69.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 47800480 9.85% 79.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 20690881 4.26% 83.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 22810841 4.70% 88.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 8150144 1.68% 89.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 8105919 1.67% 91.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 7050996 1.45% 92.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 34402468 7.09% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 428726988 56.06% 56.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 171833427 22.47% 78.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 73566428 9.62% 88.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 31619643 4.13% 92.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 7902471 1.03% 93.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 14889027 1.95% 95.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 7271717 0.95% 96.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 6618968 0.87% 97.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 22360845 2.92% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 485351634 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 764789514 # Number of insts commited each cycle
system.cpu.commit.committedInsts 640654410 # Number of instructions committed
system.cpu.commit.committedOps 788730069 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 788730069 # Class of committed instruction
-system.cpu.commit.bw_lim_events 34402468 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 22360845 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1926179188 # The number of ROB reads
-system.cpu.rob.rob_writes 3042778169 # The number of ROB writes
-system.cpu.timesIdled 159779 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 16752807 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 1888573713 # The number of ROB reads
+system.cpu.rob.rob_writes 2343133825 # The number of ROB writes
+system.cpu.timesIdled 646395 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 155573 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 640649298 # Number of Instructions Simulated
system.cpu.committedOps 788724957 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.927803 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.927803 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.077815 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.077815 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1132703521 # number of integer regfile reads
-system.cpu.int_regfile_writes 646986163 # number of integer regfile writes
-system.cpu.fp_regfile_reads 37276202 # number of floating regfile reads
-system.cpu.fp_regfile_writes 27223952 # number of floating regfile writes
-system.cpu.cc_regfile_reads 4371075707 # number of cc regfile reads
-system.cpu.cc_regfile_writes 413227106 # number of cc regfile writes
-system.cpu.misc_regfile_reads 814254354 # number of misc regfile reads
+system.cpu.cpi 1.273345 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.273345 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.785333 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.785333 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 995802638 # number of integer regfile reads
+system.cpu.int_regfile_writes 567917186 # number of integer regfile writes
+system.cpu.fp_regfile_reads 31889847 # number of floating regfile reads
+system.cpu.fp_regfile_writes 22959506 # number of floating regfile writes
+system.cpu.cc_regfile_reads 3794452598 # number of cc regfile reads
+system.cpu.cc_regfile_writes 384905504 # number of cc regfile writes
+system.cpu.misc_regfile_reads 715806131 # number of misc regfile reads
system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 191669699 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 729385 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 729383 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 91367 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2337 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2337 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 69311 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 69311 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 26757 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1664338 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 1691095 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 781440 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 56032960 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 56814400 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 56814400 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 149504 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 537567000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 22218748 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1220548813 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
-system.cpu.icache.tags.replacements 10545 # number of replacements
-system.cpu.icache.tags.tagsinuse 1626.781544 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 207828971 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 12209 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 17022.603899 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1626.781544 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.794327 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.794327 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 1664 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 1549 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 415715422 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 415715422 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 207833630 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 207833630 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 207833630 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 207833630 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 207833630 # number of overall hits
-system.cpu.icache.overall_hits::total 207833630 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 16808 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 16808 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 16808 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 16808 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 16808 # number of overall misses
-system.cpu.icache.overall_misses::total 16808 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 373718245 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 373718245 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 373718245 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 373718245 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 373718245 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 373718245 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 207850438 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 207850438 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total 207850438 # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total 207850438 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000081 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000081 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000081 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000081 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000081 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000081 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22234.545752 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 22234.545752 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 22234.545752 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 22234.545752 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 22234.545752 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 22234.545752 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 1690 # number of cycles access was blocked
+system.cpu.toL2Bus.trans_dist::ReadReq 7205652 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 7205652 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 735005 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq 9840757 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 20 # Transaction distribution
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+system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10339627 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6248397 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 16588024 # Packet count per connected master and slave (bytes)
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+system.cpu.toL2Bus.pkt_size::total 554335040 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 9840776 # Total snoops (count)
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+system.cpu.toL2Bus.snoop_fanout::mean 5.531838 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.498985 # Request fanout histogram
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+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 8662542 46.82% 46.82% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 9840757 53.18% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 18503299 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 5066671498 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 7754858551 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 4142472532 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
+system.cpu.icache.tags.replacements 5169293 # number of replacements
+system.cpu.icache.tags.tagsinuse 510.870067 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 364901080 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 5169803 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 70.583169 # Average number of references to valid blocks.
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+system.cpu.icache.tags.occ_blocks::cpu.inst 510.870067 # Average occupied blocks per requestor
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+system.cpu.icache.tags.occ_percent::total 0.997793 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 325 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 745315243 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 745315243 # Number of data accesses
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+system.cpu.icache.ReadReq_hits::total 364901109 # number of ReadReq hits
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+system.cpu.icache.overall_hits::total 364901109 # number of overall hits
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+system.cpu.icache.demand_miss_latency::total 41478755019 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 41478755019 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 41478755019 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 370072710 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 370072710 # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total 370072710 # number of demand (read+write) accesses
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-system.cpu.dcache.ReadReq_hits::total 328318489 # number of ReadReq hits
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-system.cpu.dcache.LoadLockedReq_hits::total 5745 # number of LoadLockedReq hits
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system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits
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-system.cpu.dcache.SoftPFReq_misses::total 156 # number of SoftPFReq misses
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-system.cpu.dcache.demand_miss_latency::total 134694562447 # number of demand (read+write) miss cycles
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-system.cpu.dcache.LoadLockedReq_accesses::total 5748 # number of LoadLockedReq accesses(hits+misses)
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-system.cpu.dcache.overall_miss_rate::total 0.005694 # miss rate for overall accesses
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 41146.199808 # average ReadReq miss latency
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.dcache.writebacks::total 91367 # number of writebacks
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-system.cpu.dcache.ReadReq_mshr_hits::total 881385 # number of ReadReq MSHR hits
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+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7265.097204 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7265.097204 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8130.637636 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8130.637636 # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9516.274113 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 9516.274113 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9515.950913 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 9515.950913 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 395726778000 # Number of ticks simulated
final_tick 395726778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 935276 # Simulator instruction rate (inst/s)
-host_op_rate 1151448 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 577711928 # Simulator tick rate (ticks/s)
-host_mem_usage 250216 # Number of bytes of host memory used
-host_seconds 684.99 # Real time elapsed on the host
+host_inst_rate 1695212 # Simulator instruction rate (inst/s)
+host_op_rate 2087030 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1047118075 # Simulator tick rate (ticks/s)
+host_mem_usage 304696 # Number of bytes of host memory used
+host_seconds 377.92 # Real time elapsed on the host
sim_insts 640654410 # Number of instructions simulated
sim_ops 788730069 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 6503253596 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4215120183 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10718373779 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 10718373779 # Throughput (bytes/s)
-system.membus.data_through_bus 4241547521 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 893703777 # Transaction distribution
+system.membus.trans_dist::ReadResp 893709516 # Transaction distribution
+system.membus.trans_dist::WriteReq 128951477 # Transaction distribution
+system.membus.trans_dist::WriteResp 128951477 # Transaction distribution
+system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution
+system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution
+system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution
+system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution
+system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755796 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 2045340704 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511592 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 4241547521 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 1022670352 # Request fanout histogram
+system.membus.snoop_fanout::mean 4.629116 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::4 379292454 37.09% 37.09% # Request fanout histogram
+system.membus.snoop_fanout::5 643377898 62.91% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 4 # Request fanout histogram
+system.membus.snoop_fanout::max_value 5 # Request fanout histogram
+system.membus.snoop_fanout::total 1022670352 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
sim_ticks 1043695084000 # Number of ticks simulated
final_tick 1043695084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 520727 # Simulator instruction rate (inst/s)
-host_op_rate 639745 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 850028397 # Simulator tick rate (ticks/s)
-host_mem_usage 259968 # Number of bytes of host memory used
-host_seconds 1227.84 # Real time elapsed on the host
+host_inst_rate 974812 # Simulator instruction rate (inst/s)
+host_op_rate 1197616 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1591272225 # Simulator tick rate (ticks/s)
+host_mem_usage 314196 # Number of bytes of host memory used
+host_seconds 655.89 # Real time elapsed on the host
sim_insts 639366786 # Number of instructions simulated
sim_ops 785501034 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 108537 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 17656774 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 21818480 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 21818480 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 223619 # Transaction distribution
system.membus.trans_dist::ReadResp 223619 # Transaction distribution
system.membus.trans_dist::Writeback 66098 # Transaction distribution
system.membus.trans_dist::ReadExResp 66093 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 645522 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 645522 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 22771840 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 355811 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 355811 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 355811 # Request fanout histogram
system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 54201945 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 91561 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655845 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1676261 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55916992 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 56570304 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55916992 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 883911 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 883911 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 883911 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks)
---------- Begin Simulation Statistics ----------
-sim_seconds 0.058327 # Number of seconds simulated
-sim_ticks 58326668000 # Number of ticks simulated
-final_tick 58326668000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.058385 # Number of seconds simulated
+sim_ticks 58384546000 # Number of ticks simulated
+final_tick 58384546000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 319236 # Simulator instruction rate (inst/s)
-host_op_rate 319236 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 210542764 # Simulator tick rate (ticks/s)
-host_mem_usage 275532 # Number of bytes of host memory used
-host_seconds 277.03 # Real time elapsed on the host
+host_inst_rate 341517 # Simulator instruction rate (inst/s)
+host_op_rate 341516 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 225460414 # Simulator tick rate (ticks/s)
+host_mem_usage 300016 # Number of bytes of host memory used
+host_seconds 258.96 # Real time elapsed on the host
sim_insts 88438073 # Number of instructions simulated
sim_ops 88438073 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 10663104 # Number of bytes read from this memory
system.physmem.bytes_read::total 10663104 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 515520 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 515520 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 515328 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 515328 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7299072 # Number of bytes written to this memory
system.physmem.bytes_written::total 7299072 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 166611 # Number of read requests responded to by this memory
system.physmem.num_reads::total 166611 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 114048 # Number of write requests responded to by this memory
system.physmem.num_writes::total 114048 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 182816958 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 182816958 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 8838496 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 8838496 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 125141248 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 125141248 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 125141248 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 182816958 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 307958205 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 182635727 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 182635727 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 8826445 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 8826445 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 125017192 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 125017192 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 125017192 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 182635727 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 307652919 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 166611 # Number of read requests accepted
system.physmem.writeReqs 114048 # Number of write requests accepted
system.physmem.readBursts 166611 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 114048 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 10662720 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7297088 # Total number of bytes written to DRAM
+system.physmem.bytesReadDRAM 10662592 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue
+system.physmem.bytesWritten 7297152 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 10663104 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7299072 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 10470 # Per bank write bursts
-system.physmem.perBankRdBursts::1 10514 # Per bank write bursts
+system.physmem.perBankRdBursts::0 10468 # Per bank write bursts
+system.physmem.perBankRdBursts::1 10513 # Per bank write bursts
system.physmem.perBankRdBursts::2 10311 # Per bank write bursts
-system.physmem.perBankRdBursts::3 10091 # Per bank write bursts
-system.physmem.perBankRdBursts::4 10432 # Per bank write bursts
+system.physmem.perBankRdBursts::3 10090 # Per bank write bursts
+system.physmem.perBankRdBursts::4 10431 # Per bank write bursts
system.physmem.perBankRdBursts::5 10426 # Per bank write bursts
-system.physmem.perBankRdBursts::6 9845 # Per bank write bursts
-system.physmem.perBankRdBursts::7 10300 # Per bank write bursts
+system.physmem.perBankRdBursts::6 9846 # Per bank write bursts
+system.physmem.perBankRdBursts::7 10302 # Per bank write bursts
system.physmem.perBankRdBursts::8 10593 # Per bank write bursts
system.physmem.perBankRdBursts::9 10643 # Per bank write bursts
-system.physmem.perBankRdBursts::10 10596 # Per bank write bursts
+system.physmem.perBankRdBursts::10 10595 # Per bank write bursts
system.physmem.perBankRdBursts::11 10255 # Per bank write bursts
system.physmem.perBankRdBursts::12 10302 # Per bank write bursts
system.physmem.perBankRdBursts::13 10651 # Per bank write bursts
system.physmem.perBankRdBursts::14 10528 # Per bank write bursts
-system.physmem.perBankRdBursts::15 10648 # Per bank write bursts
+system.physmem.perBankRdBursts::15 10649 # Per bank write bursts
system.physmem.perBankWrBursts::0 7087 # Per bank write bursts
system.physmem.perBankWrBursts::1 7261 # Per bank write bursts
system.physmem.perBankWrBursts::2 7255 # Per bank write bursts
system.physmem.perBankWrBursts::3 6999 # Per bank write bursts
system.physmem.perBankWrBursts::4 7126 # Per bank write bursts
-system.physmem.perBankWrBursts::5 7177 # Per bank write bursts
+system.physmem.perBankWrBursts::5 7178 # Per bank write bursts
system.physmem.perBankWrBursts::6 6771 # Per bank write bursts
-system.physmem.perBankWrBursts::7 7084 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7221 # Per bank write bursts
+system.physmem.perBankWrBursts::7 7079 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7222 # Per bank write bursts
system.physmem.perBankWrBursts::9 6940 # Per bank write bursts
-system.physmem.perBankWrBursts::10 7095 # Per bank write bursts
+system.physmem.perBankWrBursts::10 7097 # Per bank write bursts
system.physmem.perBankWrBursts::11 6991 # Per bank write bursts
-system.physmem.perBankWrBursts::12 6965 # Per bank write bursts
+system.physmem.perBankWrBursts::12 6967 # Per bank write bursts
system.physmem.perBankWrBursts::13 7289 # Per bank write bursts
system.physmem.perBankWrBursts::14 7284 # Per bank write bursts
system.physmem.perBankWrBursts::15 7472 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 58326641500 # Total gap between requests
+system.physmem.totGap 58384519500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 114048 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 164954 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1625 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 164957 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 1618 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 730 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 752 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 6187 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 6989 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 7028 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 7045 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 7025 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 7044 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 7045 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 7061 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 7078 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 7102 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 7263 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 7119 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 7114 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 7354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 7066 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 7021 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 727 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 754 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 6184 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 6978 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 7021 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 7028 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 7031 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 7040 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 7036 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 7069 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 7068 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 7078 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 7206 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 7162 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 7083 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 7403 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 7126 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 7023 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 54563 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 329.133809 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 195.314569 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 332.108035 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 19364 35.49% 35.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 11887 21.79% 57.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 5658 10.37% 67.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3635 6.66% 74.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2734 5.01% 79.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2059 3.77% 83.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1592 2.92% 86.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1526 2.80% 88.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 6108 11.19% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 54563 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples 54365 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 330.333707 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 195.729973 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 332.976327 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 19356 35.60% 35.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 11696 21.51% 57.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 5632 10.36% 67.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3623 6.66% 74.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2688 4.94% 79.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2044 3.76% 82.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1686 3.10% 85.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1497 2.75% 88.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 6143 11.30% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 54365 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 7019 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 23.733438 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 348.155819 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 23.733295 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 348.126500 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 7017 99.97% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 7019 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 7019 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.244052 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.228462 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.746507 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 6270 89.33% 89.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 11 0.16% 89.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 572 8.15% 97.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 129 1.84% 99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 27 0.38% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 6 0.09% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 1 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.244194 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.228515 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 0.751123 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 6265 89.26% 89.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 18 0.26% 89.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 572 8.15% 97.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 131 1.87% 99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 24 0.34% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 4 0.06% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 2 0.03% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 1 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28 2 0.03% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 7019 # Writes before turning the bus around for reads
-system.physmem.totQLat 1962392500 # Total ticks spent queuing
-system.physmem.totMemAccLat 5086236250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 833025000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11778.71 # Average queueing delay per DRAM burst
+system.physmem.totQLat 2006026500 # Total ticks spent queuing
+system.physmem.totMemAccLat 5129832750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 833015000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 12040.76 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30528.71 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 182.81 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 125.11 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 182.82 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 125.14 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 30790.76 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 182.63 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 124.98 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 182.64 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 125.02 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 2.41 # Data bus utilization in percentage
+system.physmem.busUtil 2.40 # Data bus utilization in percentage
system.physmem.busUtilRead 1.43 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.98 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.89 # Average write queue length when enqueuing
-system.physmem.readRowHits 144808 # Number of row buffer hits during reads
-system.physmem.writeRowHits 81240 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 23.87 # Average write queue length when enqueuing
+system.physmem.readRowHits 144815 # Number of row buffer hits during reads
+system.physmem.writeRowHits 81433 # Number of row buffer hits during writes
system.physmem.readRowHitRate 86.92 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 71.23 # Row buffer hit rate for writes
-system.physmem.avgGap 207820.31 # Average gap between requests
-system.physmem.pageHitRate 80.54 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 31774168500 # Time in different power states
-system.physmem.memoryStateTime::REF 1947400000 # Time in different power states
+system.physmem.writeRowHitRate 71.40 # Row buffer hit rate for writes
+system.physmem.avgGap 208026.54 # Average gap between requests
+system.physmem.pageHitRate 80.62 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 31935315750 # Time in different power states
+system.physmem.memoryStateTime::REF 1949480000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 24597717750 # Time in different power states
+system.physmem.memoryStateTime::ACT 24496780500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 307958205 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 35730 # Transaction distribution
system.membus.trans_dist::ReadResp 35730 # Transaction distribution
system.membus.trans_dist::Writeback 114048 # Transaction distribution
system.membus.trans_dist::ReadExResp 130881 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447270 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 447270 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17962176 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 17962176 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 17962176 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1302233000 # Layer occupancy (ticks)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17962176 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 17962176 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 280659 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 280659 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 280659 # Request fanout histogram
+system.membus.reqLayer0.occupancy 1302108500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1600678750 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 1600532000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 2.7 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 14594840 # Number of BP lookups
-system.cpu.branchPred.condPredicted 9449166 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 378473 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 10265774 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 6368296 # Number of BTB hits
+system.cpu.branchPred.lookups 14593516 # Number of BP lookups
+system.cpu.branchPred.condPredicted 9448617 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 379109 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 10302575 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 6369350 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 62.034251 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1700711 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 73330 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 61.822894 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1700742 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 73233 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 20553993 # DTB read hits
-system.cpu.dtb.read_misses 96885 # DTB read misses
+system.cpu.dtb.read_hits 20554145 # DTB read hits
+system.cpu.dtb.read_misses 96857 # DTB read misses
system.cpu.dtb.read_acv 9 # DTB read access violations
-system.cpu.dtb.read_accesses 20650878 # DTB read accesses
-system.cpu.dtb.write_hits 14665827 # DTB write hits
-system.cpu.dtb.write_misses 9394 # DTB write misses
+system.cpu.dtb.read_accesses 20651002 # DTB read accesses
+system.cpu.dtb.write_hits 14666071 # DTB write hits
+system.cpu.dtb.write_misses 9396 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 14675221 # DTB write accesses
-system.cpu.dtb.data_hits 35219820 # DTB hits
-system.cpu.dtb.data_misses 106279 # DTB misses
+system.cpu.dtb.write_accesses 14675467 # DTB write accesses
+system.cpu.dtb.data_hits 35220216 # DTB hits
+system.cpu.dtb.data_misses 106253 # DTB misses
system.cpu.dtb.data_acv 9 # DTB access violations
-system.cpu.dtb.data_accesses 35326099 # DTB accesses
-system.cpu.itb.fetch_hits 25536643 # ITB hits
-system.cpu.itb.fetch_misses 5175 # ITB misses
+system.cpu.dtb.data_accesses 35326469 # DTB accesses
+system.cpu.itb.fetch_hits 25540027 # ITB hits
+system.cpu.itb.fetch_misses 5176 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 25541818 # ITB accesses
+system.cpu.itb.fetch_accesses 25545203 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
-system.cpu.numCycles 116653336 # number of cpu cycles simulated
+system.cpu.numCycles 116769092 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 88438073 # Number of instructions committed
system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 1184863 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 1185538 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.319040 # CPI: cycles per instruction
-system.cpu.ipc 0.758127 # IPC: instructions per cycle
-system.cpu.tickCycles 90780036 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 25873300 # Total number of cycles that the object has spent stopped
-system.cpu.icache.tags.replacements 152673 # number of replacements
-system.cpu.icache.tags.tagsinuse 1933.703122 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 25381921 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 154721 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 164.049618 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 41483619250 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1933.703122 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.944191 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.944191 # Average percentage of cache occupancy
+system.cpu.cpi 1.320349 # CPI: cycles per instruction
+system.cpu.ipc 0.757376 # IPC: instructions per cycle
+system.cpu.tickCycles 90792552 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 25976540 # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements 153164 # number of replacements
+system.cpu.icache.tags.tagsinuse 1933.730829 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 25384814 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 155212 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 163.549300 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 41528149250 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 1933.730829 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.944205 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.944205 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 1044 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 797 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 798 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 51228007 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 51228007 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 25381921 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 25381921 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 25381921 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 25381921 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 25381921 # number of overall hits
-system.cpu.icache.overall_hits::total 25381921 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 154722 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 154722 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 154722 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 154722 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 154722 # number of overall misses
-system.cpu.icache.overall_misses::total 154722 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 2515300997 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 2515300997 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 2515300997 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 2515300997 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 2515300997 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 2515300997 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 25536643 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 25536643 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 25536643 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 25536643 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 25536643 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 25536643 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006059 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.006059 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.006059 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.006059 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.006059 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.006059 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16256.905915 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16256.905915 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16256.905915 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16256.905915 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16256.905915 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16256.905915 # average overall miss latency
+system.cpu.icache.tags.tag_accesses 51235266 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 51235266 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 25384814 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 25384814 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 25384814 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 25384814 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 25384814 # number of overall hits
+system.cpu.icache.overall_hits::total 25384814 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 155213 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 155213 # number of ReadReq misses
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+system.cpu.icache.demand_misses::total 155213 # number of demand (read+write) misses
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-system.cpu.dcache.demand_avg_mshr_miss_latency::total 60343.943565 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60343.943565 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 60343.943565 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39650.354755 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39650.354755 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69520.033435 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69520.033435 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60581.145360 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 60581.145360 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60581.145360 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 60581.145360 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.022262 # Number of seconds simulated
-sim_ticks 22262172500 # Number of ticks simulated
-final_tick 22262172500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.022330 # Number of seconds simulated
+sim_ticks 22329989500 # Number of ticks simulated
+final_tick 22329989500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 164105 # Simulator instruction rate (inst/s)
-host_op_rate 164105 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 45900767 # Simulator tick rate (ticks/s)
-host_mem_usage 245260 # Number of bytes of host memory used
-host_seconds 485.01 # Real time elapsed on the host
+host_inst_rate 232150 # Simulator instruction rate (inst/s)
+host_op_rate 232150 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 65131135 # Simulator tick rate (ticks/s)
+host_mem_usage 301288 # Number of bytes of host memory used
+host_seconds 342.85 # Real time elapsed on the host
sim_insts 79591756 # Number of instructions simulated
sim_ops 79591756 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 487296 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10152448 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10639744 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 487296 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 487296 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7297472 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7297472 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 7614 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 158632 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 166246 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 114023 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 114023 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 21888969 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 456040308 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 477929277 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 21888969 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 21888969 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 327796939 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 327796939 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 327796939 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 21888969 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 456040308 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 805726216 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 166246 # Number of read requests accepted
-system.physmem.writeReqs 114023 # Number of write requests accepted
-system.physmem.readBursts 166246 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 114023 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 10639232 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7295808 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 10639744 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 7297472 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst 487424 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10151616 # Number of bytes read from this memory
+system.physmem.bytes_read::total 10639040 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 487424 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 487424 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7296896 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7296896 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 7616 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 158619 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 166235 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 114014 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 114014 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 21828223 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 454618037 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 476446261 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 21828223 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 21828223 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 326775613 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 326775613 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 326775613 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 21828223 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 454618037 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 803221873 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 166235 # Number of read requests accepted
+system.physmem.writeReqs 114014 # Number of write requests accepted
+system.physmem.readBursts 166235 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 114014 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 10638592 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue
+system.physmem.bytesWritten 7294848 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 10639040 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 7296896 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 10440 # Per bank write bursts
-system.physmem.perBankRdBursts::1 10463 # Per bank write bursts
-system.physmem.perBankRdBursts::2 10311 # Per bank write bursts
-system.physmem.perBankRdBursts::3 10061 # Per bank write bursts
-system.physmem.perBankRdBursts::4 10417 # Per bank write bursts
-system.physmem.perBankRdBursts::5 10395 # Per bank write bursts
-system.physmem.perBankRdBursts::6 9841 # Per bank write bursts
-system.physmem.perBankRdBursts::7 10308 # Per bank write bursts
-system.physmem.perBankRdBursts::8 10597 # Per bank write bursts
-system.physmem.perBankRdBursts::9 10638 # Per bank write bursts
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system.physmem.perBankRdBursts::10 10546 # Per bank write bursts
-system.physmem.perBankRdBursts::11 10227 # Per bank write bursts
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system.physmem.perBankRdBursts::12 10273 # Per bank write bursts
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-system.physmem.perBankRdBursts::15 10621 # Per bank write bursts
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system.physmem.perBankWrBursts::0 7082 # Per bank write bursts
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system.physmem.perBankWrBursts::3 6997 # Per bank write bursts
system.physmem.perBankWrBursts::4 7126 # Per bank write bursts
-system.physmem.perBankWrBursts::5 7170 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6776 # Per bank write bursts
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system.physmem.perBankWrBursts::9 6942 # Per bank write bursts
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-system.physmem.perBankWrBursts::11 6990 # Per bank write bursts
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system.physmem.perBankWrBursts::12 6966 # Per bank write bursts
-system.physmem.perBankWrBursts::13 7288 # Per bank write bursts
+system.physmem.perBankWrBursts::13 7287 # Per bank write bursts
system.physmem.perBankWrBursts::14 7284 # Per bank write bursts
system.physmem.perBankWrBursts::15 7472 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 22262139000 # Total gap between requests
+system.physmem.totGap 22329955500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 166246 # Read request sizes (log2)
+system.physmem.readPktSize::6 166235 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 114023 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 51670 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 53911 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 45458 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::36 80 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 52156 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 343.855817 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 201.745106 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 344.281593 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 18285 35.06% 35.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 10756 20.62% 55.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 5580 10.70% 66.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3146 6.03% 72.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2660 5.10% 77.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1727 3.31% 80.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1787 3.43% 84.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1244 2.39% 86.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 6971 13.37% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 52156 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6968 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 23.856056 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 342.059287 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 6967 99.99% 99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 51907 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 345.459688 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 202.593638 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 345.239241 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 18141 34.95% 34.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 10684 20.58% 55.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 5599 10.79% 66.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2999 5.78% 72.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2733 5.27% 77.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1724 3.32% 80.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1780 3.43% 84.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1211 2.33% 86.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 7036 13.56% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 51907 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6971 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 23.843208 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 342.237754 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 6969 99.97% 99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6968 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6968 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.360075 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.330777 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.045922 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 6065 87.04% 87.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 29 0.42% 87.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 476 6.83% 94.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 227 3.26% 97.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 92 1.32% 98.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 39 0.56% 99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 17 0.24% 99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 11 0.16% 99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 8 0.11% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 3 0.04% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6968 # Writes before turning the bus around for reads
-system.physmem.totQLat 5413019750 # Total ticks spent queuing
-system.physmem.totMemAccLat 8529982250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 831190000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 32561.87 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 6971 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6971 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.350882 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.321302 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.052955 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 6113 87.69% 87.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 29 0.42% 88.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 435 6.24% 94.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 209 3.00% 97.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 90 1.29% 98.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 57 0.82% 99.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 19 0.27% 99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 5 0.07% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 4 0.06% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 6 0.09% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 4 0.06% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6971 # Writes before turning the bus around for reads
+system.physmem.totQLat 5659900500 # Total ticks spent queuing
+system.physmem.totMemAccLat 8776675500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 831140000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 34049.02 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 51311.87 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 477.91 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 327.72 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 477.93 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 327.80 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 52799.02 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 476.43 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 326.68 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 476.45 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 326.78 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 6.29 # Data bus utilization in percentage
-system.physmem.busUtilRead 3.73 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 2.56 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing
-system.physmem.readRowHits 146096 # Number of row buffer hits during reads
-system.physmem.writeRowHits 81976 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 87.88 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 71.89 # Row buffer hit rate for writes
-system.physmem.avgGap 79431.33 # Average gap between requests
-system.physmem.pageHitRate 81.38 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 9551525000 # Time in different power states
-system.physmem.memoryStateTime::REF 743340000 # Time in different power states
+system.physmem.busUtil 6.27 # Data bus utilization in percentage
+system.physmem.busUtilRead 3.72 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 2.55 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.81 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.55 # Average write queue length when enqueuing
+system.physmem.readRowHits 146045 # Number of row buffer hits during reads
+system.physmem.writeRowHits 82245 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 87.86 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 72.14 # Row buffer hit rate for writes
+system.physmem.avgGap 79678.98 # Average gap between requests
+system.physmem.pageHitRate 81.46 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 9562649000 # Time in different power states
+system.physmem.memoryStateTime::REF 745420000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 11966317750 # Time in different power states
+system.physmem.memoryStateTime::ACT 12015383500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 805726216 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 35460 # Transaction distribution
-system.membus.trans_dist::ReadResp 35460 # Transaction distribution
-system.membus.trans_dist::Writeback 114023 # Transaction distribution
-system.membus.trans_dist::ReadExReq 130786 # Transaction distribution
-system.membus.trans_dist::ReadExResp 130786 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446515 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 446515 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17937216 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 17937216 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 17937216 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1235956000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 5.6 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1525146000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 6.9 # Layer utilization (%)
+system.membus.trans_dist::ReadReq 35446 # Transaction distribution
+system.membus.trans_dist::ReadResp 35446 # Transaction distribution
+system.membus.trans_dist::Writeback 114014 # Transaction distribution
+system.membus.trans_dist::ReadExReq 130789 # Transaction distribution
+system.membus.trans_dist::ReadExResp 130789 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446484 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 446484 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17935936 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 17935936 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 280249 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 280249 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 280249 # Request fanout histogram
+system.membus.reqLayer0.occupancy 1235861000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 5.5 # Layer utilization (%)
+system.membus.respLayer1.occupancy 1525180500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 6.8 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 16618538 # Number of BP lookups
-system.cpu.branchPred.condPredicted 10751969 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 360716 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 10752045 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7371197 # Number of BTB hits
+system.cpu.branchPred.lookups 16618969 # Number of BP lookups
+system.cpu.branchPred.condPredicted 10749423 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 361100 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 10742405 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7368684 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 68.556233 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1990414 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 2895 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 68.594360 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1994688 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 3025 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 22632838 # DTB read hits
-system.cpu.dtb.read_misses 226204 # DTB read misses
-system.cpu.dtb.read_acv 19 # DTB read access violations
-system.cpu.dtb.read_accesses 22859042 # DTB read accesses
-system.cpu.dtb.write_hits 15863725 # DTB write hits
-system.cpu.dtb.write_misses 44788 # DTB write misses
-system.cpu.dtb.write_acv 4 # DTB write access violations
-system.cpu.dtb.write_accesses 15908513 # DTB write accesses
-system.cpu.dtb.data_hits 38496563 # DTB hits
-system.cpu.dtb.data_misses 270992 # DTB misses
-system.cpu.dtb.data_acv 23 # DTB access violations
-system.cpu.dtb.data_accesses 38767555 # DTB accesses
-system.cpu.itb.fetch_hits 13910081 # ITB hits
-system.cpu.itb.fetch_misses 31577 # ITB misses
+system.cpu.dtb.read_hits 22640578 # DTB read hits
+system.cpu.dtb.read_misses 225727 # DTB read misses
+system.cpu.dtb.read_acv 15 # DTB read access violations
+system.cpu.dtb.read_accesses 22866305 # DTB read accesses
+system.cpu.dtb.write_hits 15860065 # DTB write hits
+system.cpu.dtb.write_misses 44717 # DTB write misses
+system.cpu.dtb.write_acv 7 # DTB write access violations
+system.cpu.dtb.write_accesses 15904782 # DTB write accesses
+system.cpu.dtb.data_hits 38500643 # DTB hits
+system.cpu.dtb.data_misses 270444 # DTB misses
+system.cpu.dtb.data_acv 22 # DTB access violations
+system.cpu.dtb.data_accesses 38771087 # DTB accesses
+system.cpu.itb.fetch_hits 13913295 # ITB hits
+system.cpu.itb.fetch_misses 31383 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 13941658 # ITB accesses
+system.cpu.itb.fetch_accesses 13944678 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
-system.cpu.numCycles 44524349 # number of cpu cycles simulated
+system.cpu.numCycles 44659983 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 15777207 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 106088567 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 16618538 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9361611 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 27200271 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 960062 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 179 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 5019 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 332851 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13910081 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 206082 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.icacheStallCycles 15776454 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 106093576 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 16618969 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9363372 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 27339445 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 961528 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 166 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 5126 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 335016 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 84 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 13913295 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 207298 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 43795615 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.422356 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.133763 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 43937055 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.414672 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.131710 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 24068312 54.96% 54.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1538186 3.51% 58.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1404705 3.21% 61.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1522843 3.48% 65.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 4236021 9.67% 74.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1845751 4.21% 79.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 684777 1.56% 80.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1069219 2.44% 83.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 7425801 16.96% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 24208191 55.10% 55.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1538198 3.50% 58.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1405905 3.20% 61.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1524697 3.47% 65.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 4231594 9.63% 74.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1847884 4.21% 79.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 684699 1.56% 80.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1071609 2.44% 83.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 7424278 16.90% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 43795615 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.373246 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.382709 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 15090251 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 9271065 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 18462331 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 590423 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 381545 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3739004 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 100344 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 103984343 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 314766 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 381545 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 15473555 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 6415386 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 96680 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18647393 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 2781056 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 102842787 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 3945 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 148156 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 330502 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 2246834 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 61884966 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 124097859 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 123771677 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 326181 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 43937055 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.372122 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.375585 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 15090542 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 9411892 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 18462094 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 590748 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 381779 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3738870 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 100752 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 103984898 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 316746 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 381779 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 15474298 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 6446400 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 97317 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 18646914 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 2890347 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 102848317 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 4603 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 150963 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 325598 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 2361182 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 61896036 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 124089387 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 123759844 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 329542 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 9338085 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 5769 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 5827 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 2465534 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 23256981 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 16451468 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1256796 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 554193 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 91273922 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 5644 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 89085619 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 78698 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 11197079 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 4703509 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1061 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 43795615 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.034122 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.247476 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 9349155 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 5813 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 5869 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 2465054 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 23265818 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 16448253 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1251433 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 545590 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 91286622 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 5695 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 89090659 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 79052 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 11213817 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 4716109 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1112 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 43937055 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.027688 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.246728 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 17182377 39.23% 39.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 5792116 13.23% 52.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 5098261 11.64% 64.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 4417263 10.09% 74.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4344645 9.92% 84.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2649252 6.05% 90.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1946446 4.44% 94.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1380364 3.15% 97.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 984891 2.25% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 17318675 39.42% 39.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 5798510 13.20% 52.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 5098508 11.60% 64.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 4414835 10.05% 74.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 4342383 9.88% 84.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2650303 6.03% 90.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1951252 4.44% 94.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1378643 3.14% 97.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 983946 2.24% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 43795615 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 43937055 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 244209 9.65% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1174646 46.40% 56.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 1112477 43.95% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 243742 9.63% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1177038 46.48% 56.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 1111319 43.89% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 49643458 55.73% 55.73% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 44096 0.05% 55.78% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 121526 0.14% 55.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 55.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 121394 0.14% 56.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 58 0.00% 56.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 39070 0.04% 56.09% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 49642313 55.72% 55.72% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 44169 0.05% 55.77% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.77% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 122147 0.14% 55.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 55.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 121699 0.14% 56.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 55 0.00% 56.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 39048 0.04% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 23048961 25.87% 81.96% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 16066967 18.04% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 23057514 25.88% 81.97% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 16063627 18.03% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 89085619 # Type of FU issued
-system.cpu.iq.rate 2.000829 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2531332 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.028415 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 223962824 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 102066580 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 87151859 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 614059 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 431019 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 300727 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 91309756 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 307195 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1661224 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 89090659 # Type of FU issued
+system.cpu.iq.rate 1.994865 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2532099 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.028422 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 224114042 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 102090455 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 87155295 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 615482 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 436927 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 301089 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 91314862 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 307896 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1660010 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 2980343 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6431 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 21452 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1838091 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 2989180 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6359 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 21743 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1834876 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2952 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 325709 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2985 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 325715 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 381545 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1215876 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 4878836 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 100803158 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 157110 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 23256981 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 16451468 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 5576 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 3364 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 4856172 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 21452 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 149650 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 157694 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 307344 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 88311132 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 22859779 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 774487 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 381779 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1212086 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 4898049 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 100815278 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 146031 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 23265818 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 16448253 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 5611 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 3372 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 4875472 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 21743 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 149411 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 157245 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 306656 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 88317091 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 22866843 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 773568 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 9523592 # number of nop insts executed
-system.cpu.iew.exec_refs 38768607 # number of memory reference insts executed
-system.cpu.iew.exec_branches 15170240 # Number of branches executed
-system.cpu.iew.exec_stores 15908828 # Number of stores executed
-system.cpu.iew.exec_rate 1.983435 # Inst execution rate
-system.cpu.iew.wb_sent 87867079 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 87452586 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 33893139 # num instructions producing a value
-system.cpu.iew.wb_consumers 44339625 # num instructions consuming a value
+system.cpu.iew.exec_nop 9522961 # number of nop insts executed
+system.cpu.iew.exec_refs 38771937 # number of memory reference insts executed
+system.cpu.iew.exec_branches 15172750 # Number of branches executed
+system.cpu.iew.exec_stores 15905094 # Number of stores executed
+system.cpu.iew.exec_rate 1.977544 # Inst execution rate
+system.cpu.iew.wb_sent 87870804 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 87456384 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 33898733 # num instructions producing a value
+system.cpu.iew.wb_consumers 44340261 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.964152 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.764398 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.958272 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.764514 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 9260506 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 9275726 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 262230 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 42432313 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.081920 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.885099 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 262115 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 42571128 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.075131 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.882631 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 20891279 49.23% 49.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 6327574 14.91% 64.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 2939948 6.93% 71.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 1761291 4.15% 75.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1656008 3.90% 79.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1140180 2.69% 81.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1204228 2.84% 84.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 795411 1.87% 86.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5716394 13.47% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 21025343 49.39% 49.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 6328820 14.87% 64.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 2946361 6.92% 71.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 1760662 4.14% 75.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1654958 3.89% 79.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1139679 2.68% 81.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1203795 2.83% 84.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 795933 1.87% 86.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5715577 13.43% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 42432313 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 42571128 # Number of insts commited each cycle
system.cpu.commit.committedInsts 88340672 # Number of instructions committed
system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction
-system.cpu.commit.bw_lim_events 5716394 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 5715577 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 132999755 # The number of ROB reads
-system.cpu.rob.rob_writes 196569210 # The number of ROB writes
-system.cpu.timesIdled 47704 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 728734 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 133154607 # The number of ROB reads
+system.cpu.rob.rob_writes 196602232 # The number of ROB writes
+system.cpu.timesIdled 47762 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 722928 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.559409 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.559409 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.787601 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.787601 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 116880103 # number of integer regfile reads
-system.cpu.int_regfile_writes 57914968 # number of integer regfile writes
-system.cpu.fp_regfile_reads 255764 # number of floating regfile reads
-system.cpu.fp_regfile_writes 241194 # number of floating regfile writes
-system.cpu.misc_regfile_reads 38207 # number of misc regfile reads
+system.cpu.cpi 0.561113 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.561113 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.782172 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.782172 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 116877675 # number of integer regfile reads
+system.cpu.int_regfile_writes 57921110 # number of integer regfile writes
+system.cpu.fp_regfile_reads 255696 # number of floating regfile reads
+system.cpu.fp_regfile_writes 241715 # number of floating regfile writes
+system.cpu.misc_regfile_reads 38130 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 1351038673 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 157664 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 157663 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 168884 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 143407 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 143407 # Transaction distribution
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-system.cpu.toL2Bus.pkt_count::total 771025 # Packet count per connected master and slave (bytes)
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-system.cpu.toL2Bus.tot_pkt_size::total 30077056 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 30077056 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 403861500 # Layer occupancy (ticks)
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+system.cpu.toL2Bus.trans_dist::ReadExResp 143405 # Transaction distribution
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+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
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system.cpu.toL2Bus.reqLayer0.utilization 1.8 # Layer utilization (%)
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-system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
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-system.cpu.icache.tags.tagsinuse 1918.549362 # Cycle average of tags in use
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system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
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-system.cpu.icache.ReadReq_avg_miss_latency::total 18471.479758 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18471.479758 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18471.479758 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18471.479758 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 18471.479758 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 421 # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses 27922137 # Number of tag accesses
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16145.916190 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 16145.916190 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 132342 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 30650.396196 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 161877 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 164409 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.984599 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements 132334 # number of replacements
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system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26717.381554 # Average occupied blocks per requestor
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system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005804 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.005804 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48796.384587 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48796.384587 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93006.441153 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93006.441153 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79658.267029 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 79658.267029 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79658.267029 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 79658.267029 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49123.095264 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49123.095264 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 94605.186710 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 94605.186710 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 89750 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 89750 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80864.320088 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 80864.320088 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80864.320088 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 80864.320088 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 44221003000 # Number of ticks simulated
final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3162077 # Simulator instruction rate (inst/s)
-host_op_rate 3162075 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1582850501 # Simulator tick rate (ticks/s)
-host_mem_usage 263736 # Number of bytes of host memory used
-host_seconds 27.94 # Real time elapsed on the host
+host_inst_rate 2813944 # Simulator instruction rate (inst/s)
+host_op_rate 2813942 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1408584494 # Simulator tick rate (ticks/s)
+host_mem_usage 287952 # Number of bytes of host memory used
+host_seconds 31.39 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 12937468537 # Throughput (bytes/s)
-system.membus.data_through_bus 572107835 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 108714711 # Transaction distribution
+system.membus.trans_dist::ReadResp 108714711 # Transaction distribution
+system.membus.trans_dist::WriteReq 14613377 # Transaction distribution
+system.membus.trans_dist::WriteResp 14613377 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 176876146 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 69780030 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 246656176 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 353752292 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 218355543 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 572107835 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 123328088 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.717096 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.450410 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 34890015 28.29% 28.29% # Request fanout histogram
+system.membus.snoop_fanout::1 88438073 71.71% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 123328088 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
sim_ticks 133634727000 # Number of ticks simulated
final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1560477 # Simulator instruction rate (inst/s)
-host_op_rate 1560477 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2360564466 # Simulator tick rate (ticks/s)
-host_mem_usage 272464 # Number of bytes of host memory used
-host_seconds 56.61 # Real time elapsed on the host
+host_inst_rate 1471745 # Simulator instruction rate (inst/s)
+host_op_rate 1471745 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2226337698 # Simulator tick rate (ticks/s)
+host_mem_usage 297712 # Number of bytes of host memory used
+host_seconds 60.02 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 3239397 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 75855253 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 133682617 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 133682617 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 34272 # Transaction distribution
system.membus.trans_dist::ReadResp 34272 # Transaction distribution
system.membus.trans_dist::Writeback 113982 # Transaction distribution
system.membus.trans_dist::ReadExResp 130881 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 17864640 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 279135 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 279135 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 279135 # Request fanout histogram
system.membus.reqLayer0.occupancy 1190991000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
system.membus.respLayer1.occupancy 1486377000 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 215108158 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 137202 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152872 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577063 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 729935 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4891904 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23854016 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 28745920 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 28745920 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4891904 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23854016 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 28745920 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 449155 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 449155 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 449155 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 392952500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks)
---------- Begin Simulation Statistics ----------
-sim_seconds 0.056337 # Number of seconds simulated
-sim_ticks 56337328500 # Number of ticks simulated
-final_tick 56337328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.056374 # Number of seconds simulated
+sim_ticks 56374399500 # Number of ticks simulated
+final_tick 56374399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 184341 # Simulator instruction rate (inst/s)
-host_op_rate 235745 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 146446418 # Simulator tick rate (ticks/s)
-host_mem_usage 326872 # Number of bytes of host memory used
-host_seconds 384.70 # Real time elapsed on the host
+host_inst_rate 197105 # Simulator instruction rate (inst/s)
+host_op_rate 252068 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 156689619 # Simulator tick rate (ticks/s)
+host_mem_usage 315764 # Number of bytes of host memory used
+host_seconds 359.78 # Real time elapsed on the host
sim_insts 70915127 # Number of instructions simulated
sim_ops 90690083 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.num_reads::total 128862 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory
system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 146389050 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 146389050 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 5749367 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 5749367 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 95369520 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 95369520 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 95369520 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 146389050 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 241758570 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 146292787 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 146292787 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 5745587 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 5745587 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 95306807 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 95306807 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 95306807 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 146292787 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 241599593 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 128862 # Number of read requests accepted
system.physmem.writeReqs 83951 # Number of write requests accepted
system.physmem.readBursts 128862 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 8246784 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue
-system.physmem.bytesWritten 5371008 # Total number of bytes written to DRAM
+system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 8247168 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue
system.physmem.perBankRdBursts::13 7876 # Per bank write bursts
system.physmem.perBankRdBursts::14 7976 # Per bank write bursts
system.physmem.perBankRdBursts::15 8004 # Per bank write bursts
-system.physmem.perBankWrBursts::0 5182 # Per bank write bursts
+system.physmem.perBankWrBursts::0 5186 # Per bank write bursts
system.physmem.perBankWrBursts::1 5376 # Per bank write bursts
system.physmem.perBankWrBursts::2 5285 # Per bank write bursts
system.physmem.perBankWrBursts::3 5155 # Per bank write bursts
system.physmem.perBankWrBursts::4 5265 # Per bank write bursts
system.physmem.perBankWrBursts::5 5517 # Per bank write bursts
-system.physmem.perBankWrBursts::6 5198 # Per bank write bursts
+system.physmem.perBankWrBursts::6 5196 # Per bank write bursts
system.physmem.perBankWrBursts::7 5049 # Per bank write bursts
system.physmem.perBankWrBursts::8 5033 # Per bank write bursts
system.physmem.perBankWrBursts::9 5086 # Per bank write bursts
system.physmem.perBankWrBursts::15 5224 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 56337297000 # Total gap between requests
+system.physmem.totGap 56374368000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 83951 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 126556 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 2278 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 126558 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 2276 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 610 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 624 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 4267 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 5149 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 5165 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 5169 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 641 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 651 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 4263 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 5153 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 5162 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 5162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5164 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 5168 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 5166 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 5182 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 5177 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 5179 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 5351 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 5232 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 5236 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 5687 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 5245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 5159 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 5166 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 5165 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 5166 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 5162 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 5289 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 5242 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 5201 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 5740 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 5259 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 5156 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 38348 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 355.034109 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 215.640084 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 336.462166 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 12103 31.56% 31.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 8116 21.16% 52.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 4102 10.70% 63.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2869 7.48% 70.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2471 6.44% 77.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1658 4.32% 81.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1256 3.28% 84.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1197 3.12% 88.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 4576 11.93% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 38348 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 24.976149 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 361.694607 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 5154 99.94% 99.94% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 38259 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 355.901827 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 215.943020 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 337.187447 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 12097 31.62% 31.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 8058 21.06% 52.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 4075 10.65% 63.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2806 7.33% 70.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2532 6.62% 77.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1601 4.18% 81.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1324 3.46% 84.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1160 3.03% 87.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 4606 12.04% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 38259 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 5153 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 24.995537 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 361.849882 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 5150 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.273415 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.256579 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.772702 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 4535 87.94% 87.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 9 0.17% 88.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 476 9.23% 97.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 113 2.19% 99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 16 0.31% 99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 5 0.10% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 2 0.04% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads
-system.physmem.totQLat 1494390000 # Total ticks spent queuing
-system.physmem.totMemAccLat 3910440000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.rdPerTurnAround::total 5153 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 5153 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.286435 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.268739 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 0.792681 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 4505 87.42% 87.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 6 0.12% 87.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 503 9.76% 97.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 112 2.17% 99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 16 0.31% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 4 0.08% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 5 0.10% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 5153 # Writes before turning the bus around for reads
+system.physmem.totQLat 1533288750 # Total ticks spent queuing
+system.physmem.totMemAccLat 3949338750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 644280000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11597.36 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 11899.24 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30347.36 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 146.38 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 95.34 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 146.39 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 95.37 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 30649.24 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 146.29 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 95.28 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 146.29 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 95.31 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 1.89 # Data bus utilization in percentage
system.physmem.busUtilRead 1.14 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.43 # Average write queue length when enqueuing
-system.physmem.readRowHits 112251 # Number of row buffer hits during reads
-system.physmem.writeRowHits 62167 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 87.11 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 74.05 # Row buffer hit rate for writes
-system.physmem.avgGap 264726.76 # Average gap between requests
-system.physmem.pageHitRate 81.96 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 31175393250 # Time in different power states
-system.physmem.memoryStateTime::REF 1881100000 # Time in different power states
+system.physmem.avgWrQLen 23.42 # Average write queue length when enqueuing
+system.physmem.readRowHits 112227 # Number of row buffer hits during reads
+system.physmem.writeRowHits 62289 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 87.09 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 74.20 # Row buffer hit rate for writes
+system.physmem.avgGap 264900.96 # Average gap between requests
+system.physmem.pageHitRate 82.01 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 30998356250 # Time in different power states
+system.physmem.memoryStateTime::REF 1882400000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 23277299250 # Time in different power states
+system.physmem.memoryStateTime::ACT 23491967500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 241758570 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 26583 # Transaction distribution
system.membus.trans_dist::ReadResp 26583 # Transaction distribution
system.membus.trans_dist::Writeback 83951 # Transaction distribution
system.membus.trans_dist::ReadExResp 102279 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341675 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 341675 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620032 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 13620032 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 13620032 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 942262500 # Layer occupancy (ticks)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620032 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 13620032 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 212813 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 212813 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 212813 # Request fanout histogram
+system.membus.reqLayer0.occupancy 942245500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1221459500 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 1221409750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 2.2 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 14808792 # Number of BP lookups
-system.cpu.branchPred.condPredicted 9910132 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 393085 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9534896 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 6736289 # Number of BTB hits
+system.cpu.branchPred.lookups 14808790 # Number of BP lookups
+system.cpu.branchPred.condPredicted 9910130 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 393084 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9534894 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 6736290 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 70.648794 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 70.648819 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1716012 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
-system.cpu.numCycles 112674657 # number of cpu cycles simulated
+system.cpu.numCycles 112748799 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 70915127 # Number of instructions committed
system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 1227274 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 1227279 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.588866 # CPI: cycles per instruction
-system.cpu.ipc 0.629380 # IPC: instructions per cycle
-system.cpu.tickCycles 93712970 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 18961687 # Total number of cycles that the object has spent stopped
+system.cpu.cpi 1.589912 # CPI: cycles per instruction
+system.cpu.ipc 0.628966 # IPC: instructions per cycle
+system.cpu.tickCycles 93715149 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 19033650 # Total number of cycles that the object has spent stopped
system.cpu.icache.tags.replacements 42434 # number of replacements
-system.cpu.icache.tags.tagsinuse 1857.452171 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 24948252 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 1857.503994 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 24948244 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 44476 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 560.937404 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 560.937225 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1857.452171 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.906959 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.906959 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 1857.503994 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.906984 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.906984 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 846 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1075 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 50029934 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 50029934 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 24948252 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 24948252 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 24948252 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 24948252 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 24948252 # number of overall hits
-system.cpu.icache.overall_hits::total 24948252 # number of overall hits
+system.cpu.icache.tags.tag_accesses 50029918 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 50029918 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 24948244 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 24948244 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 24948244 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 24948244 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 24948244 # number of overall hits
+system.cpu.icache.overall_hits::total 24948244 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 44477 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 44477 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 44477 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 44477 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 44477 # number of overall misses
system.cpu.icache.overall_misses::total 44477 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 894991489 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 894991489 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 894991489 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 894991489 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 894991489 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 894991489 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 24992729 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 24992729 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 24992729 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 24992729 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 24992729 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 24992729 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 894634739 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 894634739 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 894634739 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 894634739 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 894634739 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 894634739 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 24992721 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 24992721 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 24992721 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 24992721 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 24992721 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 24992721 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001780 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.001780 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.001780 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.001780 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001780 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001780 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20122.568721 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20122.568721 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20122.568721 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20122.568721 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20122.568721 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20122.568721 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20114.547721 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 20114.547721 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 20114.547721 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 20114.547721 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 20114.547721 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 20114.547721 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 44477 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 44477 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 44477 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804116511 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 804116511 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804116511 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 804116511 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804116511 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 804116511 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 803759261 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 803759261 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 803759261 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 803759261 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 803759261 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 803759261 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001780 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.001780 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18079.378353 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18079.378353 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18079.378353 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18079.378353 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18079.378353 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18079.378353 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18071.346111 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18071.346111 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18071.346111 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 18071.346111 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18071.346111 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 18071.346111 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 378768688 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 97959 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 97958 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 128423 # Transaction distribution
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-system.cpu.dcache.overall_miss_rate::cpu.inst 0.006110 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.006110 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38261.192341 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 38261.192341 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73712.963502 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 73712.963502 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66135.827485 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 66135.827485 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66135.827485 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 66135.827485 # average overall miss latency
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010380 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.010380 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst 0.006109 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.006109 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst 0.006109 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.006109 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38393.688101 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 38393.688101 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 74017.434891 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 74017.434891 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66402.699794 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 66402.699794 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66402.699794 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 66402.699794 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.writebacks::total 128423 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2533 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 2533 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 99029 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 99029 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst 101562 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 101562 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst 101562 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 101562 # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 99000 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 99000 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst 101533 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 101533 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst 101533 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 101533 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53482 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 53482 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107038 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::total 160520 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.inst 160520 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 160520 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1986266811 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 1986266811 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7607104750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 7607104750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9593371561 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 9593371561 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9593371561 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 9593371561 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1992994061 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 1992994061 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7637775000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 7637775000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9630769061 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 9630769061 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9630769061 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 9630769061 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002321 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.005392 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37138.977806 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37138.977806 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71069.197388 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71069.197388 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59764.338157 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 59764.338157 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59764.338157 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 59764.338157 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37264.763117 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37264.763117 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71355.733478 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71355.733478 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59997.315356 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 59997.315356 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59997.315356 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 59997.315356 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.023896 # Number of seconds simulated
-sim_ticks 23896420500 # Number of ticks simulated
-final_tick 23896420500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.032615 # Number of seconds simulated
+sim_ticks 32615215000 # Number of ticks simulated
+final_tick 32615215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 105740 # Simulator instruction rate (inst/s)
-host_op_rate 135229 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 35635051 # Simulator tick rate (ticks/s)
-host_mem_usage 262840 # Number of bytes of host memory used
-host_seconds 670.59 # Real time elapsed on the host
+host_inst_rate 86014 # Simulator instruction rate (inst/s)
+host_op_rate 110001 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 39563517 # Simulator tick rate (ticks/s)
+host_mem_usage 333060 # Number of bytes of host memory used
+host_seconds 824.38 # Real time elapsed on the host
sim_insts 70907629 # Number of instructions simulated
sim_ops 90682584 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 299392 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 7936704 # Number of bytes read from this memory
-system.physmem.bytes_read::total 8236096 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 299392 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 299392 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 5372800 # Number of bytes written to this memory
-system.physmem.bytes_written::total 5372800 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 4678 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 124011 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 128689 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 83950 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 83950 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 12528738 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 332129408 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 344658147 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 12528738 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 12528738 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 224837021 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 224837021 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 224837021 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 12528738 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 332129408 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 569495168 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 128689 # Number of read requests accepted
-system.physmem.writeReqs 83950 # Number of write requests accepted
-system.physmem.readBursts 128689 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 83950 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 8235648 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue
-system.physmem.bytesWritten 5371072 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 8236096 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 5372800 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst 133120 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 2337984 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher 7506432 # Number of bytes read from this memory
+system.physmem.bytes_read::total 9977536 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 133120 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 133120 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6303424 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6303424 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 2080 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 36531 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher 117288 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 155899 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 98491 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 98491 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 4081531 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 71683844 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher 230151235 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 305916610 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 4081531 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 4081531 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 193266364 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 193266364 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 193266364 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 4081531 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 71683844 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher 230151235 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 499182973 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 155899 # Number of read requests accepted
+system.physmem.writeReqs 98491 # Number of write requests accepted
+system.physmem.readBursts 155899 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 98491 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 9968640 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue
+system.physmem.bytesWritten 6301696 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 9977536 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 6303424 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 380 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 8141 # Per bank write bursts
-system.physmem.perBankRdBursts::1 8384 # Per bank write bursts
-system.physmem.perBankRdBursts::2 8239 # Per bank write bursts
-system.physmem.perBankRdBursts::3 8150 # Per bank write bursts
-system.physmem.perBankRdBursts::4 8295 # Per bank write bursts
-system.physmem.perBankRdBursts::5 8428 # Per bank write bursts
-system.physmem.perBankRdBursts::6 8074 # Per bank write bursts
-system.physmem.perBankRdBursts::7 7958 # Per bank write bursts
-system.physmem.perBankRdBursts::8 8067 # Per bank write bursts
-system.physmem.perBankRdBursts::9 7598 # Per bank write bursts
-system.physmem.perBankRdBursts::10 7783 # Per bank write bursts
-system.physmem.perBankRdBursts::11 7813 # Per bank write bursts
-system.physmem.perBankRdBursts::12 7877 # Per bank write bursts
-system.physmem.perBankRdBursts::13 7881 # Per bank write bursts
-system.physmem.perBankRdBursts::14 7983 # Per bank write bursts
-system.physmem.perBankRdBursts::15 8011 # Per bank write bursts
-system.physmem.perBankWrBursts::0 5183 # Per bank write bursts
-system.physmem.perBankWrBursts::1 5376 # Per bank write bursts
-system.physmem.perBankWrBursts::2 5289 # Per bank write bursts
-system.physmem.perBankWrBursts::3 5157 # Per bank write bursts
-system.physmem.perBankWrBursts::4 5266 # Per bank write bursts
-system.physmem.perBankWrBursts::5 5517 # Per bank write bursts
-system.physmem.perBankWrBursts::6 5198 # Per bank write bursts
-system.physmem.perBankWrBursts::7 5051 # Per bank write bursts
-system.physmem.perBankWrBursts::8 5029 # Per bank write bursts
-system.physmem.perBankWrBursts::9 5090 # Per bank write bursts
-system.physmem.perBankWrBursts::10 5246 # Per bank write bursts
-system.physmem.perBankWrBursts::11 5140 # Per bank write bursts
-system.physmem.perBankWrBursts::12 5343 # Per bank write bursts
-system.physmem.perBankWrBursts::13 5363 # Per bank write bursts
-system.physmem.perBankWrBursts::14 5452 # Per bank write bursts
-system.physmem.perBankWrBursts::15 5223 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 10106 # Per bank write bursts
+system.physmem.perBankRdBursts::1 10077 # Per bank write bursts
+system.physmem.perBankRdBursts::2 9750 # Per bank write bursts
+system.physmem.perBankRdBursts::3 10345 # Per bank write bursts
+system.physmem.perBankRdBursts::4 10619 # Per bank write bursts
+system.physmem.perBankRdBursts::5 10733 # Per bank write bursts
+system.physmem.perBankRdBursts::6 9548 # Per bank write bursts
+system.physmem.perBankRdBursts::7 9567 # Per bank write bursts
+system.physmem.perBankRdBursts::8 9971 # Per bank write bursts
+system.physmem.perBankRdBursts::9 9445 # Per bank write bursts
+system.physmem.perBankRdBursts::10 9639 # Per bank write bursts
+system.physmem.perBankRdBursts::11 9476 # Per bank write bursts
+system.physmem.perBankRdBursts::12 8930 # Per bank write bursts
+system.physmem.perBankRdBursts::13 9084 # Per bank write bursts
+system.physmem.perBankRdBursts::14 9062 # Per bank write bursts
+system.physmem.perBankRdBursts::15 9408 # Per bank write bursts
+system.physmem.perBankWrBursts::0 6017 # Per bank write bursts
+system.physmem.perBankWrBursts::1 6275 # Per bank write bursts
+system.physmem.perBankWrBursts::2 6171 # Per bank write bursts
+system.physmem.perBankWrBursts::3 6231 # Per bank write bursts
+system.physmem.perBankWrBursts::4 6142 # Per bank write bursts
+system.physmem.perBankWrBursts::5 6389 # Per bank write bursts
+system.physmem.perBankWrBursts::6 6054 # Per bank write bursts
+system.physmem.perBankWrBursts::7 6025 # Per bank write bursts
+system.physmem.perBankWrBursts::8 6057 # Per bank write bursts
+system.physmem.perBankWrBursts::9 6227 # Per bank write bursts
+system.physmem.perBankWrBursts::10 6350 # Per bank write bursts
+system.physmem.perBankWrBursts::11 5949 # Per bank write bursts
+system.physmem.perBankWrBursts::12 6129 # Per bank write bursts
+system.physmem.perBankWrBursts::13 6148 # Per bank write bursts
+system.physmem.perBankWrBursts::14 6212 # Per bank write bursts
+system.physmem.perBankWrBursts::15 6088 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 23896016500 # Total gap between requests
+system.physmem.totGap 32615126500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 128689 # Read request sizes (log2)
+system.physmem.readPktSize::6 155899 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 83950 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 68784 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 50927 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 6546 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 2414 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 98491 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 46242 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 51007 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::3 10907 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 7160 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 6108 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 5351 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 4799 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 4082 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 329 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 161 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 100 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 51 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 32 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 22 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 628 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 644 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 2057 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 3691 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 4468 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 4948 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 5100 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 5202 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 5301 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 5438 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 5521 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 5545 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 5656 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 6068 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 5800 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 6220 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 6095 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 5413 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 91 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 30 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 1248 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 1291 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 1960 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 2723 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 3606 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 4588 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 5262 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 5698 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 5990 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 6308 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 6755 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 7385 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 8090 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 8877 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 7957 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 7389 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 6799 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 6302 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 151 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 59 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 37607 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 361.810089 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 217.183531 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 344.455844 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 11970 31.83% 31.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 7877 20.95% 52.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 3759 10.00% 62.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2606 6.93% 69.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2473 6.58% 76.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1554 4.13% 80.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1216 3.23% 83.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1043 2.77% 86.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 5109 13.59% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 37607 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5143 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 25.009139 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 391.762417 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 5141 99.96% 99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5143 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5143 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.317908 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.294258 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.943897 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 4493 87.36% 87.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 13 0.25% 87.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 424 8.24% 95.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 146 2.84% 98.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 43 0.84% 99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 15 0.29% 99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 3 0.06% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 1 0.02% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 1 0.02% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 1 0.02% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28 1 0.02% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32 2 0.04% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5143 # Writes before turning the bus around for reads
-system.physmem.totQLat 2744774250 # Total ticks spent queuing
-system.physmem.totMemAccLat 5157561750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 643410000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 21329.90 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 91367 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 178.055709 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 111.660605 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 241.201750 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 53557 58.62% 58.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 22743 24.89% 83.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 4730 5.18% 88.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 1990 2.18% 90.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 1303 1.43% 92.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 874 0.96% 93.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 818 0.90% 94.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 792 0.87% 95.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 4560 4.99% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 91367 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 5918 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 26.315816 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean 22.639360 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 186.500180 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511 5917 99.98% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 5918 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 5918 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.638053 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.588323 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.367969 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 4586 77.49% 77.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 35 0.59% 78.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 770 13.01% 91.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 230 3.89% 94.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 141 2.38% 97.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 69 1.17% 98.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 46 0.78% 99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 20 0.34% 99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 12 0.20% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 3 0.05% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 5 0.08% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 5918 # Writes before turning the bus around for reads
+system.physmem.totQLat 7435933847 # Total ticks spent queuing
+system.physmem.totMemAccLat 10356433847 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 778800000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 47739.69 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 40079.90 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 344.64 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 224.76 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 344.66 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 224.84 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 66489.69 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 305.64 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 193.21 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 305.92 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 193.27 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 4.45 # Data bus utilization in percentage
-system.physmem.busUtilRead 2.69 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 1.76 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.39 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.67 # Average write queue length when enqueuing
-system.physmem.readRowHits 112874 # Number of row buffer hits during reads
-system.physmem.writeRowHits 62123 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 87.72 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes
-system.physmem.avgGap 112378.33 # Average gap between requests
-system.physmem.pageHitRate 82.30 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 9567571500 # Time in different power states
-system.physmem.memoryStateTime::REF 797940000 # Time in different power states
+system.physmem.busUtil 3.90 # Data bus utilization in percentage
+system.physmem.busUtilRead 2.39 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 1.51 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.56 # Average write queue length when enqueuing
+system.physmem.readRowHits 126861 # Number of row buffer hits during reads
+system.physmem.writeRowHits 35985 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 81.45 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 36.54 # Row buffer hit rate for writes
+system.physmem.avgGap 128209.15 # Average gap between requests
+system.physmem.pageHitRate 64.05 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 11335868113 # Time in different power states
+system.physmem.memoryStateTime::REF 1088880000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 13530763500 # Time in different power states
+system.physmem.memoryStateTime::ACT 20184340637 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 569495168 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 26431 # Transaction distribution
-system.membus.trans_dist::ReadResp 26431 # Transaction distribution
-system.membus.trans_dist::Writeback 83950 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 380 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 380 # Transaction distribution
-system.membus.trans_dist::ReadExReq 102258 # Transaction distribution
-system.membus.trans_dist::ReadExResp 102258 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342088 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 342088 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13608896 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 13608896 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 13608896 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 898146000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 3.8 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1183170872 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 5.0 # Layer utilization (%)
+system.membus.trans_dist::ReadReq 149976 # Transaction distribution
+system.membus.trans_dist::ReadResp 149976 # Transaction distribution
+system.membus.trans_dist::Writeback 98491 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 6 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 6 # Transaction distribution
+system.membus.trans_dist::ReadExReq 5923 # Transaction distribution
+system.membus.trans_dist::ReadExResp 5923 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 410301 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 410301 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16280960 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 16280960 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 254396 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 254396 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 254396 # Request fanout histogram
+system.membus.reqLayer0.occupancy 1082237025 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 3.3 # Layer utilization (%)
+system.membus.respLayer1.occupancy 1431940683 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 4.4 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 17877019 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11927811 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 593439 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 11204319 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 8313088 # Number of BTB hits
+system.cpu.branchPred.lookups 17209876 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11519021 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 648079 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9339439 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7675638 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 74.195388 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1978187 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 104069 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 82.185215 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1872557 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 101558 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
-system.cpu.numCycles 47792842 # number of cpu cycles simulated
+system.cpu.numCycles 65230431 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 13399730 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 91818563 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 17877019 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 10291275 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 33374868 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1293258 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 460 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 3119 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 70 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 12485707 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 222370 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 47424876 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.444936 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.221090 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 4923591 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 88199449 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 17209876 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9548195 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 59293355 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1322460 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 1971 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 4935 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 22763618 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 68177 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 64885124 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.720232 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.289546 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 25840907 54.49% 54.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2398343 5.06% 59.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2102611 4.43% 63.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2392037 5.04% 69.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1862029 3.93% 72.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1496992 3.16% 76.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1004992 2.12% 78.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1407650 2.97% 81.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 8919315 18.81% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 19096390 29.43% 29.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 8276176 12.76% 42.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 9196383 14.17% 56.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 28316175 43.64% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 47424876 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.374052 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.921178 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 9991238 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 18372924 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 15962018 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 2553700 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 544996 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3514191 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 104008 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 110994138 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 375319 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 544996 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 11354333 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 2895918 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 1063087 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 17104266 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 14462276 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 108881212 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 1310 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1983947 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 2643349 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 9691184 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 114456313 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 501643948 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 126478316 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 2998 # Number of floating rename lookups
+system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 64885124 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.263832 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.352121 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 8536355 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 18658081 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 31532227 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 5666329 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 492132 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3179364 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 171028 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 101394580 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 3046745 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 492132 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 13317145 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 5269714 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 677558 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 32193664 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 12934911 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 99186097 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 982635 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 3696460 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 54484 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 4041872 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 4848974 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 103911408 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 457625717 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 115391737 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 582 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 20827087 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 24787 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 25137 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12915604 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 25719384 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 23405570 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 6651489 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 7812944 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 105238243 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 38026 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 99646497 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 159437 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 14433434 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 35646535 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 4240 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 47424876 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.101144 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.177334 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 10282182 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 18671 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 18658 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12776141 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 24320792 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 21987717 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1318624 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2218270 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 98150566 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 34524 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 94860274 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 691673 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 7398751 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 20189182 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 738 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 64885124 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.461973 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.146315 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 16924239 35.69% 35.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 6535440 13.78% 49.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 6148782 12.97% 62.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5092843 10.74% 73.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 5223877 11.02% 84.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3271997 6.90% 91.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2206801 4.65% 95.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1128511 2.38% 98.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 892386 1.88% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 16747153 25.81% 25.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 17200007 26.51% 52.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 17188207 26.49% 78.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 11716155 18.06% 96.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 2032622 3.13% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 980 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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+system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 64885124 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 215167 9.06% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1190055 50.09% 59.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 970810 40.86% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 6675057 22.12% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 43 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 11293925 37.43% 59.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 12204027 40.45% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 51976863 52.16% 52.16% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 92995 0.09% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 147 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 25513927 25.60% 77.86% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 22062558 22.14% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 49495845 52.18% 52.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 89880 0.09% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.27% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 24035217 25.34% 77.61% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 21239293 22.39% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 99646497 # Type of FU issued
-system.cpu.iq.rate 2.084967 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2376032 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.023845 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 249252729 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 119771582 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 97191472 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 610 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 940 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 210 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 102022220 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 309 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 2232705 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 94860274 # Type of FU issued
+system.cpu.iq.rate 1.454233 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 30173052 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.318079 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 285470188 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 105595239 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 93464369 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 254 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 125033207 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 119 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1351291 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 2853122 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 4762 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 65666 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2849832 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1454530 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 2099 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 11910 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1431979 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 726205 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 82286 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 120662 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 168795 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 544996 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1714516 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 834399 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 105286702 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 183365 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 25719384 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 23405570 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 22106 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 17305 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 806226 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 65666 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 396732 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 182672 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 579404 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 98631248 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25214590 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1015249 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 492132 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 622391 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 354812 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 98194956 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 24320792 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 21987717 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 18604 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1618 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 350368 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 11910 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 302846 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 221657 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 524503 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 93943274 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 23727789 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 917000 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 10433 # number of nop insts executed
-system.cpu.iew.exec_refs 46968385 # number of memory reference insts executed
-system.cpu.iew.exec_branches 14905400 # Number of branches executed
-system.cpu.iew.exec_stores 21753795 # Number of stores executed
-system.cpu.iew.exec_rate 2.063724 # Inst execution rate
-system.cpu.iew.wb_sent 97441036 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 97191682 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 50912103 # num instructions producing a value
-system.cpu.iew.wb_consumers 98942269 # num instructions consuming a value
+system.cpu.iew.exec_nop 9866 # number of nop insts executed
+system.cpu.iew.exec_refs 44709300 # number of memory reference insts executed
+system.cpu.iew.exec_branches 14252629 # Number of branches executed
+system.cpu.iew.exec_stores 20981511 # Number of stores executed
+system.cpu.iew.exec_rate 1.440176 # Inst execution rate
+system.cpu.iew.wb_sent 93586002 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 93464426 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 44933898 # num instructions producing a value
+system.cpu.iew.wb_consumers 76510027 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.033603 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.514564 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.432835 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.587294 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 14604340 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 6524705 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 491808 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 45293214 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.002246 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.787973 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 478981 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 63829281 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.420792 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.179767 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 20766641 45.85% 45.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 9214809 20.34% 66.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 2670756 5.90% 72.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2400198 5.30% 77.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2023573 4.47% 81.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 972100 2.15% 84.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 768345 1.70% 85.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 447977 0.99% 86.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 6028815 13.31% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 30376493 47.59% 47.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 16710378 26.18% 73.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 4273265 6.69% 80.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 4126779 6.47% 86.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1950134 3.06% 89.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1295842 2.03% 92.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 707155 1.11% 93.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 585665 0.92% 94.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 3803570 5.96% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 45293214 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 63829281 # Number of insts commited each cycle
system.cpu.commit.committedInsts 70913181 # Number of instructions committed
system.cpu.commit.committedOps 90688136 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 90688136 # Class of committed instruction
-system.cpu.commit.bw_lim_events 6028815 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 3803570 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 144531576 # The number of ROB reads
-system.cpu.rob.rob_writes 212728591 # The number of ROB writes
-system.cpu.timesIdled 10876 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 367966 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 157213253 # The number of ROB reads
+system.cpu.rob.rob_writes 195483387 # The number of ROB writes
+system.cpu.timesIdled 20301 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 345307 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 70907629 # Number of Instructions Simulated
system.cpu.committedOps 90682584 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.674016 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.674016 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.483645 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.483645 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 106842718 # number of integer regfile reads
-system.cpu.int_regfile_writes 59180200 # number of integer regfile writes
-system.cpu.fp_regfile_reads 1084 # number of floating regfile reads
-system.cpu.fp_regfile_writes 924 # number of floating regfile writes
-system.cpu.cc_regfile_reads 361896749 # number of cc regfile reads
-system.cpu.cc_regfile_writes 40174850 # number of cc regfile writes
-system.cpu.misc_regfile_reads 45647350 # number of misc regfile reads
+system.cpu.cpi 0.919935 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.919935 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.087033 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.087033 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 102236516 # number of integer regfile reads
+system.cpu.int_regfile_writes 56794814 # number of integer regfile writes
+system.cpu.fp_regfile_reads 36 # number of floating regfile reads
+system.cpu.fp_regfile_writes 21 # number of floating regfile writes
+system.cpu.cc_regfile_reads 346002142 # number of cc regfile reads
+system.cpu.cc_regfile_writes 38804540 # number of cc regfile writes
+system.cpu.misc_regfile_reads 44207937 # number of misc regfile reads
system.cpu.misc_regfile_writes 31840 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 869793867 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 88682 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 88681 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 129104 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 425 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 425 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 106980 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 106980 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66417 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454340 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 520757 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2108672 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18643008 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 20751680 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 20751680 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 33280 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 291703993 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 50946473 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 259533576 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
-system.cpu.icache.tags.replacements 31122 # number of replacements
-system.cpu.icache.tags.tagsinuse 1801.454521 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 12448339 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 33152 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 375.492851 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1801.454521 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.879616 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.879616 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 2030 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 1255 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 672 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.991211 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 25004882 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 25004882 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 12448346 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 12448346 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 12448346 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 12448346 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 12448346 # number of overall hits
-system.cpu.icache.overall_hits::total 12448346 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 37361 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 37361 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 37361 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 37361 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 37361 # number of overall misses
-system.cpu.icache.overall_misses::total 37361 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 833057215 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 833057215 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 833057215 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 833057215 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 833057215 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 833057215 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 12485707 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 12485707 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 12485707 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 12485707 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 12485707 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 12485707 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002992 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.002992 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.002992 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.002992 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.002992 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.002992 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22297.508498 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 22297.508498 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 22297.508498 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 22297.508498 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 22297.508498 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 22297.508498 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 1054 # number of cycles access was blocked
+system.cpu.toL2Bus.trans_dist::ReadReq 661258 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 661257 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 256573 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq 261175 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 148561 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 148561 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 647966 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1228253 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 1876219 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20734528 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47513792 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 68248320 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 261186 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 1327591 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5.196729 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.397525 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 1066416 80.33% 80.33% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 261175 19.67% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 1327591 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 789786488 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 486428945 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 733917689 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
+system.cpu.icache.tags.replacements 323466 # number of replacements
+system.cpu.icache.tags.tagsinuse 510.438944 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 22431935 # Total number of references to valid blocks.
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-system.cpu.dcache.tags.tagsinuse 4066.697393 # Cycle average of tags in use
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-system.cpu.dcache.tags.warmup_cycle 349035000 # Cycle when the warmup percentage was hit.
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+system.cpu.dcache.overall_mshr_hits::total 1118258 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299722 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 299722 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148521 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 148521 # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 448243 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 448243 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 485840 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 485840 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2813681816 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2813681816 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1950344957 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 1950344957 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1901549750 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1901549750 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4764026773 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 4764026773 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6665576523 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6665576523 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013583 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013583 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007482 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007482 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291802 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291802 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010694 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.010694 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011555 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.011555 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9387.638598 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9387.638598 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13131.779055 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 13131.779055 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50577.167061 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50577.167061 # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10628.223470 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 10628.223470 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13719.694803 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13719.694803 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 48960011000 # Number of ticks simulated
final_tick 48960011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1457592 # Simulator instruction rate (inst/s)
-host_op_rate 1864058 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1006352889 # Simulator tick rate (ticks/s)
-host_mem_usage 314048 # Number of bytes of host memory used
-host_seconds 48.65 # Real time elapsed on the host
+host_inst_rate 264072 # Simulator instruction rate (inst/s)
+host_op_rate 337712 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 182321320 # Simulator tick rate (ticks/s)
+host_mem_usage 304496 # Number of bytes of host memory used
+host_seconds 268.54 # Real time elapsed on the host
sim_insts 70913181 # Number of instructions simulated
sim_ops 90688136 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 6384399546 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3783364264 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10167763810 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 10167763810 # Throughput (bytes/s)
-system.membus.data_through_bus 497813828 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 100925135 # Transaction distribution
+system.membus.trans_dist::ReadResp 100941054 # Transaction distribution
+system.membus.trans_dist::WriteReq 19849901 # Transaction distribution
+system.membus.trans_dist::WriteResp 19849901 # Transaction distribution
+system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution
+system.membus.trans_dist::SoftPFResp 123744 # Transaction distribution
+system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution
+system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution
+system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290136 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 241861236 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580272 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 497813828 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 120930618 # Request fanout histogram
+system.membus.snoop_fanout::mean 4.646198 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::4 42785550 35.38% 35.38% # Request fanout histogram
+system.membus.snoop_fanout::5 78145068 64.62% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 4 # Request fanout histogram
+system.membus.snoop_fanout::max_value 5 # Request fanout histogram
+system.membus.snoop_fanout::total 120930618 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
sim_ticks 127293983000 # Number of ticks simulated
final_tick 127293983000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 875914 # Simulator instruction rate (inst/s)
-host_op_rate 1118296 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1584379759 # Simulator tick rate (ticks/s)
-host_mem_usage 323804 # Number of bytes of host memory used
-host_seconds 80.34 # Real time elapsed on the host
+host_inst_rate 949441 # Simulator instruction rate (inst/s)
+host_op_rate 1212170 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1717378261 # Simulator tick rate (ticks/s)
+host_mem_usage 313972 # Number of bytes of host memory used
+host_seconds 74.12 # Real time elapsed on the host
sim_insts 70373628 # Number of instructions simulated
sim_ops 89847362 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 2007071 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 62253375 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 106447639 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 106447639 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 25532 # Transaction distribution
system.membus.trans_dist::ReadResp 25532 # Transaction distribution
system.membus.trans_dist::Writeback 83909 # Transaction distribution
system.membus.trans_dist::ReadExResp 102280 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 339533 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 339533 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 13550144 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 214631 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 214631 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 214631 # Request fanout histogram
system.membus.reqLayer0.occupancy 895030780 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.membus.respLayer1.occupancy 1156019000 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43583.422918 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 43583.422918 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 154424267 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 37816 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 448235 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 486051 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1210112 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18447168 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 19657280 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1210112 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18447168 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 307145 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 307145 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 307145 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks)
sim_ticks 68148672000 # Number of ticks simulated
final_tick 68148672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2339703 # Simulator instruction rate (inst/s)
-host_op_rate 2369997 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1186374997 # Simulator tick rate (ticks/s)
-host_mem_usage 273296 # Number of bytes of host memory used
-host_seconds 57.44 # Real time elapsed on the host
+host_inst_rate 2078407 # Simulator instruction rate (inst/s)
+host_op_rate 2105318 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1053881878 # Simulator tick rate (ticks/s)
+host_mem_usage 288492 # Number of bytes of host memory used
+host_seconds 64.66 # Real time elapsed on the host
sim_insts 134398962 # Number of instructions simulated
sim_ops 136139190 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7897648835 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3484181027 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11381829862 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 11383698247 # Throughput (bytes/s)
-system.membus.data_through_bus 775783918 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 171784870 # Transaction distribution
+system.membus.trans_dist::ReadResp 171784870 # Transaction distribution
+system.membus.trans_dist::WriteReq 20864304 # Transaction distribution
+system.membus.trans_dist::WriteResp 20864304 # Transaction distribution
+system.membus.trans_dist::SwapReq 15916 # Transaction distribution
+system.membus.trans_dist::SwapResp 15916 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107140 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 116223040 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 385330180 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214280 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 775783918 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 192665090 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.698381 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.458961 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 58111520 30.16% 30.16% # Request fanout histogram
+system.membus.snoop_fanout::1 134553570 69.84% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 192665090 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 136297345 # number of cpu cycles simulated
sim_ticks 202242260000 # Number of ticks simulated
final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1069571 # Simulator instruction rate (inst/s)
-host_op_rate 1083420 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1609480248 # Simulator tick rate (ticks/s)
-host_mem_usage 282012 # Number of bytes of host memory used
-host_seconds 125.66 # Real time elapsed on the host
+host_inst_rate 1318449 # Simulator instruction rate (inst/s)
+host_op_rate 1335520 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1983988186 # Simulator tick rate (ticks/s)
+host_mem_usage 297988 # Number of bytes of host memory used
+host_seconds 101.94 # Real time elapsed on the host
sim_insts 134398962 # Number of instructions simulated
sim_ops 136139190 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 2924651 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 38699251 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 67847660 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 67847660 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 30277 # Transaction distribution
system.membus.trans_dist::ReadResp 30277 # Transaction distribution
system.membus.trans_dist::Writeback 82868 # Transaction distribution
system.membus.trans_dist::ReadExResp 101256 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 345934 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 345934 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 13721664 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 214401 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 214401 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 214401 # Request fanout histogram
system.membus.reqLayer0.occupancy 877345000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 1183797000 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 146097102 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 232523 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 123970 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374048 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 425326 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 799374 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11969536 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17577472 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 29547008 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 29547008 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11969536 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17577472 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 29547008 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 461672 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 461672 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 461672 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 354806000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks)
---------- Begin Simulation Statistics ----------
-sim_seconds 1.181972 # Number of seconds simulated
-sim_ticks 1181971516500 # Number of ticks simulated
-final_tick 1181971516500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.182263 # Number of seconds simulated
+sim_ticks 1182263011500 # Number of ticks simulated
+final_tick 1182263011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 316302 # Simulator instruction rate (inst/s)
-host_op_rate 316302 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 204699977 # Simulator tick rate (ticks/s)
-host_mem_usage 267460 # Number of bytes of host memory used
-host_seconds 5774.17 # Real time elapsed on the host
+host_inst_rate 338169 # Simulator instruction rate (inst/s)
+host_op_rate 338169 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 218905814 # Simulator tick rate (ticks/s)
+host_mem_usage 291920 # Number of bytes of host memory used
+host_seconds 5400.78 # Real time elapsed on the host
sim_insts 1826378509 # Number of instructions simulated
sim_ops 1826378509 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 125504768 # Number of bytes read from this memory
-system.physmem.bytes_read::total 125504768 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 65167040 # Number of bytes written to this memory
-system.physmem.bytes_written::total 65167040 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1961012 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1961012 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1018235 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1018235 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 106182566 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 106182566 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 51873 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 51873 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 55134188 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 55134188 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 55134188 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 106182566 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 161316754 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1961012 # Number of read requests accepted
-system.physmem.writeReqs 1018235 # Number of write requests accepted
-system.physmem.readBursts 1961012 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1018235 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 125424512 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 80256 # Total number of bytes read from write queue
-system.physmem.bytesWritten 65165696 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 125504768 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 65167040 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 1254 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst 125507520 # Number of bytes read from this memory
+system.physmem.bytes_read::total 125507520 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 61184 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 61184 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 65168128 # Number of bytes written to this memory
+system.physmem.bytes_written::total 65168128 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 1961055 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1961055 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1018252 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1018252 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 106158713 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 106158713 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 51752 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 51752 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 55121515 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 55121515 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 55121515 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 106158713 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 161280228 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1961055 # Number of read requests accepted
+system.physmem.writeReqs 1018252 # Number of write requests accepted
+system.physmem.readBursts 1961055 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1018252 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 125426368 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 81152 # Total number of bytes read from write queue
+system.physmem.bytesWritten 65166528 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 125507520 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 65168128 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 1268 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 118750 # Per bank write bursts
-system.physmem.perBankRdBursts::1 114103 # Per bank write bursts
-system.physmem.perBankRdBursts::2 116233 # Per bank write bursts
-system.physmem.perBankRdBursts::3 117780 # Per bank write bursts
-system.physmem.perBankRdBursts::4 117833 # Per bank write bursts
-system.physmem.perBankRdBursts::5 117521 # Per bank write bursts
-system.physmem.perBankRdBursts::6 119886 # Per bank write bursts
-system.physmem.perBankRdBursts::7 124520 # Per bank write bursts
-system.physmem.perBankRdBursts::8 126974 # Per bank write bursts
-system.physmem.perBankRdBursts::9 130087 # Per bank write bursts
-system.physmem.perBankRdBursts::10 128649 # Per bank write bursts
-system.physmem.perBankRdBursts::11 130350 # Per bank write bursts
-system.physmem.perBankRdBursts::12 126060 # Per bank write bursts
-system.physmem.perBankRdBursts::13 125237 # Per bank write bursts
-system.physmem.perBankRdBursts::14 122580 # Per bank write bursts
-system.physmem.perBankRdBursts::15 123195 # Per bank write bursts
-system.physmem.perBankWrBursts::0 61223 # Per bank write bursts
+system.physmem.perBankRdBursts::0 118756 # Per bank write bursts
+system.physmem.perBankRdBursts::1 114094 # Per bank write bursts
+system.physmem.perBankRdBursts::2 116231 # Per bank write bursts
+system.physmem.perBankRdBursts::3 117777 # Per bank write bursts
+system.physmem.perBankRdBursts::4 117824 # Per bank write bursts
+system.physmem.perBankRdBursts::5 117524 # Per bank write bursts
+system.physmem.perBankRdBursts::6 119883 # Per bank write bursts
+system.physmem.perBankRdBursts::7 124524 # Per bank write bursts
+system.physmem.perBankRdBursts::8 126980 # Per bank write bursts
+system.physmem.perBankRdBursts::9 130091 # Per bank write bursts
+system.physmem.perBankRdBursts::10 128645 # Per bank write bursts
+system.physmem.perBankRdBursts::11 130349 # Per bank write bursts
+system.physmem.perBankRdBursts::12 126066 # Per bank write bursts
+system.physmem.perBankRdBursts::13 125260 # Per bank write bursts
+system.physmem.perBankRdBursts::14 122596 # Per bank write bursts
+system.physmem.perBankRdBursts::15 123187 # Per bank write bursts
+system.physmem.perBankWrBursts::0 61220 # Per bank write bursts
system.physmem.perBankWrBursts::1 61486 # Per bank write bursts
-system.physmem.perBankWrBursts::2 60566 # Per bank write bursts
-system.physmem.perBankWrBursts::3 61239 # Per bank write bursts
-system.physmem.perBankWrBursts::4 61662 # Per bank write bursts
-system.physmem.perBankWrBursts::5 63100 # Per bank write bursts
-system.physmem.perBankWrBursts::6 64151 # Per bank write bursts
-system.physmem.perBankWrBursts::7 65612 # Per bank write bursts
-system.physmem.perBankWrBursts::8 65333 # Per bank write bursts
-system.physmem.perBankWrBursts::9 65776 # Per bank write bursts
-system.physmem.perBankWrBursts::10 65296 # Per bank write bursts
-system.physmem.perBankWrBursts::11 65642 # Per bank write bursts
-system.physmem.perBankWrBursts::12 64167 # Per bank write bursts
-system.physmem.perBankWrBursts::13 64207 # Per bank write bursts
-system.physmem.perBankWrBursts::14 64568 # Per bank write bursts
-system.physmem.perBankWrBursts::15 64186 # Per bank write bursts
+system.physmem.perBankWrBursts::2 60567 # Per bank write bursts
+system.physmem.perBankWrBursts::3 61241 # Per bank write bursts
+system.physmem.perBankWrBursts::4 61658 # Per bank write bursts
+system.physmem.perBankWrBursts::5 63102 # Per bank write bursts
+system.physmem.perBankWrBursts::6 64150 # Per bank write bursts
+system.physmem.perBankWrBursts::7 65615 # Per bank write bursts
+system.physmem.perBankWrBursts::8 65332 # Per bank write bursts
+system.physmem.perBankWrBursts::9 65779 # Per bank write bursts
+system.physmem.perBankWrBursts::10 65299 # Per bank write bursts
+system.physmem.perBankWrBursts::11 65643 # Per bank write bursts
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+system.physmem.perBankWrBursts::13 64211 # Per bank write bursts
+system.physmem.perBankWrBursts::14 64571 # Per bank write bursts
+system.physmem.perBankWrBursts::15 64187 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 1181971406500 # Total gap between requests
+system.physmem.totGap 1182262901500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 1961012 # Read request sizes (log2)
+system.physmem.readPktSize::6 1961055 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1018235 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1833489 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 126251 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1018252 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 1833329 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 126440 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 31694 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 33227 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 55449 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 59149 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 59888 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 59833 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 59765 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 59757 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 59786 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 59783 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 59794 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::27 60768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 60180 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 59898 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 60650 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 59424 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 59239 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 86 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 29905 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::27 60608 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::29 60198 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 61396 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::33 67 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1832879 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 103.982912 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 81.202772 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 130.375131 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 1452262 79.23% 79.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 263657 14.38% 93.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 49315 2.69% 96.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 20815 1.14% 97.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 12975 0.71% 98.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 7226 0.39% 98.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 5262 0.29% 98.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 4170 0.23% 99.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 17197 0.94% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1832879 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 59235 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 33.083110 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 163.258366 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 59198 99.94% 99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 10 0.02% 99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.97% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 1836557 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 103.775367 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 81.104101 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 130.072591 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 1457072 79.34% 79.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 262826 14.31% 93.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 49283 2.68% 96.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 20722 1.13% 97.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 12908 0.70% 98.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 7083 0.39% 98.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 5369 0.29% 98.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 4081 0.22% 99.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 17213 0.94% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1836557 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 59478 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 32.947897 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 162.231607 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 59437 99.93% 99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047 16 0.03% 99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071 8 0.01% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 59235 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 59235 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.189398 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.153834 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.107502 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 25894 43.71% 43.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 1328 2.24% 45.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 27547 46.50% 92.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 3948 6.66% 99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 431 0.73% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 64 0.11% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 18 0.03% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 4 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 59235 # Writes before turning the bus around for reads
-system.physmem.totQLat 36544529000 # Total ticks spent queuing
-system.physmem.totMemAccLat 73289991500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 9798790000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 18647.47 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 59478 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 59478 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.119389 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.083537 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.112675 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 28008 47.09% 47.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 1262 2.12% 49.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 25918 43.58% 92.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 3789 6.37% 99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 422 0.71% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 60 0.10% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 14 0.02% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 3 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 59478 # Writes before turning the bus around for reads
+system.physmem.totQLat 36992521000 # Total ticks spent queuing
+system.physmem.totMemAccLat 73738527250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 9798935000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 18875.79 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 37397.47 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 106.11 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 55.13 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 106.18 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 55.13 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 37625.79 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 106.09 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 55.12 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 106.16 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 55.12 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 1.26 # Data bus utilization in percentage
system.physmem.busUtilRead 0.83 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.43 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.78 # Average write queue length when enqueuing
-system.physmem.readRowHits 729927 # Number of row buffer hits during reads
-system.physmem.writeRowHits 415160 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 37.25 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 40.77 # Row buffer hit rate for writes
-system.physmem.avgGap 396734.95 # Average gap between requests
-system.physmem.pageHitRate 38.45 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 385912942500 # Time in different power states
-system.physmem.memoryStateTime::REF 39468520000 # Time in different power states
+system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing
+system.physmem.readRowHits 727653 # Number of row buffer hits during reads
+system.physmem.writeRowHits 413795 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 37.13 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 40.64 # Row buffer hit rate for writes
+system.physmem.avgGap 396824.80 # Average gap between requests
+system.physmem.pageHitRate 38.33 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 385836572500 # Time in different power states
+system.physmem.memoryStateTime::REF 39478140000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 756587133750 # Time in different power states
+system.physmem.memoryStateTime::ACT 756941975000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 161316754 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 1181581 # Transaction distribution
-system.membus.trans_dist::ReadResp 1181581 # Transaction distribution
-system.membus.trans_dist::Writeback 1018235 # Transaction distribution
-system.membus.trans_dist::ReadExReq 779431 # Transaction distribution
-system.membus.trans_dist::ReadExResp 779431 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940259 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 4940259 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190671808 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 190671808 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 190671808 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 11933364500 # Layer occupancy (ticks)
+system.membus.trans_dist::ReadReq 1181608 # Transaction distribution
+system.membus.trans_dist::ReadResp 1181608 # Transaction distribution
+system.membus.trans_dist::Writeback 1018252 # Transaction distribution
+system.membus.trans_dist::ReadExReq 779447 # Transaction distribution
+system.membus.trans_dist::ReadExResp 779447 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940362 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 4940362 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190675648 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 190675648 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 2979307 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 2979307 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 2979307 # Request fanout histogram
+system.membus.reqLayer0.occupancy 11933178500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 18494109500 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 18493465250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.6 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 244428250 # Number of BP lookups
-system.cpu.branchPred.condPredicted 184893435 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 15662948 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 166307436 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 163975175 # Number of BTB hits
+system.cpu.branchPred.lookups 244422779 # Number of BP lookups
+system.cpu.branchPred.condPredicted 184893031 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 15656805 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 166159806 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 163963467 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 98.597621 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 18313183 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 99860 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 98.678177 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 18313255 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 100190 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 452570396 # DTB read hits
-system.cpu.dtb.read_misses 4982513 # DTB read misses
+system.cpu.dtb.read_hits 452570621 # DTB read hits
+system.cpu.dtb.read_misses 4982980 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 457552909 # DTB read accesses
-system.cpu.dtb.write_hits 161353452 # DTB write hits
-system.cpu.dtb.write_misses 1708793 # DTB write misses
+system.cpu.dtb.read_accesses 457553601 # DTB read accesses
+system.cpu.dtb.write_hits 161352620 # DTB write hits
+system.cpu.dtb.write_misses 1708824 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 163062245 # DTB write accesses
-system.cpu.dtb.data_hits 613923848 # DTB hits
-system.cpu.dtb.data_misses 6691306 # DTB misses
+system.cpu.dtb.write_accesses 163061444 # DTB write accesses
+system.cpu.dtb.data_hits 613923241 # DTB hits
+system.cpu.dtb.data_misses 6691804 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 620615154 # DTB accesses
-system.cpu.itb.fetch_hits 591487986 # ITB hits
+system.cpu.dtb.data_accesses 620615045 # DTB accesses
+system.cpu.itb.fetch_hits 591467838 # ITB hits
system.cpu.itb.fetch_misses 19 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 591488005 # ITB accesses
+system.cpu.itb.fetch_accesses 591467857 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
-system.cpu.numCycles 2363943033 # number of cpu cycles simulated
+system.cpu.numCycles 2364526023 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1826378509 # Number of instructions committed
system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 49642925 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 49659953 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.294334 # CPI: cycles per instruction
-system.cpu.ipc 0.772598 # IPC: instructions per cycle
-system.cpu.tickCycles 2043545366 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 320397667 # Total number of cycles that the object has spent stopped
+system.cpu.cpi 1.294653 # CPI: cycles per instruction
+system.cpu.ipc 0.772408 # IPC: instructions per cycle
+system.cpu.tickCycles 2043503290 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 321022733 # Total number of cycles that the object has spent stopped
system.cpu.icache.tags.replacements 3 # number of replacements
-system.cpu.icache.tags.tagsinuse 750.580892 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 591487028 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 958 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 617418.609603 # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 749.760915 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 591466882 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 956 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 618689.207113 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 750.580892 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.366495 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.366495 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 955 # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst 749.760915 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.366094 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.366094 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 953 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 1182976930 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 1182976930 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 591487028 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 591487028 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 591487028 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 591487028 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 591487028 # number of overall hits
-system.cpu.icache.overall_hits::total 591487028 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 958 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 958 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 958 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 958 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 958 # number of overall misses
-system.cpu.icache.overall_misses::total 958 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 69768750 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 69768750 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 69768750 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 69768750 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 69768750 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 69768750 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 591487986 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 591487986 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 591487986 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 591487986 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 591487986 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 591487986 # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::4 872 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.465332 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 1182936632 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 1182936632 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 591466882 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 591466882 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 591466882 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 591466882 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 591466882 # number of overall hits
+system.cpu.icache.overall_hits::total 591466882 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 956 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 956 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 956 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 956 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 956 # number of overall misses
+system.cpu.icache.overall_misses::total 956 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 70103250 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 70103250 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 70103250 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 70103250 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 70103250 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 70103250 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 591467838 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 591467838 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72827.505219 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 72827.505219 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 72827.505219 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 72827.505219 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 72827.505219 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 72827.505219 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73329.759414 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 73329.759414 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 73329.759414 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 73329.759414 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 73329.759414 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 73329.759414 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 958 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 958 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 958 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 958 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67467250 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 67467250 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67467250 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 67467250 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67467250 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 67467250 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 956 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 956 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 956 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 956 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 956 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 956 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67802750 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 67802750 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67802750 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 67802750 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67802750 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 67802750 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.016133 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016133 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.661836 # Number of seconds simulated
-sim_ticks 661835607000 # Number of ticks simulated
-final_tick 661835607000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.662267 # Number of seconds simulated
+sim_ticks 662266942000 # Number of ticks simulated
+final_tick 662266942000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 129941 # Simulator instruction rate (inst/s)
-host_op_rate 129941 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 49537566 # Simulator tick rate (ticks/s)
-host_mem_usage 237180 # Number of bytes of host memory used
-host_seconds 13360.28 # Real time elapsed on the host
+host_inst_rate 180229 # Simulator instruction rate (inst/s)
+host_op_rate 180229 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 68753783 # Simulator tick rate (ticks/s)
+host_mem_usage 293196 # Number of bytes of host memory used
+host_seconds 9632.44 # Real time elapsed on the host
sim_insts 1736043781 # Number of instructions simulated
sim_ops 1736043781 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 61952 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 125980800 # Number of bytes read from this memory
-system.physmem.bytes_read::total 126042752 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 61952 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 61952 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 65306880 # Number of bytes written to this memory
-system.physmem.bytes_written::total 65306880 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 968 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1968450 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1969418 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1020420 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1020420 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 93606 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 190350593 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 190444199 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 93606 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 93606 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 98675380 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 98675380 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 98675380 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 93606 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 190350593 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 289119579 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1969418 # Number of read requests accepted
-system.physmem.writeReqs 1020420 # Number of write requests accepted
-system.physmem.readBursts 1969418 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1020420 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 125960256 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 82496 # Total number of bytes read from write queue
-system.physmem.bytesWritten 65304896 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 126042752 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 65306880 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 1289 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst 62272 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 125973696 # Number of bytes read from this memory
+system.physmem.bytes_read::total 126035968 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 62272 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 62272 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 65304064 # Number of bytes written to this memory
+system.physmem.bytes_written::total 65304064 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 973 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1968339 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1969312 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1020376 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1020376 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 94029 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 190215890 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 190309919 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 94029 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 94029 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 98606861 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 98606861 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 98606861 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 94029 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 190215890 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 288916779 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1969312 # Number of read requests accepted
+system.physmem.writeReqs 1020376 # Number of write requests accepted
+system.physmem.readBursts 1969312 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1020376 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 125955072 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 80896 # Total number of bytes read from write queue
+system.physmem.bytesWritten 65302080 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 126035968 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 65304064 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 1264 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 119133 # Per bank write bursts
-system.physmem.perBankRdBursts::1 114512 # Per bank write bursts
-system.physmem.perBankRdBursts::2 116620 # Per bank write bursts
-system.physmem.perBankRdBursts::3 118156 # Per bank write bursts
-system.physmem.perBankRdBursts::4 118267 # Per bank write bursts
-system.physmem.perBankRdBursts::5 117901 # Per bank write bursts
-system.physmem.perBankRdBursts::6 120342 # Per bank write bursts
-system.physmem.perBankRdBursts::7 125056 # Per bank write bursts
-system.physmem.perBankRdBursts::8 127675 # Per bank write bursts
-system.physmem.perBankRdBursts::9 130585 # Per bank write bursts
-system.physmem.perBankRdBursts::10 129305 # Per bank write bursts
-system.physmem.perBankRdBursts::11 130922 # Per bank write bursts
-system.physmem.perBankRdBursts::12 126863 # Per bank write bursts
-system.physmem.perBankRdBursts::13 125867 # Per bank write bursts
-system.physmem.perBankRdBursts::14 123079 # Per bank write bursts
-system.physmem.perBankRdBursts::15 123846 # Per bank write bursts
-system.physmem.perBankWrBursts::0 61299 # Per bank write bursts
-system.physmem.perBankWrBursts::1 61588 # Per bank write bursts
-system.physmem.perBankWrBursts::2 60677 # Per bank write bursts
-system.physmem.perBankWrBursts::3 61353 # Per bank write bursts
-system.physmem.perBankWrBursts::4 61807 # Per bank write bursts
-system.physmem.perBankWrBursts::5 63207 # Per bank write bursts
-system.physmem.perBankWrBursts::6 64256 # Per bank write bursts
-system.physmem.perBankWrBursts::7 65745 # Per bank write bursts
-system.physmem.perBankWrBursts::8 65527 # Per bank write bursts
-system.physmem.perBankWrBursts::9 65905 # Per bank write bursts
-system.physmem.perBankWrBursts::10 65467 # Per bank write bursts
-system.physmem.perBankWrBursts::11 65774 # Per bank write bursts
-system.physmem.perBankWrBursts::12 64405 # Per bank write bursts
-system.physmem.perBankWrBursts::13 64356 # Per bank write bursts
-system.physmem.perBankWrBursts::14 64678 # Per bank write bursts
-system.physmem.perBankWrBursts::15 64345 # Per bank write bursts
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+system.physmem.perBankRdBursts::11 130962 # Per bank write bursts
+system.physmem.perBankRdBursts::12 126769 # Per bank write bursts
+system.physmem.perBankRdBursts::13 125905 # Per bank write bursts
+system.physmem.perBankRdBursts::14 123070 # Per bank write bursts
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+system.physmem.perBankWrBursts::0 61320 # Per bank write bursts
+system.physmem.perBankWrBursts::1 61597 # Per bank write bursts
+system.physmem.perBankWrBursts::2 60678 # Per bank write bursts
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+system.physmem.perBankWrBursts::8 65524 # Per bank write bursts
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+system.physmem.perBankWrBursts::14 64665 # Per bank write bursts
+system.physmem.perBankWrBursts::15 64331 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 661835517500 # Total gap between requests
+system.physmem.totGap 662266852500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 1969418 # Read request sizes (log2)
+system.physmem.readPktSize::6 1969312 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1020420 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1619695 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 248396 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1020376 # Write request sizes (log2)
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1772142 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 107.926701 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 82.988600 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 137.225720 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 1375537 77.62% 77.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 272696 15.39% 93.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 53852 3.04% 96.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 21473 1.21% 97.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 12850 0.73% 97.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 6581 0.37% 98.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 4855 0.27% 98.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 3761 0.21% 98.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 20537 1.16% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1772142 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 59644 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 32.954195 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 163.722438 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 59607 99.94% 99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 13 0.02% 99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071 6 0.01% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095 8 0.01% 99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 1775882 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 107.694867 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 82.878503 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 136.793796 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 1380775 77.75% 77.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 271356 15.28% 93.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 53913 3.04% 96.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 21326 1.20% 97.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 12854 0.72% 97.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 6480 0.36% 98.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 5132 0.29% 98.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 3787 0.21% 98.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 20259 1.14% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1775882 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 59943 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 32.788466 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 161.189780 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 59903 99.93% 99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047 15 0.03% 99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071 9 0.02% 99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 59644 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 59644 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.107991 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.066184 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.220335 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 29768 49.91% 49.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 1416 2.37% 52.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 22411 37.57% 89.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 4939 8.28% 98.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 872 1.46% 99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 162 0.27% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 31 0.05% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 10 0.02% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 7 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 1 0.00% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 3 0.01% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28 1 0.00% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29 1 0.00% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30 2 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31 10 0.02% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32 4 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33 2 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34 3 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 59644 # Writes before turning the bus around for reads
-system.physmem.totQLat 40394853000 # Total ticks spent queuing
-system.physmem.totMemAccLat 77297271750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 9840645000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 20524.49 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 59943 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 59943 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.021921 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.980571 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.225631 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17 33661 56.16% 56.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19 25267 42.15% 98.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21 929 1.55% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23 52 0.09% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25 8 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27 5 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29 4 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31 3 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33 6 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34-35 6 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-37 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-69 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 59943 # Writes before turning the bus around for reads
+system.physmem.totQLat 41251747750 # Total ticks spent queuing
+system.physmem.totMemAccLat 78152647750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 9840240000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 20960.74 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 39274.49 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 190.32 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 98.67 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 190.44 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 98.68 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 39710.74 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 190.19 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 98.60 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 190.31 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 98.61 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 2.26 # Data bus utilization in percentage
system.physmem.busUtilRead 1.49 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.77 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.96 # Average write queue length when enqueuing
-system.physmem.readRowHits 798370 # Number of row buffer hits during reads
-system.physmem.writeRowHits 417997 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 40.56 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 40.96 # Row buffer hit rate for writes
-system.physmem.avgGap 221361.66 # Average gap between requests
-system.physmem.pageHitRate 40.70 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 126237669000 # Time in different power states
-system.physmem.memoryStateTime::REF 22100000000 # Time in different power states
+system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing
+system.physmem.readRowHits 795732 # Number of row buffer hits during reads
+system.physmem.writeRowHits 416769 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 40.43 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 40.84 # Row buffer hit rate for writes
+system.physmem.avgGap 221517.05 # Average gap between requests
+system.physmem.pageHitRate 40.57 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 126335534000 # Time in different power states
+system.physmem.memoryStateTime::REF 22114300000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 513493900500 # Time in different power states
+system.physmem.memoryStateTime::ACT 513810229000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 289119579 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 1198182 # Transaction distribution
-system.membus.trans_dist::ReadResp 1198182 # Transaction distribution
-system.membus.trans_dist::Writeback 1020420 # Transaction distribution
-system.membus.trans_dist::ReadExReq 771236 # Transaction distribution
-system.membus.trans_dist::ReadExResp 771236 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4959256 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 4959256 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191349632 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 191349632 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 191349632 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 11823202500 # Layer occupancy (ticks)
+system.membus.trans_dist::ReadReq 1197969 # Transaction distribution
+system.membus.trans_dist::ReadResp 1197969 # Transaction distribution
+system.membus.trans_dist::Writeback 1020376 # Transaction distribution
+system.membus.trans_dist::ReadExReq 771343 # Transaction distribution
+system.membus.trans_dist::ReadExResp 771343 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4959000 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 4959000 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191340032 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 191340032 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 2989688 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 2989688 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 2989688 # Request fanout histogram
+system.membus.reqLayer0.occupancy 11823557000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.8 # Layer utilization (%)
-system.membus.respLayer1.occupancy 18425039000 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 18423875500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 2.8 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 410520712 # Number of BP lookups
-system.cpu.branchPred.condPredicted 318849760 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 16265290 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 282927738 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 279343276 # Number of BTB hits
+system.cpu.branchPred.lookups 410506798 # Number of BP lookups
+system.cpu.branchPred.condPredicted 318826270 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 16270103 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 283363020 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 279346814 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 98.733082 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 26370791 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 98.582664 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 26372853 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 646139057 # DTB read hits
-system.cpu.dtb.read_misses 12159875 # DTB read misses
+system.cpu.dtb.read_hits 646169518 # DTB read hits
+system.cpu.dtb.read_misses 12159492 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 658298932 # DTB read accesses
-system.cpu.dtb.write_hits 218185834 # DTB write hits
-system.cpu.dtb.write_misses 7515423 # DTB write misses
+system.cpu.dtb.read_accesses 658329010 # DTB read accesses
+system.cpu.dtb.write_hits 218199205 # DTB write hits
+system.cpu.dtb.write_misses 7515385 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 225701257 # DTB write accesses
-system.cpu.dtb.data_hits 864324891 # DTB hits
-system.cpu.dtb.data_misses 19675298 # DTB misses
+system.cpu.dtb.write_accesses 225714590 # DTB write accesses
+system.cpu.dtb.data_hits 864368723 # DTB hits
+system.cpu.dtb.data_misses 19674877 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 884000189 # DTB accesses
-system.cpu.itb.fetch_hits 422443679 # ITB hits
-system.cpu.itb.fetch_misses 44 # ITB misses
+system.cpu.dtb.data_accesses 884043600 # DTB accesses
+system.cpu.itb.fetch_hits 422435766 # ITB hits
+system.cpu.itb.fetch_misses 46 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 422443723 # ITB accesses
+system.cpu.itb.fetch_accesses 422435812 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
-system.cpu.numCycles 1323671215 # number of cpu cycles simulated
+system.cpu.numCycles 1324533885 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 433730630 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 3419498139 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 410520712 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 305714067 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 866879802 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 45990094 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 88 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1786 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 422443679 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 8426079 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1323607404 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.583469 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.158025 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 433728129 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 3419447982 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 410506798 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 305719667 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 867740174 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 45999556 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 89 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1859 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 122 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 422435766 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 8419815 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1324470151 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.581748 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.157662 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 696600974 52.63% 52.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 48023746 3.63% 56.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 24394821 1.84% 58.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 45250405 3.42% 61.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 142990505 10.80% 72.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 66206181 5.00% 77.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 43787822 3.31% 80.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 29609921 2.24% 82.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 226743029 17.13% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 697483370 52.66% 52.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 48005474 3.62% 56.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 24395138 1.84% 58.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 45249876 3.42% 61.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 142980828 10.80% 72.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 66219617 5.00% 77.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 43796288 3.31% 80.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 29613001 2.24% 82.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 226726559 17.12% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1323607404 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.310138 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.583344 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 355560821 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 384357689 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 525784970 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 34909729 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 22994195 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 62281773 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 917 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3264096854 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2212 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 22994195 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 373922324 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 204910686 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 7734 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 538718918 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 183053547 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 3181111000 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 1787853 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 18972686 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 140245391 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 27858899 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 2377395421 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 4126748897 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 4126578364 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 170532 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1324470151 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.309925 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.581624 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 355594570 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 385179518 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 525809516 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 34887563 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 22998984 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 62292881 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 862 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3264034617 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 2122 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 22998984 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 373946851 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 205483814 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 7143 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 538725666 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 183307693 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 3181027912 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 1764061 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 19006533 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 140449897 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 27939508 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 2377346604 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 4126580900 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 4126409923 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 170976 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 1001192458 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 212 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 209 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 99259627 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 719210617 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 272896274 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 90779805 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 59022559 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2889836484 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 194 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2624050349 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1575226 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 1139401909 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 505657216 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 165 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1323607404 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.982499 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.151238 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 1001143641 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 182 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 180 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 99171579 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 719206222 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 272877842 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 90853191 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 58764648 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2889718435 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 163 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2624030011 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1568714 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 1139278450 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 505521247 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 134 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1324470151 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.981192 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.151140 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 519394281 39.24% 39.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 169344121 12.79% 52.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 158328435 11.96% 64.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 149155945 11.27% 75.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 126186051 9.53% 84.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 84451720 6.38% 91.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 68205907 5.15% 96.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 33984275 2.57% 98.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 14556669 1.10% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 520285766 39.28% 39.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 169352294 12.79% 52.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 158263377 11.95% 64.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 149147598 11.26% 75.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 126214674 9.53% 84.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 84460771 6.38% 91.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 68224303 5.15% 96.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 33971144 2.56% 98.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 14550224 1.10% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1323607404 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1324470151 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 13175247 35.70% 35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 13169928 35.70% 35.70% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 35.70% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 35.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 19116655 51.79% 87.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 4618094 12.51% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 19111172 51.81% 87.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 4608428 12.49% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1719340504 65.52% 65.52% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 109 0.00% 65.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1719281995 65.52% 65.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 111 0.00% 65.52% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 896937 0.03% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 19 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 170 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 34 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 672950109 25.65% 91.20% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 230862442 8.80% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 896550 0.03% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 18 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 159 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 28 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 672977290 25.65% 91.20% # Type of FU issued
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2624050349 # Type of FU issued
-system.cpu.iq.rate 1.982403 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 36909996 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.014066 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 6608212970 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 4028086926 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 2521962769 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 1980354 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1298007 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 893087 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2659977012 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 983333 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 69535121 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2624030011 # Type of FU issued
+system.cpu.iq.rate 1.981097 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 36889528 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.014058 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 6609007948 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 4027844088 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 2521909296 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 1980467 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1299263 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 893137 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2659936163 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 983376 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 69546745 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 274614954 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 379465 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 148696 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 112167772 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 274610559 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 379781 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 148802 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 112149340 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 269 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 6022963 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 343 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 6024507 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 22994195 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 147722049 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 18412868 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 3041056525 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 6683505 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 719210617 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 272896274 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 194 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 821771 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 17859213 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 148696 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 10896298 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 8844115 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 19740413 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2578377980 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 658298938 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 45672369 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 22998984 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 147954834 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 18526434 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 3040938881 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 6690511 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 719206222 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 272877842 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 163 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 822212 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 17973283 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 148802 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 10902941 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 8845995 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 19748936 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2578346915 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 658329015 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 45683096 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 151219847 # number of nop insts executed
-system.cpu.iew.exec_refs 884000267 # number of memory reference insts executed
-system.cpu.iew.exec_branches 315975248 # Number of branches executed
-system.cpu.iew.exec_stores 225701329 # Number of stores executed
-system.cpu.iew.exec_rate 1.947899 # Inst execution rate
-system.cpu.iew.wb_sent 2552852780 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2522855856 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1489309006 # num instructions producing a value
-system.cpu.iew.wb_consumers 1920624303 # num instructions consuming a value
+system.cpu.iew.exec_nop 151220283 # number of nop insts executed
+system.cpu.iew.exec_refs 884043668 # number of memory reference insts executed
+system.cpu.iew.exec_branches 315967801 # Number of branches executed
+system.cpu.iew.exec_stores 225714653 # Number of stores executed
+system.cpu.iew.exec_rate 1.946607 # Inst execution rate
+system.cpu.iew.wb_sent 2552803336 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2522802433 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1489230488 # num instructions producing a value
+system.cpu.iew.wb_consumers 1920481156 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.905954 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.775430 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.904672 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.775447 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 1005196168 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 1005079964 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 16264438 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1184721059 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.536041 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.558766 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 16269309 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1185591559 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.534913 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.558094 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 695617998 58.72% 58.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 159800446 13.49% 72.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 79745623 6.73% 78.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 52150996 4.40% 83.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 28466079 2.40% 85.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 19402088 1.64% 87.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 20010452 1.69% 89.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 23121038 1.95% 91.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 106406339 8.98% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 696399330 58.74% 58.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 159901902 13.49% 72.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 79790439 6.73% 78.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 52118707 4.40% 83.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 28427889 2.40% 85.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 19400301 1.64% 87.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 20045609 1.69% 89.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 23104546 1.95% 91.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 106402836 8.97% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1184721059 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1185591559 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1819780126 # Number of instructions committed
system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction
-system.cpu.commit.bw_lim_events 106406339 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 106402836 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3817511814 # The number of ROB reads
-system.cpu.rob.rob_writes 5788973646 # The number of ROB writes
-system.cpu.timesIdled 715 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 63811 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3818269613 # The number of ROB reads
+system.cpu.rob.rob_writes 5788733936 # The number of ROB writes
+system.cpu.timesIdled 729 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 63734 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.762464 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.762464 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.311537 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.311537 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3467668910 # number of integer regfile reads
-system.cpu.int_regfile_writes 2022324472 # number of integer regfile writes
-system.cpu.fp_regfile_reads 45289 # number of floating regfile reads
-system.cpu.fp_regfile_writes 607 # number of floating regfile writes
+system.cpu.cpi 0.762961 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.762961 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.310683 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.310683 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3467602221 # number of integer regfile reads
+system.cpu.int_regfile_writes 2022271322 # number of integer regfile writes
+system.cpu.fp_regfile_reads 45596 # number of floating regfile reads
+system.cpu.fp_regfile_writes 565 # number of floating regfile writes
system.cpu.misc_regfile_reads 25 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 1252958492 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 7335196 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 7335196 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 3742782 # Transaction distribution
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-system.cpu.dcache.WriteReq_hits::total 155514155 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 5 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 5 # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data 713868948 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 713868948 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 713868948 # number of overall hits
-system.cpu.dcache.overall_hits::total 713868948 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 12746431 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 12746431 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 5214347 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 5214347 # number of WriteReq misses
+system.cpu.dcache.tags.tag_accesses 1472907715 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1472907715 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 558369192 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 558369192 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 155514142 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 155514142 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data 713883334 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 713883334 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 713883334 # number of overall hits
+system.cpu.dcache.overall_hits::total 713883334 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 12749578 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 12749578 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 5214360 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 5214360 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 17960778 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 17960778 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 17960778 # number of overall misses
-system.cpu.dcache.overall_misses::total 17960778 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 384137632000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 384137632000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 288800427104 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 288800427104 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 70500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 70500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 672938059104 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 672938059104 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 672938059104 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 672938059104 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 571101224 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 571101224 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 17963938 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 17963938 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 17963938 # number of overall misses
+system.cpu.dcache.overall_misses::total 17963938 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 385716453000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 385716453000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 289481531698 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 289481531698 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 71500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 71500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 675197984698 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 675197984698 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 675197984698 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 675197984698 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 571118770 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 571118770 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 731829726 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 731829726 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 731829726 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 731829726 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022319 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.022319 # miss rate for ReadReq accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 731847272 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 731847272 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 731847272 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 731847272 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022324 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.022324 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032442 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.032442 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.024542 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.024542 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.024542 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.024542 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30136.877688 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 30136.877688 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55385.732308 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55385.732308 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70500 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70500 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 37467.088514 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 37467.088514 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 37467.088514 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 37467.088514 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 14080620 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 8619116 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1054999 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 67267 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.346572 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 128.132903 # average number of cycles each access was blocked
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.024546 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.024546 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.024546 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.024546 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30253.272148 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 30253.272148 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55516.215163 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55516.215163 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71500 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71500 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37586.301216 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37586.301216 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 37586.301216 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 37586.301216 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 14206702 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 8627771 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 1055420 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 67280 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.460709 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 128.236787 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3742782 # number of writebacks
-system.cpu.dcache.writebacks::total 3742782 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5412183 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 5412183 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3335275 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 3335275 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 8747458 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 8747458 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 8747458 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 8747458 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334248 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 7334248 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879072 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1879072 # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks 3742826 # number of writebacks
+system.cpu.dcache.writebacks::total 3742826 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5415535 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 5415535 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3335243 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 3335243 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 8750778 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 8750778 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 8750778 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 8750778 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334043 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 7334043 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879117 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1879117 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 9213320 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 9213320 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 9213320 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 9213320 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168546702500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 168546702500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77098541067 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 77098541067 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 68500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 68500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245645243567 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 245645243567 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245645243567 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 245645243567 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data 9213160 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 9213160 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 9213160 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 9213160 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168998137000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 168998137000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77338215218 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 77338215218 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 69500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 69500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 246336352218 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 246336352218 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 246336352218 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 246336352218 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012842 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011691 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011691 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.166667 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.166667 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.012589 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.012589 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22980.774921 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22980.774921 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41030.115433 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41030.115433 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 68500 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 68500 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26661.968060 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26661.968060 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26661.968060 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26661.968060 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23042.970569 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23042.970569 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41156.679024 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41156.679024 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 69500 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 69500 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26737.444288 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26737.444288 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26737.444288 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26737.444288 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 913189263000 # Number of ticks simulated
final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3321406 # Simulator instruction rate (inst/s)
-host_op_rate 3321406 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1666724755 # Simulator tick rate (ticks/s)
-host_mem_usage 255644 # Number of bytes of host memory used
-host_seconds 547.89 # Real time elapsed on the host
+host_inst_rate 2928853 # Simulator instruction rate (inst/s)
+host_op_rate 2928852 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1469736098 # Simulator tick rate (ticks/s)
+host_mem_usage 279876 # Number of bytes of host memory used
+host_seconds 621.33 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7999999926 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3068994956 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11068994882 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 11068994882 # Throughput (bytes/s)
-system.membus.data_through_bus 10108087278 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 2270974172 # Transaction distribution
+system.membus.trans_dist::ReadResp 2270974172 # Transaction distribution
+system.membus.trans_dist::WriteReq 160728502 # Transaction distribution
+system.membus.trans_dist::WriteResp 160728502 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3652757018 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1210648330 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 4863405348 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 7305514036 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2802573242 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 10108087278 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 2431702674 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.751070 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.432393 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 605324165 24.89% 24.89% # Request fanout histogram
+system.membus.snoop_fanout::1 1826378509 75.11% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 2431702674 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
sim_ticks 2623386226000 # Number of ticks simulated
final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1619868 # Simulator instruction rate (inst/s)
-host_op_rate 1619868 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2335193556 # Simulator tick rate (ticks/s)
-host_mem_usage 265412 # Number of bytes of host memory used
-host_seconds 1123.41 # Real time elapsed on the host
+host_inst_rate 1656263 # Simulator instruction rate (inst/s)
+host_op_rate 1656263 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2387660297 # Simulator tick rate (ticks/s)
+host_mem_usage 289632 # Number of bytes of host memory used
+host_seconds 1098.73 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 19566 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 47788276 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 72644797 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 72644797 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 1178362 # Transaction distribution
system.membus.trans_dist::ReadResp 1178362 # Transaction distribution
system.membus.trans_dist::Writeback 1018077 # Transaction distribution
system.membus.trans_dist::ReadExResp 781301 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937403 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4937403 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575360 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 190575360 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 190575360 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575360 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 190575360 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 2977740 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 2977740 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 2977740 # Request fanout histogram
system.membus.reqLayer0.occupancy 11122356000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 17636967000 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 312415345 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 7223216 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 3693497 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1604 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916965 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 21918569 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819534784 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 819586112 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 819586112 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819534784 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 819586112 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 12806033 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 12806033 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 12806033 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 10096513500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks)
---------- Begin Simulation Statistics ----------
-sim_seconds 1.095875 # Number of seconds simulated
-sim_ticks 1095875470500 # Number of ticks simulated
-final_tick 1095875470500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.096187 # Number of seconds simulated
+sim_ticks 1096186990500 # Number of ticks simulated
+final_tick 1096186990500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 232088 # Simulator instruction rate (inst/s)
-host_op_rate 250040 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 164667871 # Simulator tick rate (ticks/s)
-host_mem_usage 318056 # Number of bytes of host memory used
-host_seconds 6655.07 # Real time elapsed on the host
+host_inst_rate 242878 # Simulator instruction rate (inst/s)
+host_op_rate 261664 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 172372275 # Simulator tick rate (ticks/s)
+host_mem_usage 308000 # Number of bytes of host memory used
+host_seconds 6359.42 # Real time elapsed on the host
sim_insts 1544563087 # Number of instructions simulated
sim_ops 1664032480 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 131539072 # Number of bytes read from this memory
-system.physmem.bytes_read::total 131539072 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 131551936 # Number of bytes read from this memory
+system.physmem.bytes_read::total 131551936 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 50432 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 50432 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 66963456 # Number of bytes written to this memory
-system.physmem.bytes_written::total 66963456 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2055298 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2055298 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1046304 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1046304 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 120031040 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 120031040 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 46020 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 46020 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 61104987 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 61104987 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 61104987 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 120031040 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 181136026 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 2055298 # Number of read requests accepted
-system.physmem.writeReqs 1046304 # Number of write requests accepted
-system.physmem.readBursts 2055298 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1046304 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 131453056 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 86016 # Total number of bytes read from write queue
-system.physmem.bytesWritten 66961856 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 131539072 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 66963456 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 1344 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_written::writebacks 66968384 # Number of bytes written to this memory
+system.physmem.bytes_written::total 66968384 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 2055499 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2055499 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1046381 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1046381 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 120008664 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 120008664 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 46007 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 46007 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 61092117 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 61092117 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 61092117 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 120008664 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 181100781 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 2055499 # Number of read requests accepted
+system.physmem.writeReqs 1046381 # Number of write requests accepted
+system.physmem.readBursts 2055499 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1046381 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 131465088 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 86848 # Total number of bytes read from write queue
+system.physmem.bytesWritten 66966784 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 131551936 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 66968384 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 1357 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 127944 # Per bank write bursts
-system.physmem.perBankRdBursts::1 125151 # Per bank write bursts
-system.physmem.perBankRdBursts::2 122313 # Per bank write bursts
-system.physmem.perBankRdBursts::3 124176 # Per bank write bursts
-system.physmem.perBankRdBursts::4 123203 # Per bank write bursts
-system.physmem.perBankRdBursts::5 123365 # Per bank write bursts
-system.physmem.perBankRdBursts::6 123797 # Per bank write bursts
-system.physmem.perBankRdBursts::7 124247 # Per bank write bursts
-system.physmem.perBankRdBursts::8 131879 # Per bank write bursts
-system.physmem.perBankRdBursts::9 134089 # Per bank write bursts
-system.physmem.perBankRdBursts::10 132451 # Per bank write bursts
-system.physmem.perBankRdBursts::11 133680 # Per bank write bursts
-system.physmem.perBankRdBursts::12 133764 # Per bank write bursts
-system.physmem.perBankRdBursts::13 133810 # Per bank write bursts
-system.physmem.perBankRdBursts::14 129795 # Per bank write bursts
-system.physmem.perBankRdBursts::15 130290 # Per bank write bursts
-system.physmem.perBankWrBursts::0 65788 # Per bank write bursts
-system.physmem.perBankWrBursts::1 64108 # Per bank write bursts
-system.physmem.perBankWrBursts::2 62418 # Per bank write bursts
-system.physmem.perBankWrBursts::3 62855 # Per bank write bursts
-system.physmem.perBankWrBursts::4 62808 # Per bank write bursts
-system.physmem.perBankWrBursts::5 62982 # Per bank write bursts
-system.physmem.perBankWrBursts::6 64271 # Per bank write bursts
-system.physmem.perBankWrBursts::7 65268 # Per bank write bursts
-system.physmem.perBankWrBursts::8 67081 # Per bank write bursts
-system.physmem.perBankWrBursts::9 67609 # Per bank write bursts
-system.physmem.perBankWrBursts::10 67274 # Per bank write bursts
-system.physmem.perBankWrBursts::11 67626 # Per bank write bursts
-system.physmem.perBankWrBursts::12 67000 # Per bank write bursts
-system.physmem.perBankWrBursts::13 67431 # Per bank write bursts
-system.physmem.perBankWrBursts::14 66125 # Per bank write bursts
-system.physmem.perBankWrBursts::15 65635 # Per bank write bursts
+system.physmem.perBankRdBursts::0 127914 # Per bank write bursts
+system.physmem.perBankRdBursts::1 125107 # Per bank write bursts
+system.physmem.perBankRdBursts::2 122280 # Per bank write bursts
+system.physmem.perBankRdBursts::3 124254 # Per bank write bursts
+system.physmem.perBankRdBursts::4 123262 # Per bank write bursts
+system.physmem.perBankRdBursts::5 123345 # Per bank write bursts
+system.physmem.perBankRdBursts::6 123865 # Per bank write bursts
+system.physmem.perBankRdBursts::7 124190 # Per bank write bursts
+system.physmem.perBankRdBursts::8 131999 # Per bank write bursts
+system.physmem.perBankRdBursts::9 134064 # Per bank write bursts
+system.physmem.perBankRdBursts::10 132428 # Per bank write bursts
+system.physmem.perBankRdBursts::11 133673 # Per bank write bursts
+system.physmem.perBankRdBursts::12 133725 # Per bank write bursts
+system.physmem.perBankRdBursts::13 133862 # Per bank write bursts
+system.physmem.perBankRdBursts::14 129895 # Per bank write bursts
+system.physmem.perBankRdBursts::15 130279 # Per bank write bursts
+system.physmem.perBankWrBursts::0 65789 # Per bank write bursts
+system.physmem.perBankWrBursts::1 64087 # Per bank write bursts
+system.physmem.perBankWrBursts::2 62403 # Per bank write bursts
+system.physmem.perBankWrBursts::3 62885 # Per bank write bursts
+system.physmem.perBankWrBursts::4 62820 # Per bank write bursts
+system.physmem.perBankWrBursts::5 62979 # Per bank write bursts
+system.physmem.perBankWrBursts::6 64285 # Per bank write bursts
+system.physmem.perBankWrBursts::7 65232 # Per bank write bursts
+system.physmem.perBankWrBursts::8 67082 # Per bank write bursts
+system.physmem.perBankWrBursts::9 67588 # Per bank write bursts
+system.physmem.perBankWrBursts::10 67303 # Per bank write bursts
+system.physmem.perBankWrBursts::11 67613 # Per bank write bursts
+system.physmem.perBankWrBursts::12 67020 # Per bank write bursts
+system.physmem.perBankWrBursts::13 67468 # Per bank write bursts
+system.physmem.perBankWrBursts::14 66169 # Per bank write bursts
+system.physmem.perBankWrBursts::15 65633 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 1095875382500 # Total gap between requests
+system.physmem.totGap 1096186902500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 2055298 # Read request sizes (log2)
+system.physmem.readPktSize::6 2055499 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1046304 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1922424 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 131512 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1046381 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 1922421 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 131703 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 33528 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 34841 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::18 60757 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::20 61327 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 61251 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 61258 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 61259 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 61367 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::27 62306 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 61683 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::32 60798 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 90 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 13 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 31796 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1911965 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 103.774418 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 81.877172 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 125.825249 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 1485376 77.69% 77.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 306998 16.06% 93.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 52789 2.76% 96.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 21060 1.10% 97.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 13283 0.69% 98.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 6873 0.36% 98.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 5659 0.30% 98.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 4134 0.22% 99.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 15793 0.83% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1911965 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 60795 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 33.737117 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 161.571664 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 60754 99.93% 99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 14 0.02% 99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071 14 0.02% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 1916158 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 103.556187 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 81.764224 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 125.552714 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 1491113 77.82% 77.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 305811 15.96% 93.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 52727 2.75% 96.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 21051 1.10% 97.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 13077 0.68% 98.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 6875 0.36% 98.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 5570 0.29% 98.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 4107 0.21% 99.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 15827 0.83% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1916158 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 61021 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 33.615247 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 160.737468 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 60978 99.93% 99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047 19 0.03% 99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071 9 0.01% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 60795 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 60795 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.209951 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.175292 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.091996 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 25805 42.45% 42.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 1192 1.96% 44.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 29551 48.61% 93.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 3811 6.27% 99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 363 0.60% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 60 0.10% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 11 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 61021 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 61021 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.147474 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.112394 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.099372 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 27727 45.44% 45.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 1223 2.00% 47.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 27936 45.78% 93.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 3708 6.08% 99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 355 0.58% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 59 0.10% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 10 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 60795 # Writes before turning the bus around for reads
-system.physmem.totQLat 38124649000 # Total ticks spent queuing
-system.physmem.totMemAccLat 76636286500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 10269770000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 18561.59 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 61021 # Writes before turning the bus around for reads
+system.physmem.totQLat 38533876500 # Total ticks spent queuing
+system.physmem.totMemAccLat 77049039000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 10270710000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 18759.11 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 37311.59 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 119.95 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 61.10 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 120.03 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 61.10 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 37509.11 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 119.93 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 61.09 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 120.01 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 61.09 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 1.41 # Data bus utilization in percentage
system.physmem.busUtilRead 0.94 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.48 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.69 # Average write queue length when enqueuing
-system.physmem.readRowHits 779774 # Number of row buffer hits during reads
-system.physmem.writeRowHits 408484 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 37.96 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 39.04 # Row buffer hit rate for writes
-system.physmem.avgGap 353325.60 # Average gap between requests
-system.physmem.pageHitRate 38.33 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 306310282500 # Time in different power states
-system.physmem.memoryStateTime::REF 36593440000 # Time in different power states
+system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing
+system.physmem.readRowHits 777772 # Number of row buffer hits during reads
+system.physmem.writeRowHits 406558 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 37.86 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 38.85 # Row buffer hit rate for writes
+system.physmem.avgGap 353394.36 # Average gap between requests
+system.physmem.pageHitRate 38.20 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 306608104500 # Time in different power states
+system.physmem.memoryStateTime::REF 36603840000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 752968660500 # Time in different power states
+system.physmem.memoryStateTime::ACT 752971887000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 181136026 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 1255348 # Transaction distribution
-system.membus.trans_dist::ReadResp 1255348 # Transaction distribution
-system.membus.trans_dist::Writeback 1046304 # Transaction distribution
-system.membus.trans_dist::ReadExReq 799950 # Transaction distribution
-system.membus.trans_dist::ReadExResp 799950 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5156900 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5156900 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198502528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 198502528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 198502528 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 12227667000 # Layer occupancy (ticks)
+system.membus.trans_dist::ReadReq 1255486 # Transaction distribution
+system.membus.trans_dist::ReadResp 1255486 # Transaction distribution
+system.membus.trans_dist::Writeback 1046381 # Transaction distribution
+system.membus.trans_dist::ReadExReq 800013 # Transaction distribution
+system.membus.trans_dist::ReadExResp 800013 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5157379 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 5157379 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198520320 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 198520320 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 3101880 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 3101880 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 3101880 # Request fanout histogram
+system.membus.reqLayer0.occupancy 12229457500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 19360882250 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 19361348500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.8 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 239641872 # Number of BP lookups
-system.cpu.branchPred.condPredicted 186303374 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 14594643 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 130836287 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 121989290 # Number of BTB hits
+system.cpu.branchPred.lookups 239650352 # Number of BP lookups
+system.cpu.branchPred.condPredicted 186306880 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 14598405 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 131764254 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 121991524 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 93.238117 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 15653729 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 92.583171 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 15654227 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 2191750941 # number of cpu cycles simulated
+system.cpu.numCycles 2192373981 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1544563087 # Number of instructions committed
system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 42066132 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 42081657 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.419010 # CPI: cycles per instruction
-system.cpu.ipc 0.704717 # IPC: instructions per cycle
-system.cpu.tickCycles 1808188284 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 383562657 # Total number of cycles that the object has spent stopped
+system.cpu.cpi 1.419414 # CPI: cycles per instruction
+system.cpu.ipc 0.704516 # IPC: instructions per cycle
+system.cpu.tickCycles 1808241834 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 384132147 # Total number of cycles that the object has spent stopped
system.cpu.icache.tags.replacements 29 # number of replacements
-system.cpu.icache.tags.tagsinuse 661.141376 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 464847257 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 661.144399 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 464861353 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 566886.898780 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 566904.089024 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 661.141376 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.322823 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.322823 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 661.144399 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.322824 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.322824 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 929696974 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 929696974 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 464847257 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 464847257 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 464847257 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 464847257 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 464847257 # number of overall hits
-system.cpu.icache.overall_hits::total 464847257 # number of overall hits
+system.cpu.icache.tags.tag_accesses 929725166 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 929725166 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 464861353 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 464861353 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 464861353 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 464861353 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 464861353 # number of overall hits
+system.cpu.icache.overall_hits::total 464861353 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses
system.cpu.icache.overall_misses::total 820 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 58324499 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 58324499 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 58324499 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 58324499 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 58324499 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 58324499 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 464848077 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 464848077 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 464848077 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 464848077 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 464848077 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 464848077 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 59141749 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 59141749 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 59141749 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 59141749 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 59141749 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 59141749 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 464862173 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 464862173 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 464862173 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 464862173 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 464862173 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 464862173 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71127.437805 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 71127.437805 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 71127.437805 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 71127.437805 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 71127.437805 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 71127.437805 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72124.084146 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 72124.084146 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 72124.084146 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 72124.084146 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 72124.084146 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 72124.084146 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56360501 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 56360501 # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26598.011700 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.014563 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.014563 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22959.656456 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22959.656456 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40909.369978 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40909.369978 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26638.119103 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26638.119103 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26638.119103 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26638.119103 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.506591 # Number of seconds simulated
-sim_ticks 506591420000 # Number of ticks simulated
-final_tick 506591420000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.753004 # Number of seconds simulated
+sim_ticks 753003557500 # Number of ticks simulated
+final_tick 753003557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 188296 # Simulator instruction rate (inst/s)
-host_op_rate 202861 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 61758141 # Simulator tick rate (ticks/s)
-host_mem_usage 254008 # Number of bytes of host memory used
-host_seconds 8202.83 # Real time elapsed on the host
+host_inst_rate 139511 # Simulator instruction rate (inst/s)
+host_op_rate 150302 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 68014357 # Simulator tick rate (ticks/s)
+host_mem_usage 308752 # Number of bytes of host memory used
+host_seconds 11071.24 # Real time elapsed on the host
sim_insts 1544563023 # Number of instructions simulated
sim_ops 1664032415 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 46336 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 143772736 # Number of bytes read from this memory
-system.physmem.bytes_read::total 143819072 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 46336 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 46336 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 70460288 # Number of bytes written to this memory
-system.physmem.bytes_written::total 70460288 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 724 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2246449 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2247173 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1100942 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1100942 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 91466 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 283804128 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 283895594 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 91466 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 91466 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 139087014 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 139087014 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 139087014 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 91466 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 283804128 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 422982608 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 2247174 # Number of read requests accepted
-system.physmem.writeReqs 1100942 # Number of write requests accepted
-system.physmem.readBursts 2247174 # Number of DRAM read bursts, including those serviced by the write queue
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-system.physmem.bytesReadDRAM 143725504 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 93632 # Total number of bytes read from write queue
-system.physmem.bytesWritten 70458432 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 143819136 # Total read bytes from the system interface side
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-system.physmem.servicedByWrQ 1463 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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+system.physmem.bw_read::cpu.inst 19378 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_write::writebacks 142162282 # Write bandwidth from this memory (bytes/s)
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+system.physmem.bw_total::total 575724026 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 5101149 # Number of read requests accepted
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+system.physmem.bytesReadDRAM 326003456 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 470080 # Total number of bytes read from write queue
+system.physmem.bytesWritten 107046272 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 326473536 # Total read bytes from the system interface side
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+system.physmem.servicedByWrQ 7345 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 139870 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 506591366500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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+system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 2025013 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 105.768407 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 82.613194 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 129.925028 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 1567130 77.39% 77.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 318117 15.71% 93.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 66732 3.30% 96.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 23886 1.18% 97.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 14001 0.69% 98.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 6496 0.32% 98.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 4833 0.24% 98.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 3896 0.19% 99.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 19922 0.98% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 2025013 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 65320 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 34.335441 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 154.678788 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 65282 99.94% 99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 11 0.02% 99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071 14 0.02% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 65320 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 65320 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.854149 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.813582 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.224401 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17 41990 64.28% 64.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19 22168 33.94% 98.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21 1073 1.64% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23 57 0.09% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25 8 0.01% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27 3 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29 2 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31 14 0.02% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33 2 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-45 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-85 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 65320 # Writes before turning the bus around for reads
-system.physmem.totQLat 50678676000 # Total ticks spent queuing
-system.physmem.totMemAccLat 92785757250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 11228555000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 22566.87 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 4344411 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 99.679291 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 80.657847 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 113.406930 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 3407328 78.43% 78.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 696147 16.02% 94.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 107309 2.47% 96.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 43326 1.00% 97.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 33261 0.77% 98.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 16273 0.37% 99.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 9699 0.22% 99.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 6677 0.15% 99.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 24391 0.56% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 4344411 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 100519 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 50.674768 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean 34.618065 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 99.194987 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-255 98006 97.50% 97.50% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::256-511 1235 1.23% 98.73% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-767 738 0.73% 99.46% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::768-1023 394 0.39% 99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1279 104 0.10% 99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1280-1535 26 0.03% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-1791 7 0.01% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1792-2047 1 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2304-2559 2 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-3327 2 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3328-3583 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 100519 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 100519 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.639620 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.599991 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.204272 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 73763 73.38% 73.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 1810 1.80% 75.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 17937 17.84% 93.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 4183 4.16% 97.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 1485 1.48% 98.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 646 0.64% 99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 326 0.32% 99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 183 0.18% 99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 100 0.10% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 51 0.05% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 16 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27 9 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28 2 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29 3 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30 3 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 100519 # Writes before turning the bus around for reads
+system.physmem.totQLat 147032532073 # Total ticks spent queuing
+system.physmem.totMemAccLat 242541357073 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 25469020000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 28864.98 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 41316.87 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 283.71 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 139.08 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 283.90 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 139.09 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 47614.98 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 432.94 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 142.16 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 433.56 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 142.16 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 3.30 # Data bus utilization in percentage
-system.physmem.busUtilRead 2.22 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 1.09 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.41 # Average write queue length when enqueuing
-system.physmem.readRowHits 906473 # Number of row buffer hits during reads
-system.physmem.writeRowHits 415128 # Number of row buffer hits during writes
+system.physmem.busUtil 4.49 # Data bus utilization in percentage
+system.physmem.busUtilRead 3.38 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 1.11 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing
+system.physmem.readRowHits 2056015 # Number of row buffer hits during reads
+system.physmem.writeRowHits 365966 # Number of row buffer hits during writes
system.physmem.readRowHitRate 40.36 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 37.71 # Row buffer hit rate for writes
-system.physmem.avgGap 151306.40 # Average gap between requests
-system.physmem.pageHitRate 39.49 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 89126966500 # Time in different power states
-system.physmem.memoryStateTime::REF 16916120000 # Time in different power states
+system.physmem.writeRowHitRate 21.88 # Row buffer hit rate for writes
+system.physmem.avgGap 111164.37 # Average gap between requests
+system.physmem.pageHitRate 35.79 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 77100737509 # Time in different power states
+system.physmem.memoryStateTime::REF 25144340000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 400546526000 # Time in different power states
+system.physmem.memoryStateTime::ACT 650755672741 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 422982608 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 1419539 # Transaction distribution
-system.membus.trans_dist::ReadResp 1419538 # Transaction distribution
-system.membus.trans_dist::Writeback 1100942 # Transaction distribution
-system.membus.trans_dist::ReadExReq 827635 # Transaction distribution
-system.membus.trans_dist::ReadExResp 827635 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5595289 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5595289 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214279360 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 214279360 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 214279360 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 12858312000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 2.5 # Layer utilization (%)
-system.membus.respLayer1.occupancy 21011522750 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 4.1 # Layer utilization (%)
+system.membus.trans_dist::ReadReq 4164250 # Transaction distribution
+system.membus.trans_dist::ReadResp 4164249 # Transaction distribution
+system.membus.trans_dist::Writeback 1672636 # Transaction distribution
+system.membus.trans_dist::ReadExReq 936899 # Transaction distribution
+system.membus.trans_dist::ReadExResp 936899 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11874933 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 11874933 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 433522176 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 433522176 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 6773785 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 6773785 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 6773785 # Request fanout histogram
+system.membus.reqLayer0.occupancy 21336071694 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
+system.membus.respLayer1.occupancy 47387677526 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 6.3 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 322479068 # Number of BP lookups
-system.cpu.branchPred.condPredicted 251697336 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 15342173 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 182789015 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 169211218 # Number of BTB hits
+system.cpu.branchPred.lookups 286237274 # Number of BP lookups
+system.cpu.branchPred.condPredicted 223376247 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 14631258 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 157873028 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 150326972 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 92.571875 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 19180311 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 62 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 95.220174 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 16640209 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 1013182841 # number of cpu cycles simulated
+system.cpu.numCycles 1506007116 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 309137299 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2319640214 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 322479068 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 188391529 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 688452374 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 31084694 # Number of cycles fetch has spent squashing
-system.cpu.fetch.CacheLines 300792002 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 5498702 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1013132020 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.455758 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.154346 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 13915908 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2067206547 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 286237274 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 166967181 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 1477423210 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 29286858 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.IcacheWaitRetryStallCycles 232 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 656844028 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 587 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1505982817 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.470565 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.223309 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 555222202 54.80% 54.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 28050197 2.77% 57.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 43308558 4.27% 61.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 56959165 5.62% 67.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 42292761 4.17% 71.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 51207543 5.05% 76.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 41019007 4.05% 80.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 29441196 2.91% 83.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 165631391 16.35% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 423738570 28.14% 28.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 465347942 30.90% 59.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 101390896 6.73% 65.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 515505409 34.23% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1013132020 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.318283 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.289459 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 248682792 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 345622952 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 359459924 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 43824601 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 15541751 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 49856372 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 610 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 2395697302 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2189 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 15541751 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 269479595 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 192381996 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 17471 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 380094168 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 155617039 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2338847400 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 939227 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 43524152 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 85831703 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 28336004 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 2341659219 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 10827293229 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 2896191361 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 924 # Number of floating rename lookups
+system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 1505982817 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.190064 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.372641 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 74738188 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 508470466 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 849951241 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 58180203 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 14642719 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 42195522 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 748 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 2037029518 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 52402529 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 14642719 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 139800206 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 434773312 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 14137 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 837909741 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 78842702 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 1976226014 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 26698193 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 45123172 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 125355 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 1314299 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 18015097 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 1985707207 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 9127389229 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 2432660668 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 146 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 666760274 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 297 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 295 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 177584133 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 623787680 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 234474986 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 103326529 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 119861826 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2235979798 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 279 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2042453270 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1123672 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 568282292 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1410742018 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 109 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1013132020 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.015979 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.060962 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 310808262 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 156 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 144 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 111604908 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 542499825 # Number of loads inserted to the mem dependence unit.
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+system.cpu.memDep0.conflictingLoads 26858708 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 28865215 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 1947820848 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 214 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1857727691 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 13537484 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 279225798 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 646033301 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed
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+system.cpu.iq.issued_per_cycle::mean 1.233565 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.149736 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 369509753 36.47% 36.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 122144381 12.06% 48.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 148105848 14.62% 63.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 116397380 11.49% 74.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 120158766 11.86% 86.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 67734855 6.69% 93.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 38716090 3.82% 97.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 19620402 1.94% 98.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 10744545 1.06% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 553461726 36.75% 36.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 325286672 21.60% 58.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 378400557 25.13% 83.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 219701727 14.59% 98.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 29125951 1.93% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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+system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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-system.cpu.iq.fu_full::IntMult 890 0.00% 18.71% # attempts to use FU when none available
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-system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 18.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.71% # attempts to use FU when none available
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-system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.71% # attempts to use FU when none available
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-system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 18.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 18.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.71% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.01% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.01% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.01% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.01% # attempts to use FU when none available
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+system.cpu.iq.fu_full::MemRead 191579576 47.17% 88.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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-system.cpu.iq.FU_type_0::IntMult 999501 0.05% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 75 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 36 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 18 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.15% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 618802083 30.30% 90.45% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 195096510 9.55% 100.00% # Type of FU issued
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+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 27 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 26 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 532245079 28.65% 89.97% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 186316069 10.03% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2042453270 # Type of FU issued
-system.cpu.iq.rate 2.015878 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 19520263 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.009557 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 5118681932 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2804481694 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1937195401 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 563 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 772 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 222 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2061973250 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 283 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 29620868 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1857727691 # Type of FU issued
+system.cpu.iq.rate 1.233545 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 406189268 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.218648 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 5641164724 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2227059400 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1805827330 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 227 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 234 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 67 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2263916833 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 126 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 17868715 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 165481346 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 152761 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 223174 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 59627941 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 84193491 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 66602 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 12979 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 24445259 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 27365932 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 20554693 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 4569389 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 5015263 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 15541751 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 99594513 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 79709192 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2235980127 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 3715851 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 623787680 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 234474986 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 217 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 887425 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 78519079 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 223174 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 8257753 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 10408115 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 18665868 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2014561503 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 604829298 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 27891767 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 14642719 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 25280273 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1153411 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 1947821148 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 542499825 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 199292304 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 152 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 158606 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 993784 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 12979 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 7710323 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 8723960 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 16434283 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1828067374 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 517076026 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 29660317 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 50 # number of nop insts executed
-system.cpu.iew.exec_refs 796810326 # number of memory reference insts executed
-system.cpu.iew.exec_branches 245407289 # Number of branches executed
-system.cpu.iew.exec_stores 191981028 # Number of stores executed
-system.cpu.iew.exec_rate 1.988349 # Inst execution rate
-system.cpu.iew.wb_sent 1947397166 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1937195623 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1312629106 # num instructions producing a value
-system.cpu.iew.wb_consumers 2061058840 # num instructions consuming a value
+system.cpu.iew.exec_nop 86 # number of nop insts executed
+system.cpu.iew.exec_refs 698832649 # number of memory reference insts executed
+system.cpu.iew.exec_branches 229600081 # Number of branches executed
+system.cpu.iew.exec_stores 181756623 # Number of stores executed
+system.cpu.iew.exec_rate 1.213850 # Inst execution rate
+system.cpu.iew.wb_sent 1808848691 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1805827397 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1169333238 # num instructions producing a value
+system.cpu.iew.wb_consumers 1689629138 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.911990 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.636871 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.199083 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.692065 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 572342091 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 257853927 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 15341577 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 933174586 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.783195 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.675212 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 14630548 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1466512041 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.134687 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.044179 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 468896979 50.25% 50.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 178641910 19.14% 69.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 68227019 7.31% 76.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 32102473 3.44% 80.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 24397966 2.61% 82.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 27603302 2.96% 85.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 17322198 1.86% 87.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 14774408 1.58% 89.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 101208331 10.85% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 886829793 60.47% 60.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 250699029 17.09% 77.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 109472668 7.46% 85.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 55016344 3.75% 88.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 29216480 1.99% 90.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 33954895 2.32% 93.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 24874922 1.70% 94.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 18134171 1.24% 96.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 58313739 3.98% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 933174586 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1466512041 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1544563041 # Number of instructions committed
system.cpu.commit.committedOps 1664032433 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction
-system.cpu.commit.bw_lim_events 101208331 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 58313739 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3068340180 # The number of ROB reads
-system.cpu.rob.rob_writes 4552875899 # The number of ROB writes
-system.cpu.timesIdled 556 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 50821 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3330084063 # The number of ROB reads
+system.cpu.rob.rob_writes 3883248691 # The number of ROB writes
+system.cpu.timesIdled 433 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 24299 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1544563023 # Number of Instructions Simulated
system.cpu.committedOps 1664032415 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.655967 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.655967 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.524466 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.524466 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 2376547647 # number of integer regfile reads
-system.cpu.int_regfile_writes 1366493054 # number of integer regfile writes
-system.cpu.fp_regfile_reads 209 # number of floating regfile reads
-system.cpu.fp_regfile_writes 233 # number of floating regfile writes
-system.cpu.cc_regfile_reads 7643535318 # number of cc regfile reads
-system.cpu.cc_regfile_writes 583887345 # number of cc regfile writes
-system.cpu.misc_regfile_reads 725285725 # number of misc regfile reads
+system.cpu.cpi 0.975038 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.975038 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.025601 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.025601 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 2176017050 # number of integer regfile reads
+system.cpu.int_regfile_writes 1261587528 # number of integer regfile writes
+system.cpu.fp_regfile_reads 38 # number of floating regfile reads
+system.cpu.fp_regfile_writes 49 # number of floating regfile writes
+system.cpu.cc_regfile_reads 6966468810 # number of cc regfile reads
+system.cpu.cc_regfile_writes 551975360 # number of cc regfile writes
+system.cpu.misc_regfile_reads 675847678 # number of misc regfile reads
system.cpu.misc_regfile_writes 124 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 1691907313 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 7714547 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 7714546 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 3783532 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1894199 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1894199 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1502 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22999521 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 23001023 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 48064 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 857057664 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 857105728 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 857105728 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 10479902270 # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::ReadReq 14271352 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 14271352 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 4800041 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq 2156446 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 2737659 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 2737659 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2176 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38815887 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 38818063 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 69632 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1395709696 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 1395779328 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 2156446 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 23967212 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5.089975 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.286146 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 21810766 91.00% 91.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 2156446 9.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 23967212 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 15706134446 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1252249 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1655247 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 14758141993 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 2.9 # Layer utilization (%)
-system.cpu.icache.tags.replacements 15 # number of replacements
-system.cpu.icache.tags.tagsinuse 614.894819 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 300790815 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 751 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 400520.392810 # Average number of references to valid blocks.
+system.cpu.toL2Bus.respLayer1.occupancy 25977831897 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 3.4 # Layer utilization (%)
+system.cpu.icache.tags.replacements 600 # number of replacements
+system.cpu.icache.tags.tagsinuse 446.759697 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 656842791 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 1088 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 603715.800551 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 614.894819 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.300242 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.300242 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 736 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 709 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.359375 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 601584755 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 601584755 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 300790815 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 300790815 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 300790815 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 300790815 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 300790815 # number of overall hits
-system.cpu.icache.overall_hits::total 300790815 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1187 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1187 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1187 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1187 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1187 # number of overall misses
-system.cpu.icache.overall_misses::total 1187 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 83295499 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 83295499 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 83295499 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 83295499 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 83295499 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 83295499 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 300792002 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 300792002 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 300792002 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 300792002 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 300792002 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 300792002 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70173.124684 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 70173.124684 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 70173.124684 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 70173.124684 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 70173.124684 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 70173.124684 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 65 # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst 446.759697 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.872578 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.872578 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 1313689140 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 1313689140 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 656842791 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 656842791 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 656842791 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 656842791 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 656842791 # number of overall hits
+system.cpu.icache.overall_hits::total 656842791 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1235 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1235 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1235 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1235 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1235 # number of overall misses
+system.cpu.icache.overall_misses::total 1235 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 31675742 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 31675742 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 31675742 # number of demand (read+write) miss cycles
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-system.cpu.dcache.overall_misses::cpu.data 18233919 # number of overall misses
-system.cpu.dcache.overall_misses::total 18233919 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 378927155489 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 378927155489 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 307221007401 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 307221007401 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 228000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 686148162890 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 686148162890 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 686148162890 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 686148162890 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 524388902 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 524388902 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 20891298 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 20891298 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 20891300 # number of overall misses
+system.cpu.dcache.overall_misses::total 20891300 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 389285003128 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 389285003128 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 129453998118 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 129453998118 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 384750 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 384750 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 518739001246 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 518739001246 # number of demand (read+write) miss cycles
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+system.cpu.dcache.overall_miss_latency::total 518739001246 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 486682973 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 486682973 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 4 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 4 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 66 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 66 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 696974949 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 696974949 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 696974953 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 696974953 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023933 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.023933 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032933 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.032933 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.500000 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.500000 # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045455 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045455 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.026162 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.026162 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.026162 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.026162 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30193.153449 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 30193.153449 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54051.901302 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54051.901302 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 76000 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 76000 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 37630.321718 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 37630.321718 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 37630.317591 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 37630.317591 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 28822616 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 4626055 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1847693 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 65151 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.599245 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 71.005127 # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 659269020 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 659269020 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 659269022 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 659269022 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035449 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.035449 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.021085 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.021085 # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.031689 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.031689 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.031689 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.031689 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22564.100665 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 22564.100665 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35575.104329 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 35575.104329 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 96187.500000 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 96187.500000 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 24830.386376 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 24830.386376 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 24830.383999 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 24830.383999 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 20820542 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 1650046 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 1039120 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 52884 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.036706 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 31.201233 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3783532 # number of writebacks
-system.cpu.dcache.writebacks::total 3783532 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4836306 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 4836306 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3789617 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 3789617 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 8625923 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 8625923 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 8625923 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 8625923 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7713796 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 7713796 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894198 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1894198 # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks 4800041 # number of writebacks
+system.cpu.dcache.writebacks::total 4800041 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2982110 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 2982110 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 901266 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 901266 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3883376 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3883376 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3883376 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3883376 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14270295 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 14270295 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737627 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 2737627 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 9607994 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 9607994 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 9607995 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 9607995 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 192253948507 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 192253948507 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84881076130 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 84881076130 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69500 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69500 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 277135024637 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 277135024637 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 277135094137 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 277135094137 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014710 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014710 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010975 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010975 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013785 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.013785 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013785 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.013785 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24923.390314 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24923.390314 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44811.089511 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44811.089511 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69500 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69500 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28844.212917 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28844.212917 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28844.217148 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28844.217148 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_misses::cpu.data 17007922 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 17007922 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 17007923 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 17007923 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 301459973376 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 301459973376 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 108130443900 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 108130443900 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 101000 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 101000 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 409590417276 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 409590417276 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 409590518276 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 409590518276 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029322 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029322 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025798 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025798 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025798 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.025798 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21124.999404 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21124.999404 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39497.873122 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39497.873122 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 101000 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 101000 # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24082.331591 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24082.331591 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24082.336113 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24082.336113 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 832017490000 # Number of ticks simulated
final_tick 832017490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1782051 # Simulator instruction rate (inst/s)
-host_op_rate 1919890 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 959946236 # Simulator tick rate (ticks/s)
-host_mem_usage 306272 # Number of bytes of host memory used
-host_seconds 866.73 # Real time elapsed on the host
+host_inst_rate 2048371 # Simulator instruction rate (inst/s)
+host_op_rate 2206809 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1103406177 # Simulator tick rate (ticks/s)
+host_mem_usage 296712 # Number of bytes of host memory used
+host_seconds 754.04 # Real time elapsed on the host
sim_insts 1544563041 # Number of instructions simulated
sim_ops 1664032433 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2650840985 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10076480987 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 10076480987 # Throughput (bytes/s)
-system.membus.data_through_bus 8383808419 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 1999474724 # Transaction distribution
+system.membus.trans_dist::ReadResp 1999474785 # Transaction distribution
+system.membus.trans_dist::WriteReq 172586047 # Transaction distribution
+system.membus.trans_dist::WriteResp 172586047 # Transaction distribution
+system.membus.trans_dist::SoftPFReq 1 # Transaction distribution
+system.membus.trans_dist::SoftPFResp 1 # Transaction distribution
+system.membus.trans_dist::LoadLockedReq 61 # Transaction distribution
+system.membus.trans_dist::StoreCondReq 61 # Transaction distribution
+system.membus.trans_dist::StoreCondResp 61 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131178 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 4344121788 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262356 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 8383808419 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 2172060894 # Request fanout histogram
+system.membus.snoop_fanout::mean 4.711106 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::4 627495305 28.89% 28.89% # Request fanout histogram
+system.membus.snoop_fanout::5 1544565589 71.11% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 4 # Request fanout histogram
+system.membus.snoop_fanout::max_value 5 # Request fanout histogram
+system.membus.snoop_fanout::total 2172060894 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
sim_ticks 2363670998000 # Number of ticks simulated
final_tick 2363670998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1066052 # Simulator instruction rate (inst/s)
-host_op_rate 1148821 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1637550718 # Simulator tick rate (ticks/s)
-host_mem_usage 316024 # Number of bytes of host memory used
-host_seconds 1443.42 # Real time elapsed on the host
+host_inst_rate 1205605 # Simulator instruction rate (inst/s)
+host_op_rate 1299208 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1851916301 # Simulator tick rate (ticks/s)
+host_mem_usage 306192 # Number of bytes of host memory used
+host_seconds 1276.34 # Real time elapsed on the host
sim_insts 1538759601 # Number of instructions simulated
sim_ops 1658228914 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 16679 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 53020117 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 80578984 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 80578984 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 1177898 # Transaction distribution
system.membus.trans_dist::ReadResp 1177898 # Transaction distribution
system.membus.trans_dist::Writeback 1017198 # Transaction distribution
system.membus.trans_dist::ReadExResp 780876 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 190462208 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 2975972 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 2975972 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 2975972 # Request fanout histogram
system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 346939438 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21927890 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 21929166 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 820050688 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 12813292 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 12813292 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 12813292 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks)
sim_ticks 2846007227500 # Number of ticks simulated
final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1186122 # Simulator instruction rate (inst/s)
-host_op_rate 1848085 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1122213991 # Simulator tick rate (ticks/s)
-host_mem_usage 278740 # Number of bytes of host memory used
-host_seconds 2536.06 # Real time elapsed on the host
+host_inst_rate 1299561 # Simulator instruction rate (inst/s)
+host_op_rate 2024834 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1229541445 # Simulator tick rate (ticks/s)
+host_mem_usage 299440 # Number of bytes of host memory used
+host_seconds 2314.69 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
sim_ops 4686862596 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 13588998587 # Throughput (bytes/s)
-system.membus.data_through_bus 38674388193 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution
+system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution
+system.membus.trans_dist::WriteReq 438528338 # Transaction distribution
+system.membus.trans_dist::WriteResp 438528338 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::total 8026465764 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::total 3355426168 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 11381891932 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::total 32105863056 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::total 6568525137 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 38674388193 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 5690945966 # Request fanout histogram
+system.membus.snoop_fanout::mean 2.705196 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.455955 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::2 1677713084 29.48% 29.48% # Request fanout histogram
+system.membus.snoop_fanout::3 4013232882 70.52% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 2 # Request fanout histogram
+system.membus.snoop_fanout::max_value 3 # Request fanout histogram
+system.membus.snoop_fanout::total 5690945966 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 46 # Number of system calls
sim_ticks 5882580526000 # Number of ticks simulated
final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 693030 # Simulator instruction rate (inst/s)
-host_op_rate 1079804 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1355284560 # Simulator tick rate (ticks/s)
-host_mem_usage 288492 # Number of bytes of host memory used
-host_seconds 4340.48 # Real time elapsed on the host
+host_inst_rate 912016 # Simulator instruction rate (inst/s)
+host_op_rate 1421004 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1783532526 # Simulator tick rate (ticks/s)
+host_mem_usage 308940 # Number of bytes of host memory used
+host_seconds 3298.27 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
sim_ops 4686862596 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 32392097 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 1177614 # Transaction distribution
system.membus.trans_dist::ReadResp 1177614 # Transaction distribution
system.membus.trans_dist::Writeback 1018421 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 190549120 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 2977330 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 2977330 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 2977330 # Request fanout histogram
system.membus.reqLayer0.occupancy 11124698000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 17630181000 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 139381638 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 7223525 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1350 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21923310 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 21924660 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43200 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819880512 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 819923712 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 819923712 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43200 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819880512 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 819923712 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 12811308 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 12811308 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 12811308 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks)
sim_ticks 51522973500 # Number of ticks simulated
final_tick 51522973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 335661 # Simulator instruction rate (inst/s)
-host_op_rate 335661 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 188179142 # Simulator tick rate (ticks/s)
-host_mem_usage 271092 # Number of bytes of host memory used
-host_seconds 273.80 # Real time elapsed on the host
+host_inst_rate 356175 # Simulator instruction rate (inst/s)
+host_op_rate 356175 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 199679816 # Simulator tick rate (ticks/s)
+host_mem_usage 295568 # Number of bytes of host memory used
+host_seconds 258.03 # Real time elapsed on the host
sim_insts 91903089 # Number of instructions simulated
sim_ops 91903089 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 4908 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 387 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 4906 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 389 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 970 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 349.690722 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 213.310004 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 331.842695 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 314 32.37% 32.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 200 20.62% 52.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 99 10.21% 63.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 77 7.94% 71.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 82 8.45% 79.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 28 2.89% 82.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 30 3.09% 85.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 24 2.47% 88.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 116 11.96% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 970 # Bytes accessed per row activation
-system.physmem.totQLat 35079750 # Total ticks spent queuing
-system.physmem.totMemAccLat 134717250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples 963 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 352.232606 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 215.271932 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 332.609683 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 308 31.98% 31.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 198 20.56% 52.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 99 10.28% 62.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 77 8.00% 70.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 83 8.62% 79.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 29 3.01% 82.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 26 2.70% 85.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 28 2.91% 88.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 115 11.94% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 963 # Bytes accessed per row activation
+system.physmem.totQLat 35638500 # Total ticks spent queuing
+system.physmem.totMemAccLat 135276000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 26570000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 6601.38 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 6706.53 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 25351.38 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 25456.53 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 6.60 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 6.60 # Average system read bandwidth in MiByte/s
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 4339 # Number of row buffer hits during reads
+system.physmem.readRowHits 4346 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.65 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 81.78 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 9695689.12 # Average gap between requests
-system.physmem.pageHitRate 81.65 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 48460480000 # Time in different power states
+system.physmem.pageHitRate 81.78 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 48467499750 # Time in different power states
system.physmem.memoryStateTime::REF 1720420000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 1340990000 # Time in different power states
+system.physmem.memoryStateTime::ACT 1333970250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 6600861 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 3595 # Transaction distribution
system.membus.trans_dist::ReadResp 3595 # Transaction distribution
system.membus.trans_dist::ReadExReq 1719 # Transaction distribution
system.membus.trans_dist::ReadExResp 1719 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10628 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 10628 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340096 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 340096 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 340096 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 6107000 # Layer occupancy (ticks)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340096 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 340096 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 5314 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 5314 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 5314 # Request fanout histogram
+system.membus.reqLayer0.occupancy 6106500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 49715750 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 49715250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 11407320 # Number of BP lookups
+system.cpu.branchPred.lookups 11407319 # Number of BP lookups
system.cpu.branchPred.condPredicted 8177175 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 788662 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 6672694 # Number of BTB lookups
system.cpu.branchPred.BTBHits 5348459 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 80.154417 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1172953 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.usedRAS 1172952 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.data_misses 47245 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 27017239 # DTB accesses
-system.cpu.itb.fetch_hits 22956162 # ITB hits
+system.cpu.itb.fetch_hits 22956157 # ITB hits
system.cpu.itb.fetch_misses 88 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 22956250 # ITB accesses
+system.cpu.itb.fetch_accesses 22956245 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 91903089 # Number of instructions committed
system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 2250216 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 2250214 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.121246 # CPI: cycles per instruction
system.cpu.ipc 0.891865 # IPC: instructions per cycle
-system.cpu.tickCycles 100852685 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 2193262 # Total number of cycles that the object has spent stopped
+system.cpu.tickCycles 100852672 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 2193275 # Total number of cycles that the object has spent stopped
system.cpu.icache.tags.replacements 13697 # number of replacements
-system.cpu.icache.tags.tagsinuse 1640.300457 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 22940501 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 1640.302767 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 22940496 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 15661 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 1464.817125 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 1464.816806 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1640.300457 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.800928 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.800928 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 1640.302767 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.800929 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.800929 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 45927985 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 45927985 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 22940501 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 22940501 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 22940501 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 22940501 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 22940501 # number of overall hits
-system.cpu.icache.overall_hits::total 22940501 # number of overall hits
+system.cpu.icache.tags.tag_accesses 45927975 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 45927975 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 22940496 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 22940496 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 22940496 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 22940496 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 22940496 # number of overall hits
+system.cpu.icache.overall_hits::total 22940496 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 15661 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 15661 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 15661 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 15661 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 15661 # number of overall misses
system.cpu.icache.overall_misses::total 15661 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 385791500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 385791500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 385791500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 385791500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 385791500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 385791500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 22956162 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 22956162 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 22956162 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 22956162 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 22956162 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 22956162 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 386976750 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 386976750 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 386976750 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 386976750 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 386976750 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 386976750 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 22956157 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 22956157 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 22956157 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 22956157 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 22956157 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 22956157 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000682 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000682 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000682 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000682 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000682 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000682 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24633.899496 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 24633.899496 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 24633.899496 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 24633.899496 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 24633.899496 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 24633.899496 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24709.581125 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 24709.581125 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 24709.581125 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 24709.581125 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 24709.581125 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 24709.581125 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 15661 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 15661 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 15661 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353105500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 353105500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353105500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 353105500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353105500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 353105500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 354287250 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 354287250 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 354287250 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 354287250 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 354287250 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 354287250 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000682 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000682 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000682 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22546.804163 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22546.804163 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22546.804163 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 22546.804163 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22546.804163 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 22546.804163 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22622.262308 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22622.262308 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22622.262308 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 22622.262308 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22622.262308 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 22622.262308 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 22356474 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 16146 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 16146 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31322 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4567 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 35889 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1002304 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 1151872 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 1151872 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1002304 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 1151872 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 17998 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 17998 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 17998 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 9106000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 24173500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 24175250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3734250 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 3734000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 2477.580697 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 2477.584038 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 12565 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 3661 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 3.432122 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 17.790277 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 2459.790419 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 2459.793761 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075067 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.075610 # Average percentage of cache occupancy
system.cpu.l2cache.demand_misses::total 5314 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 5314 # number of overall misses
system.cpu.l2cache.overall_misses::total 5314 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245013750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 245013750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 117202000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 117202000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 362215750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 362215750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 362215750 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 362215750 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 246128750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 246128750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 116497000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 116497000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 362625750 # number of demand (read+write) miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.inst 362625750 # number of overall miss cycles
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system.cpu.l2cache.ReadReq_accesses::cpu.inst 16146 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 16146 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.demand_miss_rate::total 0.297021 # miss rate for demand accesses
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system.cpu.l2cache.overall_miss_rate::total 0.297021 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68154.033380 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68154.033380 # average ReadReq miss latency
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-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68180.337405 # average ReadExReq miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::total 68162.542341 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68162.542341 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68162.542341 # average overall miss latency
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+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67770.215241 # average ReadExReq miss latency
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+system.cpu.l2cache.demand_avg_miss_latency::total 68239.697027 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68239.697027 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.demand_mshr_misses::total 5314 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.overall_mshr_misses::total 5314 # number of overall MSHR misses
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-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95648000 # number of ReadExReq MSHR miss cycles
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-system.cpu.l2cache.demand_mshr_miss_latency::total 295486750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 295486750 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 295486750 # number of overall MSHR miss cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::total 295895750 # number of demand (read+write) MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::total 295895750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.222656 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.222656 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.985100 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.297021 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.297021 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.297021 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55587.969402 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55587.969402 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55641.652123 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55641.652123 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55605.334964 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55605.334964 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55605.334964 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55605.334964 # average overall mshr miss latency
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55231.820826 # average ReadExReq mshr miss latency
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+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55682.301468 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55682.301468 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55682.301468 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 157 # number of replacements
-system.cpu.dcache.tags.tagsinuse 1448.553115 # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse 1448.555792 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26545428 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11903.779372 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.553115 # Average occupied blocks per requestor
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system.cpu.dcache.tags.occ_percent::cpu.inst 0.353651 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.353651 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id
system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.inst 3430 # number of overall misses
system.cpu.dcache.overall_misses::total 3430 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36876750 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 36876750 # number of ReadReq miss cycles
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-system.cpu.dcache.WriteReq_miss_latency::total 198611000 # number of WriteReq miss cycles
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-system.cpu.dcache.demand_miss_latency::total 235487750 # number of demand (read+write) miss cycles
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-system.cpu.dcache.overall_miss_latency::total 235487750 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.inst 20047755 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20047755 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.inst 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.inst 0.000129 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 71053.468208 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 71053.468208 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68227.756785 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 68227.756785 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 68655.320700 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 68655.320700 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 68655.320700 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 68655.320700 # average overall miss latency
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+system.cpu.dcache.ReadReq_avg_miss_latency::total 71394.990366 # average ReadReq miss latency
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+system.cpu.dcache.demand_avg_miss_latency::total 68234.693878 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 68234.693878 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 68234.693878 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.inst 2230 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses
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-system.cpu.dcache.ReadReq_mshr_miss_latency::total 33572250 # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.WriteReq_mshr_miss_latency::total 119207500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 152779750 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 152779750 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 152779750 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 152779750 # number of overall MSHR miss cycles
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+system.cpu.dcache.ReadReq_mshr_miss_latency::total 33506000 # number of ReadReq MSHR miss cycles
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+system.cpu.dcache.WriteReq_mshr_miss_latency::total 118502500 # number of WriteReq MSHR miss cycles
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+system.cpu.dcache.demand_mshr_miss_latency::total 152008500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 152008500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 152008500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000268 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 69221.134021 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69221.134021 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68313.753582 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68313.753582 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68511.098655 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68511.098655 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68511.098655 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68511.098655 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 69084.536082 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69084.536082 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67909.742120 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67909.742120 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68165.246637 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68165.246637 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68165.246637 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68165.246637 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 22159411000 # Number of ticks simulated
final_tick 22159411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 150496 # Simulator instruction rate (inst/s)
-host_op_rate 150496 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 39616568 # Simulator tick rate (ticks/s)
-host_mem_usage 240828 # Number of bytes of host memory used
-host_seconds 559.35 # Real time elapsed on the host
+host_inst_rate 217065 # Simulator instruction rate (inst/s)
+host_op_rate 217065 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 57140149 # Simulator tick rate (ticks/s)
+host_mem_usage 296848 # Number of bytes of host memory used
+host_seconds 387.81 # Real time elapsed on the host
sim_insts 84179709 # Number of instructions simulated
sim_ops 84179709 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bytesPerActivate::896-1023 46 5.31% 85.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 123 14.20% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 866 # Bytes accessed per row activation
-system.physmem.totQLat 40678250 # Total ticks spent queuing
-system.physmem.totMemAccLat 138778250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 41291750 # Total ticks spent queuing
+system.physmem.totMemAccLat 139391750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 26160000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 7774.89 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 7892.15 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 26524.89 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 26642.15 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 15.11 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 15.11 # Average system read bandwidth in MiByte/s
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 4235344.32 # Average gap between requests
system.physmem.pageHitRate 83.22 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 20544029500 # Time in different power states
+system.physmem.memoryStateTime::IDLE 20543925500 # Time in different power states
system.physmem.memoryStateTime::REF 739700000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 868593500 # Time in different power states
+system.physmem.memoryStateTime::ACT 868697500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 15110871 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 3523 # Transaction distribution
system.membus.trans_dist::ReadResp 3523 # Transaction distribution
system.membus.trans_dist::ReadExReq 1709 # Transaction distribution
system.membus.trans_dist::ReadExResp 1709 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10464 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 10464 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334848 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 334848 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 334848 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 6531000 # Layer occupancy (ticks)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334848 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 334848 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 5232 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 5232 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 5232 # Request fanout histogram
+system.membus.reqLayer0.occupancy 6530000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 48922250 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 48921000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 16298030 # Number of BP lookups
system.cpu.numCycles 44318823 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 16859425 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 16859440 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 139373095 # Number of instructions fetch has processed
system.cpu.fetch.Branches 16298030 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 9227373 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 26218432 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.Cycles 26218420 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2029202 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 113 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 2359 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 16127186 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 380559 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 44094959 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 44094962 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 3.160749 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.432020 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 19653194 44.57% 44.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 19653197 44.57% 44.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2660337 6.03% 50.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1339868 3.04% 53.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1948475 4.42% 58.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 44094959 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 44094962 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.367745 # Number of branch fetches per cycle
system.cpu.fetch.rate 3.144783 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 13063421 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 8246941 # Number of cycles decode is blocked
+system.cpu.decode.IdleCycles 13063436 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 8246929 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 19674377 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 2107337 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1002883 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 133445502 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 49010 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1002883 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 14206611 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 4728529 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 8933 # count of cycles rename stalled for serializing inst
+system.cpu.rename.IdleCycles 14206626 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 4728528 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 8922 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 20521133 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 3626870 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 129917938 # Number of instructions processed by rename
system.cpu.memDep0.conflictingStores 1618929 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 112639456 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1940 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 100102495 # Number of instructions issued
+system.cpu.iq.iqInstsIssued 100102500 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 120259 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 27967887 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 21886195 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined 21886191 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1551 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 44094959 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 44094962 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.270157 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.096378 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 11535003 26.16% 26.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 7754472 17.59% 43.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7555417 17.13% 60.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5737107 13.01% 73.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4489381 10.18% 84.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2977390 6.75% 90.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2013843 4.57% 95.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 11535006 26.16% 26.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 7754469 17.59% 43.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7555421 17.13% 60.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5737104 13.01% 73.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 4489383 10.18% 84.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2977389 6.75% 90.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 2013844 4.57% 95.39% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1160432 2.63% 98.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 871914 1.98% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 44094959 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 44094962 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 479018 20.14% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 60895265 60.83% 60.83% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 60895268 60.83% 60.83% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 491428 0.49% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2836761 2.83% 64.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.79% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 24980976 24.96% 92.74% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 24980978 24.96% 92.74% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 7264985 7.26% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 100102495 # Type of FU issued
+system.cpu.iq.FU_type_0::total 100102500 # Type of FU issued
system.cpu.iq.rate 2.258690 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2377986 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.023756 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 231175572 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 231175585 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 131029945 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 90008845 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_wakeup_accesses 90008848 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 15622622 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 9621224 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 7166740 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 94135365 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 94135370 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 8345109 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1908745 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 1908744 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 7109479 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 10719 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1002883 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 3707628 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 461880 # Number of cycles IEW is unblocking
+system.cpu.iew.iewUnblockCycles 461879 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 123638491 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 278104 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 27105677 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 8747640 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1940 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 39979 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 414958 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 414957 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 42241 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 554445 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 525545 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1079990 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 98729732 # Number of executed instructions
+system.cpu.iew.iewExecutedInsts 98729735 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 24378234 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1372763 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecSquashedInsts 1372765 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 10997095 # number of nop insts executed
system.cpu.iew.exec_refs 31540837 # number of memory reference insts executed
system.cpu.iew.exec_branches 12532490 # Number of branches executed
system.cpu.iew.exec_stores 7162603 # Number of stores executed
system.cpu.iew.exec_rate 2.227716 # Inst execution rate
-system.cpu.iew.wb_sent 97918366 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 97175585 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 67088116 # num instructions producing a value
-system.cpu.iew.wb_consumers 95122373 # num instructions consuming a value
+system.cpu.iew.wb_sent 97918369 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 97175588 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 67088119 # num instructions producing a value
+system.cpu.iew.wb_consumers 95122375 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.192648 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.705282 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 31736961 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 962705 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 39466883 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 39466886 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.328612 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.908948 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 14969501 37.93% 37.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 8597580 21.78% 59.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3898486 9.88% 69.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 1956471 4.96% 74.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1378247 3.49% 78.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1028776 2.61% 80.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 694004 1.76% 82.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 14969499 37.93% 37.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 8597582 21.78% 59.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3898491 9.88% 69.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 1956472 4.96% 74.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1378246 3.49% 78.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1028775 2.61% 80.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 694003 1.76% 82.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 732346 1.86% 84.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 6211472 15.74% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 39466883 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 39466886 # Number of insts commited each cycle
system.cpu.commit.committedInsts 91903055 # Number of instructions committed
system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction
system.cpu.commit.bw_lim_events 6211472 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 156894387 # The number of ROB reads
+system.cpu.rob.rob_reads 156894390 # The number of ROB reads
system.cpu.rob.rob_writes 251967276 # The number of ROB writes
-system.cpu.timesIdled 4538 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 223864 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.timesIdled 4539 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 223861 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 0.526479 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.526479 # CPI: Total CPI of All Threads
system.cpu.ipc 1.899412 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.899412 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 133358099 # number of integer regfile reads
-system.cpu.int_regfile_writes 73122879 # number of integer regfile writes
+system.cpu.int_regfile_reads 133358103 # number of integer regfile reads
+system.cpu.int_regfile_writes 73122882 # number of integer regfile writes
system.cpu.fp_regfile_reads 6250590 # number of floating regfile reads
system.cpu.fp_regfile_writes 6153622 # number of floating regfile writes
system.cpu.misc_regfile_reads 718773 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 40079044 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 12032 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 12032 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 110 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23038 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4606 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 27644 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737216 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150912 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 888128 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 888128 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737216 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150912 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 888128 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 13877 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 13877 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 13877 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 7048500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 17856750 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 17856500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3547750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.icache.tags.replacements 9583 # number of replacements
-system.cpu.icache.tags.tagsinuse 1600.631079 # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse 1600.631019 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 16112652 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 11519 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1398.789131 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1600.631079 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst 1600.631019 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.781558 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.781558 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id
system.cpu.icache.demand_misses::total 14533 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 14533 # number of overall misses
system.cpu.icache.overall_misses::total 14533 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 419582750 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 419582750 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 419582750 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 419582750 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 419582750 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 419582750 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 419606250 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 419606250 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 419606250 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 419606250 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 419606250 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 419606250 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 16127185 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 16127185 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 16127185 # number of demand (read+write) accesses
system.cpu.icache.demand_miss_rate::total 0.000901 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000901 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000901 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28871.034886 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 28871.034886 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 28871.034886 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 28871.034886 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 28871.034886 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 28871.034886 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28872.651896 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 28872.651896 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 28872.651896 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 28872.651896 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 28872.651896 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 28872.651896 # average overall miss latency
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system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001287 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62851.825168 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 62851.825168 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62586.326682 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 62586.326682 # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62851.967370 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 62851.967370 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62574.685468 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 62574.685468 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 62615.697981 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 62615.697981 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 62615.697981 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 62615.697981 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 62605.389798 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 62605.389798 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 62605.389798 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 62605.389798 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 29209 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 416 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 894 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 110 # number of writebacks
system.cpu.dcache.writebacks::total 110 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 528 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 528 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6635 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 6635 # number of WriteReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 529 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 529 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 7163 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 7163 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 7163 # number of overall MSHR hits
system.cpu.dcache.demand_mshr_misses::total 2247 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2247 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2247 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36170500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 36170500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125701245 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 125701245 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36161000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 36161000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125695745 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 125695745 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161871745 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 161871745 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161871745 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 161871745 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161856745 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 161856745 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161856745 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 161856745 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70507.797271 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70507.797271 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72492.067474 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72492.067474 # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70489.278752 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70489.278752 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72488.895617 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72488.895617 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72039.049844 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 72039.049844 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72039.049844 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 72039.049844 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72032.374277 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 72032.374277 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72032.374277 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 72032.374277 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 45951567500 # Number of ticks simulated
final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3319618 # Simulator instruction rate (inst/s)
-host_op_rate 3319616 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1659808736 # Simulator tick rate (ticks/s)
-host_mem_usage 259284 # Number of bytes of host memory used
-host_seconds 27.68 # Real time elapsed on the host
+host_inst_rate 2845952 # Simulator instruction rate (inst/s)
+host_op_rate 2845951 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1422976169 # Simulator tick rate (ticks/s)
+host_mem_usage 283520 # Number of bytes of host memory used
+host_seconds 32.29 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7999995996 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3030549393 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11030545389 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 11030545389 # Throughput (bytes/s)
-system.membus.data_through_bus 506870851 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 111899287 # Transaction distribution
+system.membus.trans_dist::ReadResp 111899287 # Transaction distribution
+system.membus.trans_dist::WriteReq 6501103 # Transaction distribution
+system.membus.trans_dist::WriteResp 6501103 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 183806178 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 52994602 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 236800780 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 367612356 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 139258495 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 506870851 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 118400390 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.776206 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.416786 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 26497301 22.38% 22.38% # Request fanout histogram
+system.membus.snoop_fanout::1 91903089 77.62% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 118400390 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
sim_ticks 118729316000 # Number of ticks simulated
final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1742639 # Simulator instruction rate (inst/s)
-host_op_rate 1742639 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2251309988 # Simulator tick rate (ticks/s)
-host_mem_usage 268020 # Number of bytes of host memory used
-host_seconds 52.74 # Real time elapsed on the host
+host_inst_rate 1660785 # Simulator instruction rate (inst/s)
+host_op_rate 1660785 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2145562848 # Simulator tick rate (ticks/s)
+host_mem_usage 293264 # Number of bytes of host memory used
+host_seconds 55.34 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 2568532 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 3043 # Transaction distribution
system.membus.trans_dist::ReadResp 3043 # Transaction distribution
system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 304960 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 4765 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 4765 # Request fanout histogram
system.membus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 42885000 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 5843207 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 8985 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17020 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4553 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 21573 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 544640 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 693760 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 693760 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 544640 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 693760 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 10840 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 10840 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 10840 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 5527000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 12765000 # Layer occupancy (ticks)
sim_ticks 131652469500 # Number of ticks simulated
final_tick 131652469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 235317 # Simulator instruction rate (inst/s)
-host_op_rate 248063 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 179784828 # Simulator tick rate (ticks/s)
-host_mem_usage 321352 # Number of bytes of host memory used
-host_seconds 732.28 # Real time elapsed on the host
+host_inst_rate 246188 # Simulator instruction rate (inst/s)
+host_op_rate 259522 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 188090070 # Simulator tick rate (ticks/s)
+host_mem_usage 311300 # Number of bytes of host memory used
+host_seconds 699.94 # Real time elapsed on the host
sim_insts 172317809 # Number of instructions simulated
sim_ops 181650742 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 3617 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 240 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 241 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 903 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 272.372093 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 179.073064 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 280.203163 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 262 29.01% 29.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 352 38.98% 68.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 86 9.52% 77.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 48 5.32% 82.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 35 3.88% 86.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 23 2.55% 89.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 17 1.88% 91.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 16 1.77% 92.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 64 7.09% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 903 # Bytes accessed per row activation
-system.physmem.totQLat 27589000 # Total ticks spent queuing
-system.physmem.totMemAccLat 100132750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples 904 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 272.070796 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 178.793599 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 280.048713 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 264 29.20% 29.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 351 38.83% 68.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 86 9.51% 77.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 48 5.31% 82.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 35 3.87% 86.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 23 2.54% 89.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 17 1.88% 91.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 16 1.77% 92.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 64 7.08% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 904 # Bytes accessed per row activation
+system.physmem.totQLat 27698500 # Total ticks spent queuing
+system.physmem.totMemAccLat 100242250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 7130.78 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 7159.09 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 25880.78 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 25909.09 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
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system.membus.trans_dist::ReadResp 2779 # Transaction distribution
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55640.737410 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57143.119266 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57143.119266 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56063.888889 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56063.888889 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56063.888889 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56063.888889 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 42 # number of replacements
-system.cpu.dcache.tags.tagsinuse 1376.810162 # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse 1376.810186 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40745471 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1809 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 22523.754008 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst 1376.810162 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.inst 1376.810186 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.inst 0.336135 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.336135 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 1767 # Occupied blocks per task id
system.cpu.dcache.overall_misses::total 2411 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 52005983 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 52005983 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115778750 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 115778750 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst 167784733 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 167784733 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst 167784733 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 167784733 # number of overall miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115743750 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 115743750 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst 167749733 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 167749733 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst 167749733 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 167749733 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.inst 28338781 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 28338781 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.inst 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 67804.410691 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 67804.410691 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70425.030414 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 70425.030414 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69591.345085 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 69591.345085 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69591.345085 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 69591.345085 # average overall miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70403.740876 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 70403.740876 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69576.828287 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 69576.828287 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69576.828287 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 69576.828287 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.overall_mshr_misses::total 1809 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 47475265 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 47475265 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77144500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 77144500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 124619765 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 124619765 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 124619765 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 124619765 # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77131500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 77131500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 124606765 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 124606765 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 124606765 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 124606765 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000089 # mshr miss rate for WriteReq accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66772.524613 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66772.524613 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70259.107468 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70259.107468 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68888.758983 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68888.758983 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68888.758983 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68888.758983 # average overall mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70247.267760 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70247.267760 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68881.572692 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68881.572692 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68881.572692 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68881.572692 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.071387 # Number of seconds simulated
-sim_ticks 71387376000 # Number of ticks simulated
-final_tick 71387376000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.084956 # Number of seconds simulated
+sim_ticks 84955935500 # Number of ticks simulated
+final_tick 84955935500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 91858 # Simulator instruction rate (inst/s)
-host_op_rate 96834 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 38058123 # Simulator tick rate (ticks/s)
-host_mem_usage 257304 # Number of bytes of host memory used
-host_seconds 1875.75 # Real time elapsed on the host
+host_inst_rate 135379 # Simulator instruction rate (inst/s)
+host_op_rate 142711 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 66749907 # Simulator tick rate (ticks/s)
+host_mem_usage 309000 # Number of bytes of host memory used
+host_seconds 1272.75 # Real time elapsed on the host
sim_insts 172303021 # Number of instructions simulated
sim_ops 181635953 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 130496 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 111040 # Number of bytes read from this memory
-system.physmem.bytes_read::total 241536 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 130496 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 130496 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 2039 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1735 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 3774 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1827998 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1555457 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3383455 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1827998 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1827998 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1827998 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1555457 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3383455 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 3774 # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst 18240 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 35328 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher 268480 # Number of bytes read from this memory
+system.physmem.bytes_read::total 322048 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 18240 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 18240 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 285 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 552 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher 4195 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 5032 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 214700 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 415839 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher 3160227 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3790765 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 214700 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 214700 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 214700 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 415839 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher 3160227 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3790765 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 5032 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 3774 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 5032 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 241536 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 322048 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 241536 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 322048 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 60 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 313 # Per bank write bursts
-system.physmem.perBankRdBursts::1 214 # Per bank write bursts
-system.physmem.perBankRdBursts::2 128 # Per bank write bursts
-system.physmem.perBankRdBursts::3 306 # Per bank write bursts
-system.physmem.perBankRdBursts::4 297 # Per bank write bursts
-system.physmem.perBankRdBursts::5 299 # Per bank write bursts
-system.physmem.perBankRdBursts::6 265 # Per bank write bursts
-system.physmem.perBankRdBursts::7 217 # Per bank write bursts
-system.physmem.perBankRdBursts::8 243 # Per bank write bursts
-system.physmem.perBankRdBursts::9 220 # Per bank write bursts
-system.physmem.perBankRdBursts::10 282 # Per bank write bursts
-system.physmem.perBankRdBursts::11 189 # Per bank write bursts
-system.physmem.perBankRdBursts::12 184 # Per bank write bursts
-system.physmem.perBankRdBursts::13 208 # Per bank write bursts
-system.physmem.perBankRdBursts::14 212 # Per bank write bursts
-system.physmem.perBankRdBursts::15 197 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 395 # Per bank write bursts
+system.physmem.perBankRdBursts::1 288 # Per bank write bursts
+system.physmem.perBankRdBursts::2 188 # Per bank write bursts
+system.physmem.perBankRdBursts::3 388 # Per bank write bursts
+system.physmem.perBankRdBursts::4 399 # Per bank write bursts
+system.physmem.perBankRdBursts::5 367 # Per bank write bursts
+system.physmem.perBankRdBursts::6 381 # Per bank write bursts
+system.physmem.perBankRdBursts::7 279 # Per bank write bursts
+system.physmem.perBankRdBursts::8 314 # Per bank write bursts
+system.physmem.perBankRdBursts::9 341 # Per bank write bursts
+system.physmem.perBankRdBursts::10 369 # Per bank write bursts
+system.physmem.perBankRdBursts::11 260 # Per bank write bursts
+system.physmem.perBankRdBursts::12 244 # Per bank write bursts
+system.physmem.perBankRdBursts::13 279 # Per bank write bursts
+system.physmem.perBankRdBursts::14 295 # Per bank write bursts
+system.physmem.perBankRdBursts::15 245 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 71387262500 # Total gap between requests
+system.physmem.totGap 84955621000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 3774 # Read request sizes (log2)
+system.physmem.readPktSize::6 5032 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 2817 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 790 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 125 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 1408 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 968 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 484 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 397 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 338 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 315 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 293 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 271 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 257 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 115 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 65 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 62 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 23 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 13 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 730 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 328.591781 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 199.502533 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 324.063907 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 243 33.29% 33.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 162 22.19% 55.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 95 13.01% 68.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 41 5.62% 74.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 34 4.66% 78.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 29 3.97% 82.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 36 4.93% 87.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 21 2.88% 90.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 69 9.45% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 730 # Bytes accessed per row activation
-system.physmem.totQLat 27328250 # Total ticks spent queuing
-system.physmem.totMemAccLat 98090750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 18870000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 7241.19 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 689 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 467.413643 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 304.114713 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 362.347713 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 143 20.75% 20.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 123 17.85% 38.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 63 9.14% 47.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 69 10.01% 57.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 45 6.53% 64.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 51 7.40% 71.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 42 6.10% 77.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 21 3.05% 80.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 132 19.16% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 689 # Bytes accessed per row activation
+system.physmem.totQLat 114920157 # Total ticks spent queuing
+system.physmem.totMemAccLat 209270157 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 25160000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 22837.87 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 25991.19 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 3.38 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 41587.87 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 3.79 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 3.38 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 3.79 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.97 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 3037 # Number of row buffer hits during reads
+system.physmem.readRowHits 4343 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 86.31 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 18915543.85 # Average gap between requests
-system.physmem.pageHitRate 80.47 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 68189011250 # Time in different power states
-system.physmem.memoryStateTime::REF 2383680000 # Time in different power states
+system.physmem.avgGap 16883072.54 # Average gap between requests
+system.physmem.pageHitRate 86.31 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 81214099250 # Time in different power states
+system.physmem.memoryStateTime::REF 2836600000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 812104750 # Time in different power states
+system.physmem.memoryStateTime::ACT 905088250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 3383455 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 2699 # Transaction distribution
-system.membus.trans_dist::ReadResp 2699 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 60 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 60 # Transaction distribution
-system.membus.trans_dist::ReadExReq 1075 # Transaction distribution
-system.membus.trans_dist::ReadExResp 1075 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7668 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 7668 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 241536 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 241536 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 241536 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 4574500 # Layer occupancy (ticks)
+system.membus.trans_dist::ReadReq 4821 # Transaction distribution
+system.membus.trans_dist::ReadResp 4821 # Transaction distribution
+system.membus.trans_dist::ReadExReq 211 # Transaction distribution
+system.membus.trans_dist::ReadExResp 211 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10064 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 10064 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 322048 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 322048 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 5032 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 5032 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 5032 # Request fanout histogram
+system.membus.reqLayer0.occupancy 5681641 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 35380947 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 46027985 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 106458293 # Number of BP lookups
-system.cpu.branchPred.condPredicted 82706448 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 6339444 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 50217715 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 48291708 # Number of BTB hits
+system.cpu.branchPred.lookups 85925623 # Number of BP lookups
+system.cpu.branchPred.condPredicted 68405598 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 6015157 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 40113883 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 39024614 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 96.164686 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 5164625 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 84625 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 97.284559 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 3701789 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 81904 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
-system.cpu.numCycles 142774753 # number of cpu cycles simulated
+system.cpu.numCycles 169911872 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 44808389 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 429802861 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 106458293 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 53456333 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 91468493 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 12731388 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 5563 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 99 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 41753796 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1912042 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 142648266 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 3.160575 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.133574 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 5595281 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 349266175 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 85925623 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 42726403 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 158254745 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 12044332 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 129 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingQuiesceStallCycles 37 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 592 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 78952832 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 17522 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 169872950 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.151005 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.046766 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 53718645 37.66% 37.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 6357410 4.46% 42.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 10351894 7.26% 49.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 14920250 10.46% 59.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 10655390 7.47% 67.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 3891108 2.73% 70.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 7883355 5.53% 75.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 9310317 6.53% 82.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 25559897 17.92% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 17324644 10.20% 10.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 30203623 17.78% 27.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 31840188 18.74% 46.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 90504495 53.28% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 142648266 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.745638 # Number of branch fetches per cycle
-system.cpu.fetch.rate 3.010356 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 37233141 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 23853545 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 68602562 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 6747325 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 6211693 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 15955000 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 160395 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 420485829 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 828178 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 6211693 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 42171212 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 18551410 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 713419 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 69222818 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5777714 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 398176302 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 59 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1614739 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 2816561 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 62575 # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents 202 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 691997012 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1704697725 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 425662370 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 3491733 # Number of floating rename lookups
+system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 169872950 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.505707 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.055573 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 17551129 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 17096204 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 122646615 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 6731659 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 5847343 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 11137012 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 190128 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 306601093 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 27639828 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 5847343 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 37738327 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 8403981 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 578579 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 108919553 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 8385167 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 278647204 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 13415116 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 3048397 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 841923 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 2187656 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 31854 # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents 78402 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 483062515 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1196895890 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 297562467 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 3006395 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 399020083 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 28576 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 28600 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 15636023 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 44518617 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 18120521 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 7204434 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 5193927 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 353303303 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 50659 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 249217571 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 532732 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 170449002 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 473050896 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 5443 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 142648266 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.747077 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.881809 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 190085586 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 23528 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 23420 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 13351603 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 34138378 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 14478835 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 2550837 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1806189 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 264810642 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 45850 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 214907655 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 5190996 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 82629036 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 219889900 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 634 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 169872950 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.265108 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.017484 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 54008982 37.86% 37.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 21782256 15.27% 53.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 24530872 17.20% 70.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 16106640 11.29% 81.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 11858342 8.31% 89.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 6781839 4.75% 94.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 5090438 3.57% 98.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1742716 1.22% 99.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 746181 0.52% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 52803027 31.08% 31.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 36096104 21.25% 52.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 65778237 38.72% 91.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 13576092 7.99% 99.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 1571163 0.92% 99.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 47813 0.03% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 514 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 142648266 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 169872950 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 1599616 44.61% 44.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 5629 0.16% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 43 0.00% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 26 0.00% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 44.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 2425 0.07% 44.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 44.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 44.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1462989 40.80% 85.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 515010 14.36% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 35609099 66.11% 66.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 152890 0.28% 66.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 66.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 66.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 66.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 66.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 1075 0.00% 66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 35725 0.07% 66.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 330 0.00% 66.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 815 0.00% 66.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 34388 0.06% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 217 0.00% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 14076935 26.13% 92.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 3950981 7.34% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 192832828 77.38% 77.38% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1041370 0.42% 77.79% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 77.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 77.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 77.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 77.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 77.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 77.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 77.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 77.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 77.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 77.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 77.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 77.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 77.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 77.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 77.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 77.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 77.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 77.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 33133 0.01% 77.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 77.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 164691 0.07% 77.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 264054 0.11% 77.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 76936 0.03% 78.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 473853 0.19% 78.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 207040 0.08% 78.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 72084 0.03% 78.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 323 0.00% 78.31% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 39374798 15.80% 94.11% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 14676461 5.89% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 167347451 77.87% 77.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 918969 0.43% 78.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 33024 0.02% 78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 165192 0.08% 78.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 245769 0.11% 78.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 460683 0.21% 78.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 206710 0.10% 78.85% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 71622 0.03% 78.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.88% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 32005523 14.89% 93.78% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 13376375 6.22% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 249217571 # Type of FU issued
-system.cpu.iq.rate 1.745530 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 3585738 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.014388 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 641399049 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 521384383 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 237201307 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 3802829 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 2450137 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 1875104 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 250898873 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 1904436 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1999527 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 214907655 # Type of FU issued
+system.cpu.iq.rate 1.264818 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 53862656 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.250632 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 654786826 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 345480396 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 204601887 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 3955086 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 2012108 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 1806636 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 266634716 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 2135595 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1601086 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 16622473 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 18079 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 32569 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 5475887 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 6242234 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 7548 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 7115 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1834201 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 334532 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 126 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 25938 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 647 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 6211693 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 18514097 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 29892 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 353371291 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 723756 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 44518617 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 18120521 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 28251 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 2286 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 27735 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 32569 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 3999566 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 3827175 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 7826741 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 243157329 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 37609930 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 6060242 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 5847343 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 5682283 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 37485 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 264872462 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 34138378 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 14478835 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 23442 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 3828 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 30448 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 7115 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 3233466 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 3245683 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 6479149 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 207525838 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 30720478 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 7381817 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 17329 # number of nop insts executed
-system.cpu.iew.exec_refs 51859202 # number of memory reference insts executed
-system.cpu.iew.exec_branches 55857945 # Number of branches executed
-system.cpu.iew.exec_stores 14249272 # Number of stores executed
-system.cpu.iew.exec_rate 1.703084 # Inst execution rate
-system.cpu.iew.wb_sent 240511751 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 239076411 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 145760285 # num instructions producing a value
-system.cpu.iew.wb_consumers 269855272 # num instructions consuming a value
+system.cpu.iew.exec_nop 15970 # number of nop insts executed
+system.cpu.iew.exec_refs 43862877 # number of memory reference insts executed
+system.cpu.iew.exec_branches 44936358 # Number of branches executed
+system.cpu.iew.exec_stores 13142399 # Number of stores executed
+system.cpu.iew.exec_rate 1.221373 # Inst execution rate
+system.cpu.iew.wb_sent 206743657 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 206408523 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 129467920 # num instructions producing a value
+system.cpu.iew.wb_consumers 221670950 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.674501 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.540142 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.214798 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.584055 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 171723245 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 69532618 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 6185443 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 117932320 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.540293 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.243745 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 5840334 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 158431709 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.146553 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.646732 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 51372616 43.56% 43.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 31468321 26.68% 70.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 11935963 10.12% 80.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 6951478 5.89% 86.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 3813624 3.23% 89.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1418078 1.20% 90.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1525333 1.29% 91.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1616480 1.37% 93.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 7830427 6.64% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 73650115 46.49% 46.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 41279051 26.05% 72.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 22553954 14.24% 86.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 9627262 6.08% 92.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 3547678 2.24% 95.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 2148088 1.36% 96.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1282361 0.81% 97.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 989322 0.62% 97.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 3353878 2.12% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 117932320 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 158431709 # Number of insts commited each cycle
system.cpu.commit.committedInsts 172317409 # Number of instructions committed
system.cpu.commit.committedOps 181650341 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 181650341 # Class of committed instruction
-system.cpu.commit.bw_lim_events 7830427 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 3353878 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 463470278 # The number of ROB reads
-system.cpu.rob.rob_writes 731648814 # The number of ROB writes
-system.cpu.timesIdled 1645 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 126487 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 406255589 # The number of ROB reads
+system.cpu.rob.rob_writes 513821131 # The number of ROB writes
+system.cpu.timesIdled 2630 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 38922 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 172303021 # Number of Instructions Simulated
system.cpu.committedOps 181635953 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.828626 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.828626 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.206817 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.206817 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 248213314 # number of integer regfile reads
-system.cpu.int_regfile_writes 133191535 # number of integer regfile writes
-system.cpu.fp_regfile_reads 2934311 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2552498 # number of floating regfile writes
-system.cpu.cc_regfile_reads 830988511 # number of cc regfile reads
-system.cpu.cc_regfile_writes 255127381 # number of cc regfile writes
-system.cpu.misc_regfile_reads 66039150 # number of misc regfile reads
+system.cpu.cpi 0.986122 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.986122 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.014073 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.014073 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 218958563 # number of integer regfile reads
+system.cpu.int_regfile_writes 114511116 # number of integer regfile writes
+system.cpu.fp_regfile_reads 2904510 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2441819 # number of floating regfile writes
+system.cpu.cc_regfile_reads 709580018 # number of cc regfile reads
+system.cpu.cc_regfile_writes 229533397 # number of cc regfile writes
+system.cpu.misc_regfile_reads 59318521 # number of misc regfile reads
system.cpu.misc_regfile_writes 820036 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 5345035 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 4859 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 4858 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 17 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 61 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 61 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1087 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1087 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8146 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3823 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 11969 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 258688 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 118976 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 377664 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 377664 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 3904 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 3029000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 6522997 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3106540 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.icache.tags.replacements 2317 # number of replacements
-system.cpu.icache.tags.tagsinuse 1337.456920 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 41747829 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 4039 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 10336.179500 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1337.456920 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.653055 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.653055 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 1722 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 528 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 30 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 1033 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.840820 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 83511695 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 83511695 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 41748272 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 41748272 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 41748272 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 41748272 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 41748272 # number of overall hits
-system.cpu.icache.overall_hits::total 41748272 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 5524 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 5524 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 5524 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 5524 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 5524 # number of overall misses
-system.cpu.icache.overall_misses::total 5524 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 227823494 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 227823494 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 227823494 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 227823494 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 227823494 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 227823494 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 41753796 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 41753796 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total 41753796 # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total 41753796 # number of overall (read+write) accesses
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-system.cpu.icache.ReadReq_miss_rate::total 0.000132 # miss rate for ReadReq accesses
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-system.cpu.icache.demand_miss_rate::total 0.000132 # miss rate for demand accesses
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-system.cpu.icache.overall_miss_rate::total 0.000132 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41242.486242 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 41242.486242 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 41242.486242 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 41242.486242 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 41242.486242 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 41242.486242 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 857 # number of cycles access was blocked
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+system.cpu.toL2Bus.trans_dist::HardPFReq 7801 # Transaction distribution
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+system.cpu.toL2Bus.pkt_size::total 12362816 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 7801 # Total snoops (count)
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+system.cpu.toL2Bus.snoop_fanout::6 7801 3.88% 100.00% # Request fanout histogram
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+system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 200978 # Request fanout histogram
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+system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 82370974 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 110177995 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.cpu.icache.tags.replacements 54375 # number of replacements
+system.cpu.icache.tags.tagsinuse 510.661166 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 78896017 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 54887 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 1437.426294 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 84218922500 # Cycle when the warmup percentage was hit.
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+system.cpu.icache.tags.occ_percent::total 0.997385 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 251 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 157960533 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 157960533 # Number of data accesses
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+system.cpu.icache.ReadReq_misses::total 56806 # number of ReadReq misses
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+system.cpu.icache.overall_misses::total 56806 # number of overall misses
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+system.cpu.icache.overall_miss_latency::total 474677200 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 78952823 # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.ReadReq_avg_miss_latency::total 8356.110270 # average ReadReq miss latency
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+system.cpu.icache.demand_avg_miss_latency::total 8356.110270 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 8356.110270 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 8356.110270 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 16306 # number of cycles access was blocked
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-system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 2267 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 47.611111 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 7.192766 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1420 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 1420 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 1420 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 1420 # number of demand (read+write) MSHR hits
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-system.cpu.icache.overall_mshr_hits::total 1420 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4104 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 4104 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 4104 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 4104 # number of demand (read+write) MSHR misses
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-system.cpu.icache.overall_mshr_misses::total 4104 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 164891501 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 164891501 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 164891501 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 164891501 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 164891501 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 164891501 # number of overall MSHR miss cycles
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-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000098 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000098 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000098 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40178.240984 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40178.240984 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40178.240984 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 40178.240984 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40178.240984 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 40178.240984 # average overall mshr miss latency
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+system.cpu.icache.ReadReq_mshr_hits::total 1919 # number of ReadReq MSHR hits
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+system.cpu.icache.demand_mshr_miss_latency::total 380604754 # number of demand (read+write) MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::total 380604754 # number of overall MSHR miss cycles
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+system.cpu.icache.demand_avg_mshr_miss_latency::total 6934.333339 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6934.333339 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 6934.333339 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 3068 # number of hwpf that were already in mshr
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+system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 3291 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 894 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 5385 # number of hwpf issued
+system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 26500 # number of hwpf spanning a virtual page
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system.cpu.l2cache.tags.replacements 0 # number of replacements
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.dcache.tags.tagsinuse 1395.016190 # Cycle average of tags in use
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 61937.425335 # average ReadReq miss latency
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-system.cpu.dcache.overall_avg_miss_latency::total 63809.038387 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 848 # number of cycles access was blocked
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+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011693 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.002708 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.002708 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.002711 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.002711 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9250.665091 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 9250.665091 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9879.315248 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 9879.315248 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8881.679389 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8881.679389 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 9377.207964 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 9377.207964 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 9367.045018 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 9367.045018 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 279 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 7362 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 531 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 93 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 13.864407 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 17 # number of writebacks
-system.cpu.dcache.writebacks::total 17 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1189 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 1189 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6701 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 6701 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 7890 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 7890 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 7890 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 7890 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 753 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 753 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1146 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1146 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1899 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1899 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1903 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1903 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48859513 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 48859513 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 76658945 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 76658945 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 305000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 305000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 125518458 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 125518458 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 125823458 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 125823458 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000093 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000093 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007260 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007260 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64886.471448 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64886.471448 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66892.622164 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66892.622164 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 76250 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 76250 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66097.134281 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 66097.134281 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66118.475039 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 66118.475039 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 64873 # number of writebacks
+system.cpu.dcache.writebacks::total 64873 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24343 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 24343 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 13890 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 13890 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 262 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 262 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 38233 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 38233 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 38233 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 38233 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64732 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 64732 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8559 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 8559 # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 118 # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total 118 # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 73291 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 73291 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 73409 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 73409 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 483955005 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 483955005 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 74150498 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 74150498 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1036250 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1036250 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 558105503 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 558105503 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 559141753 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 559141753 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002246 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002246 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.244813 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.244813 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001780 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001783 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.001783 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7476.286921 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7476.286921 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8663.453441 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8663.453441 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8781.779661 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8781.779661 # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7614.925475 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 7614.925475 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7616.801114 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 7616.801114 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 99596491000 # Number of ticks simulated
final_tick 99596491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1821315 # Simulator instruction rate (inst/s)
-host_op_rate 1919960 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1052688537 # Simulator tick rate (ticks/s)
-host_mem_usage 309564 # Number of bytes of host memory used
-host_seconds 94.61 # Real time elapsed on the host
+host_inst_rate 2060285 # Simulator instruction rate (inst/s)
+host_op_rate 2171872 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1190808654 # Simulator tick rate (ticks/s)
+host_mem_usage 300012 # Number of bytes of host memory used
+host_seconds 83.64 # Real time elapsed on the host
sim_insts 172317409 # Number of instructions simulated
sim_ops 181650341 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7625170288 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1564177607 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9189347896 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 9189347896 # Throughput (bytes/s)
-system.membus.data_through_bus 915226805 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 217614902 # Transaction distribution
+system.membus.trans_dist::ReadResp 217637309 # Transaction distribution
+system.membus.trans_dist::WriteReq 12364287 # Transaction distribution
+system.membus.trans_dist::WriteResp 12364287 # Transaction distribution
+system.membus.trans_dist::SoftPFReq 463 # Transaction distribution
+system.membus.trans_dist::SoftPFResp 463 # Transaction distribution
+system.membus.trans_dist::LoadLockedReq 22407 # Transaction distribution
+system.membus.trans_dist::StoreCondReq 22407 # Transaction distribution
+system.membus.trans_dist::StoreCondResp 22407 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720102 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 80328830 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 460048932 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440204 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 915226805 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 230024466 # Request fanout histogram
+system.membus.snoop_fanout::mean 4.825391 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::4 40164415 17.46% 17.46% # Request fanout histogram
+system.membus.snoop_fanout::5 189860051 82.54% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 4 # Request fanout histogram
+system.membus.snoop_fanout::max_value 5 # Request fanout histogram
+system.membus.snoop_fanout::total 230024466 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
sim_ticks 230173357000 # Number of ticks simulated
final_tick 230173357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1246866 # Simulator instruction rate (inst/s)
-host_op_rate 1314511 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1670106565 # Simulator tick rate (ticks/s)
-host_mem_usage 319316 # Number of bytes of host memory used
-host_seconds 137.82 # Real time elapsed on the host
+host_inst_rate 1215411 # Simulator instruction rate (inst/s)
+host_op_rate 1281349 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1627973861 # Simulator tick rate (ticks/s)
+host_mem_usage 309492 # Number of bytes of host memory used
+host_seconds 141.39 # Real time elapsed on the host
sim_insts 171842483 # Number of instructions simulated
sim_ops 181165370 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 480751 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 479360 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 960111 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 960111 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 2361 # Transaction distribution
system.membus.trans_dist::ReadResp 2361 # Transaction distribution
system.membus.trans_dist::ReadExReq 1092 # Transaction distribution
system.membus.trans_dist::ReadExResp 1092 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 220992 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 3453 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 3453 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 3453 # Request fanout histogram
system.membus.reqLayer0.occupancy 3596000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 31220000 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51503.912800 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51503.912800 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 1350217 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6102 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3594 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 9696 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 195264 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 310784 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 195264 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 4856 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 4856 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 4856 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks)
sim_ticks 96722945000 # Number of ticks simulated
final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2358558 # Simulator instruction rate (inst/s)
-host_op_rate 2358560 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1179286883 # Simulator tick rate (ticks/s)
-host_mem_usage 269756 # Number of bytes of host memory used
-host_seconds 82.02 # Real time elapsed on the host
+host_inst_rate 2119754 # Simulator instruction rate (inst/s)
+host_op_rate 2119756 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1059884256 # Simulator tick rate (ticks/s)
+host_mem_usage 284956 # Number of bytes of host memory used
+host_seconds 91.26 # Real time elapsed on the host
sim_insts 193444518 # Number of instructions simulated
sim_ops 193444756 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3055415910 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11055401229 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 11057254439 # Throughput (bytes/s)
-system.membus.data_through_bus 1069490213 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 251180603 # Transaction distribution
+system.membus.trans_dist::ReadResp 251180603 # Transaction distribution
+system.membus.trans_dist::WriteReq 18976439 # Transaction distribution
+system.membus.trans_dist::WriteResp 18976439 # Transaction distribution
+system.membus.trans_dist::SwapReq 22406 # Transaction distribution
+system.membus.trans_dist::SwapResp 22406 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 386891070 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 153467826 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 540358896 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 773782140 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 295708073 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1069490213 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 270179448 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.715989 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.450942 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 76733913 28.40% 28.40% # Request fanout histogram
+system.membus.snoop_fanout::1 193445535 71.60% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 270179448 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 401 # Number of system calls
system.cpu.numCycles 193445891 # number of cpu cycles simulated
sim_ticks 270563082000 # Number of ticks simulated
final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1069922 # Simulator instruction rate (inst/s)
-host_op_rate 1069924 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1496457293 # Simulator tick rate (ticks/s)
-host_mem_usage 278484 # Number of bytes of host memory used
-host_seconds 180.80 # Real time elapsed on the host
+host_inst_rate 1449498 # Simulator instruction rate (inst/s)
+host_op_rate 1449499 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2027353723 # Simulator tick rate (ticks/s)
+host_mem_usage 294428 # Number of bytes of host memory used
+host_seconds 133.46 # Real time elapsed on the host
sim_insts 193444518 # Number of instructions simulated
sim_ops 193444756 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 1223641 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 4095 # Transaction distribution
system.membus.trans_dist::ReadResp 4095 # Transaction distribution
system.membus.trans_dist::ReadExReq 1078 # Transaction distribution
system.membus.trans_dist::ReadExResp 1078 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 331072 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 5173 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 5173 # Request fanout histogram
system.membus.reqLayer0.occupancy 5173000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 46557000 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 3279915 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 12786 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24576 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 27730 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 786432 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 887424 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 786432 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 13866 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 13866 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 13866 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 6935000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks)
---------- Begin Simulation Statistics ----------
-sim_seconds 0.148587 # Number of seconds simulated
-sim_ticks 148587085500 # Number of ticks simulated
-final_tick 148587085500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.148694 # Number of seconds simulated
+sim_ticks 148694012000 # Number of ticks simulated
+final_tick 148694012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 101386 # Simulator instruction rate (inst/s)
-host_op_rate 169932 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 114064202 # Simulator tick rate (ticks/s)
-host_mem_usage 285092 # Number of bytes of host memory used
-host_seconds 1302.66 # Real time elapsed on the host
+host_inst_rate 84654 # Simulator instruction rate (inst/s)
+host_op_rate 141888 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 95308980 # Simulator tick rate (ticks/s)
+host_mem_usage 341916 # Number of bytes of host memory used
+host_seconds 1560.13 # Real time elapsed on the host
sim_insts 132071192 # Number of instructions simulated
sim_ops 221363384 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 225472 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 125440 # Number of bytes read from this memory
-system.physmem.bytes_read::total 350912 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 225472 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 225472 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3523 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1960 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 5483 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1517440 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 844219 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2361659 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1517440 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1517440 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1517440 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 844219 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2361659 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 5483 # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst 223936 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 125888 # Number of bytes read from this memory
+system.physmem.bytes_read::total 349824 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 223936 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 223936 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 3499 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1967 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 5466 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1506019 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 846625 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2352643 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1506019 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1506019 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1506019 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 846625 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2352643 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 5466 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 5483 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 5466 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 350912 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 349824 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 350912 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 349824 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 350 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 310 # Per bank write bursts
-system.physmem.perBankRdBursts::1 352 # Per bank write bursts
-system.physmem.perBankRdBursts::2 465 # Per bank write bursts
-system.physmem.perBankRdBursts::3 360 # Per bank write bursts
-system.physmem.perBankRdBursts::4 334 # Per bank write bursts
-system.physmem.perBankRdBursts::5 328 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 296 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 294 # Per bank write bursts
+system.physmem.perBankRdBursts::1 361 # Per bank write bursts
+system.physmem.perBankRdBursts::2 463 # Per bank write bursts
+system.physmem.perBankRdBursts::3 372 # Per bank write bursts
+system.physmem.perBankRdBursts::4 337 # Per bank write bursts
+system.physmem.perBankRdBursts::5 332 # Per bank write bursts
system.physmem.perBankRdBursts::6 400 # Per bank write bursts
-system.physmem.perBankRdBursts::7 386 # Per bank write bursts
+system.physmem.perBankRdBursts::7 384 # Per bank write bursts
system.physmem.perBankRdBursts::8 341 # Per bank write bursts
-system.physmem.perBankRdBursts::9 281 # Per bank write bursts
-system.physmem.perBankRdBursts::10 278 # Per bank write bursts
-system.physmem.perBankRdBursts::11 258 # Per bank write bursts
-system.physmem.perBankRdBursts::12 226 # Per bank write bursts
-system.physmem.perBankRdBursts::13 469 # Per bank write bursts
-system.physmem.perBankRdBursts::14 405 # Per bank write bursts
-system.physmem.perBankRdBursts::15 290 # Per bank write bursts
+system.physmem.perBankRdBursts::9 282 # Per bank write bursts
+system.physmem.perBankRdBursts::10 235 # Per bank write bursts
+system.physmem.perBankRdBursts::11 262 # Per bank write bursts
+system.physmem.perBankRdBursts::12 222 # Per bank write bursts
+system.physmem.perBankRdBursts::13 508 # Per bank write bursts
+system.physmem.perBankRdBursts::14 392 # Per bank write bursts
+system.physmem.perBankRdBursts::15 281 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 148587005000 # Total gap between requests
+system.physmem.totGap 148693969000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 5483 # Read request sizes (log2)
+system.physmem.readPktSize::6 5466 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 4379 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 915 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 165 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 4370 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 896 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 174 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1137 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 307.616535 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 177.186204 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 330.211340 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 456 40.11% 40.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 252 22.16% 62.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 97 8.53% 70.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 50 4.40% 75.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 53 4.66% 79.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 61 5.36% 85.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 21 1.85% 87.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 17 1.50% 88.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 130 11.43% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1137 # Bytes accessed per row activation
-system.physmem.totQLat 38062500 # Total ticks spent queuing
-system.physmem.totMemAccLat 140868750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 27415000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 6941.91 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 1125 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 309.532444 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 178.678629 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 328.994757 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 454 40.36% 40.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 235 20.89% 61.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 101 8.98% 70.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 52 4.62% 74.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 60 5.33% 80.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 59 5.24% 85.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 19 1.69% 87.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 20 1.78% 88.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 125 11.11% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1125 # Bytes accessed per row activation
+system.physmem.totQLat 38946250 # Total ticks spent queuing
+system.physmem.totMemAccLat 141433750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 27330000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 7125.18 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 25691.91 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 25875.18 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2.35 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 2.36 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2.35 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 4339 # Number of row buffer hits during reads
+system.physmem.readRowHits 4331 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 79.14 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 79.24 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 27099581.43 # Average gap between requests
-system.physmem.pageHitRate 79.14 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 141978840750 # Time in different power states
-system.physmem.memoryStateTime::REF 4961580000 # Time in different power states
+system.physmem.avgGap 27203433.77 # Average gap between requests
+system.physmem.pageHitRate 79.24 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 142073657250 # Time in different power states
+system.physmem.memoryStateTime::REF 4964960000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 1644861750 # Time in different power states
+system.physmem.memoryStateTime::ACT 1647900000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 2361659 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 3951 # Transaction distribution
-system.membus.trans_dist::ReadResp 3951 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 350 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 350 # Transaction distribution
-system.membus.trans_dist::ReadExReq 1532 # Transaction distribution
-system.membus.trans_dist::ReadExResp 1532 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11666 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11666 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 11666 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 350912 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 350912 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 350912 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 350912 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 7101000 # Layer occupancy (ticks)
+system.membus.trans_dist::ReadReq 3933 # Transaction distribution
+system.membus.trans_dist::ReadResp 3932 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 296 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 296 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1533 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1533 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11523 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11523 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 11523 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 349760 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 349760 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 349760 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 5762 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 5762 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 5762 # Request fanout histogram
+system.membus.reqLayer0.occupancy 7167000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 51987900 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 51861454 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 22396239 # Number of BP lookups
-system.cpu.branchPred.condPredicted 22396239 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1554538 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 14104442 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 13258278 # Number of BTB hits
+system.cpu.branchPred.lookups 22382097 # Number of BP lookups
+system.cpu.branchPred.condPredicted 22382097 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1553409 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 14143770 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 13239374 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 94.000727 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1524438 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 22257 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 93.605694 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1523861 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 22060 # Number of incorrect RAS predictions.
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 400 # Number of system calls
-system.cpu.numCycles 297174180 # number of cpu cycles simulated
+system.cpu.numCycles 297388032 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 27916282 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 249227309 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 22396239 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 14782716 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 267173177 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 3706948 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 35 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 5683 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 49787 # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles 27880008 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 249058784 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 22382097 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 14763235 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 267434691 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 3695048 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 15 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 4561 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 42381 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 26681234 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 258392 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 296998563 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.383031 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.791258 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles 113 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 26649696 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 257275 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 297209306 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.380725 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.789359 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 228914394 77.08% 77.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 5078121 1.71% 78.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 4142401 1.39% 80.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 4790312 1.61% 81.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 4897925 1.65% 83.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 5093198 1.71% 85.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 5344969 1.80% 86.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 4001055 1.35% 88.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 34736188 11.70% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 229177022 77.11% 77.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 5084587 1.71% 78.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 4138437 1.39% 80.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 4791887 1.61% 81.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 4876855 1.64% 83.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 5109175 1.72% 85.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 5334492 1.79% 86.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 4008000 1.35% 88.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 34688851 11.67% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 296998563 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.075364 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.838657 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 16354452 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 230786837 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 26168548 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 21835252 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1853474 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 359377278 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 1853474 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 24140537 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 162592213 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 34818 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 38296584 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 70080937 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 350637562 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 41127 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 61846506 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 7943239 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 152837 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 405833434 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 972943751 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 642292546 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 4668888 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 297209306 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.075262 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.837488 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 16317003 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 231094890 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 26094955 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 21854934 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1847524 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 359064274 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 1847524 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 24114798 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 162761005 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 33475 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 38241804 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 70210700 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 350324590 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 42142 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 61992199 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 7946895 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 152925 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 405428411 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 972465740 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 641794462 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 4665474 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 146403984 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2369 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2300 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 128426201 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 89689525 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 32027647 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 63947531 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 21534219 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 341381240 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 5216 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 266882213 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 74332 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 119621882 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 250682367 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 3971 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 296998563 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.898598 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.365381 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 145998961 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2154 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2076 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 128653734 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 89733483 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 32018253 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 63985001 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 21567740 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 341091248 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 4877 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 266696686 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 73290 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 119329162 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 250439001 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 3632 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 297209306 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.897336 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.363195 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 171353571 57.70% 57.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 54179431 18.24% 75.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 33564937 11.30% 87.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 19156299 6.45% 93.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 10836839 3.65% 97.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 4376133 1.47% 98.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2240693 0.75% 99.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 893448 0.30% 99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 397212 0.13% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 171484109 57.70% 57.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 54269493 18.26% 75.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 33638460 11.32% 87.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 19147986 6.44% 93.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 10817239 3.64% 97.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 4351297 1.46% 98.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 2217356 0.75% 99.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 890190 0.30% 99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 393176 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 296998563 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 297209306 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 240121 7.41% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 2588686 79.93% 87.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 410086 12.66% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 237582 7.35% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 2582537 79.93% 87.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 410926 12.72% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 1211280 0.45% 0.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 167297217 62.69% 63.14% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 790659 0.30% 63.44% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 7035808 2.64% 66.07% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 1214833 0.46% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 66531787 24.93% 91.46% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 22800629 8.54% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 1211351 0.45% 0.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 167148119 62.67% 63.13% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 789126 0.30% 63.42% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 7035938 2.64% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 1214032 0.46% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 66518900 24.94% 91.46% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 22779220 8.54% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 266882213 # Type of FU issued
-system.cpu.iq.rate 0.898067 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 3238893 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.012136 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 829077263 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 457002634 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 260953197 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 4998951 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 4330787 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 2399211 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 266394178 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 2515648 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 18924906 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 266696686 # Type of FU issued
+system.cpu.iq.rate 0.896797 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 3231045 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.012115 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 828907957 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 456425026 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 260744620 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 4999056 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 4321531 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 2398079 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 266200144 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 2516236 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 18853700 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 33039938 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 13805 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 330906 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 11511930 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 33083896 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 14048 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 327034 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 11502536 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 51585 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads 52807 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1853474 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 126194753 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 5535533 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 341386456 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 110817 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 89689525 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 32027647 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 2236 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 2225894 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 376853 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 330906 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 685400 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 928719 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1614119 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 264771892 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 65665679 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2110321 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 1847524 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 126225383 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 5553775 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 341096125 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 111900 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 89733483 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 32018253 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 2073 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 2221761 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 397558 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 327034 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 687554 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 924641 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1612195 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 264577830 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 65651803 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2118856 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 88263450 # number of memory reference insts executed
-system.cpu.iew.exec_branches 14588563 # Number of branches executed
-system.cpu.iew.exec_stores 22597771 # Number of stores executed
-system.cpu.iew.exec_rate 0.890965 # Inst execution rate
-system.cpu.iew.wb_sent 264070010 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 263352408 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 208938306 # num instructions producing a value
-system.cpu.iew.wb_consumers 376948521 # num instructions consuming a value
+system.cpu.iew.exec_refs 88227876 # number of memory reference insts executed
+system.cpu.iew.exec_branches 14574542 # Number of branches executed
+system.cpu.iew.exec_stores 22576073 # Number of stores executed
+system.cpu.iew.exec_rate 0.889672 # Inst execution rate
+system.cpu.iew.wb_sent 263857804 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 263142699 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 208771445 # num instructions producing a value
+system.cpu.iew.wb_consumers 376756650 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.886189 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.554289 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.884846 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.554128 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 120072652 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 119784082 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1559859 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 280678389 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.788673 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.596070 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1557714 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 280934179 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.787955 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.593006 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 180909203 64.45% 64.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 57692004 20.55% 85.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 14189338 5.06% 90.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 11904368 4.24% 94.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 4187159 1.49% 95.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 2885597 1.03% 96.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 913299 0.33% 97.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1056183 0.38% 97.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 6941238 2.47% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 181002456 64.43% 64.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 57799506 20.57% 85.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 14236358 5.07% 90.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 11930779 4.25% 94.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 4218902 1.50% 95.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 2886432 1.03% 96.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 918195 0.33% 97.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 1050521 0.37% 97.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 6891030 2.45% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 280678389 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 280934179 # Number of insts commited each cycle
system.cpu.commit.committedInsts 132071192 # Number of instructions committed
system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction
-system.cpu.commit.bw_lim_events 6941238 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 6891030 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 615173187 # The number of ROB reads
-system.cpu.rob.rob_writes 699236981 # The number of ROB writes
-system.cpu.timesIdled 3132 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 175617 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 615190615 # The number of ROB reads
+system.cpu.rob.rob_writes 698614568 # The number of ROB writes
+system.cpu.timesIdled 3122 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 178726 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 132071192 # Number of Instructions Simulated
system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 2.250106 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.250106 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.444424 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.444424 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 456530694 # number of integer regfile reads
-system.cpu.int_regfile_writes 239288826 # number of integer regfile writes
-system.cpu.fp_regfile_reads 3276715 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2059644 # number of floating regfile writes
-system.cpu.cc_regfile_reads 102986535 # number of cc regfile reads
-system.cpu.cc_regfile_writes 60205049 # number of cc regfile writes
-system.cpu.misc_regfile_reads 136896298 # number of misc regfile reads
+system.cpu.cpi 2.251725 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.251725 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.444104 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.444104 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 456361988 # number of integer regfile reads
+system.cpu.int_regfile_writes 239113538 # number of integer regfile writes
+system.cpu.fp_regfile_reads 3275482 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2058196 # number of floating regfile writes
+system.cpu.cc_regfile_reads 102983282 # number of cc regfile reads
+system.cpu.cc_regfile_writes 60177632 # number of cc regfile writes
+system.cpu.misc_regfile_reads 136798826 # number of misc regfile reads
system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 4492019 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 8845 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 8844 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 38 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 353 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 353 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1547 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1547 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16361 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4810 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 21171 # Packet count per connected master and slave (bytes)
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+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996749 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996749 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.439643 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.977634 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.548180 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.439643 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.977634 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.548180 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56229.214286 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63407.258065 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57021.098119 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.685811 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.685811 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54695.205479 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54695.205479 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56229.214286 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56617.437722 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56368.895189 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56229.214286 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56617.437722 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56368.895189 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 91 # number of replacements
-system.cpu.dcache.tags.tagsinuse 1449.080763 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 67091510 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2033 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 33001.234629 # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements 52 # number of replacements
+system.cpu.dcache.tags.tagsinuse 1451.665096 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 67147234 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 2012 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 33373.376740 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 1449.080763 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.353779 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.353779 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 1942 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 432 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.474121 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 134190055 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 134190055 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 46577118 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 46577118 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 20513830 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 20513830 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 67090948 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 67090948 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 67090948 # number of overall hits
-system.cpu.dcache.overall_hits::total 67090948 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1162 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1162 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1901 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1901 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 3063 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3063 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3063 # number of overall misses
-system.cpu.dcache.overall_misses::total 3063 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 64753959 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 64753959 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 117721350 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 117721350 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 182475309 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 182475309 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 182475309 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 182475309 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 46578280 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 46578280 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.occ_blocks::cpu.data 1451.665096 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.354410 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.354410 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 1960 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 434 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4 1416 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.478516 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 134301424 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 134301424 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 46632911 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 46632911 # number of ReadReq hits
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+system.cpu.dcache.demand_hits::total 67146804 # number of demand (read+write) hits
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+system.cpu.dcache.overall_hits::total 67146804 # number of overall hits
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+system.cpu.dcache.ReadReq_misses::total 1064 # number of ReadReq misses
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+system.cpu.dcache.demand_misses::total 2902 # number of demand (read+write) misses
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+system.cpu.dcache.overall_misses::total 2902 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 63689380 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 63689380 # number of ReadReq miss cycles
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+system.cpu.dcache.WriteReq_miss_latency::total 116173296 # number of WriteReq miss cycles
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+system.cpu.dcache.overall_miss_latency::total 179862676 # number of overall miss cycles
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system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 67094011 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 67094011 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 67094011 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 67094011 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000093 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000093 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000046 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000046 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000046 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000046 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55726.298623 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55726.298623 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61926.012625 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61926.012625 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 59574.047992 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 59574.047992 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 59574.047992 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 59574.047992 # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data 67149706 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 67149706 # number of demand (read+write) accesses
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+system.cpu.dcache.overall_accesses::total 67149706 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000090 # miss rate for WriteReq accesses
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+system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
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+system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59858.439850 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 59858.439850 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63206.363439 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 63206.363439 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 61978.868367 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 61978.868367 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 61978.868367 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 61978.868367 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 303 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 50 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 38 # number of writebacks
-system.cpu.dcache.writebacks::total 38 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 676 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 676 # number of ReadReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 10 # number of writebacks
+system.cpu.dcache.writebacks::total 10 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 590 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 590 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 677 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 677 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 677 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 677 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 486 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 486 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1900 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1900 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2386 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2386 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2386 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2386 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33826250 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 33826250 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 113234400 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 113234400 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 147060650 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 147060650 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 147060650 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 147060650 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data 591 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 591 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 591 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 591 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 474 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 474 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1837 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1837 # number of WriteReq MSHR misses
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+system.cpu.dcache.demand_mshr_misses::total 2311 # number of demand (read+write) MSHR misses
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+system.cpu.dcache.overall_mshr_misses::total 2311 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33789250 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 33789250 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 111812454 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 111812454 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145601704 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 145601704 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 145601704 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 145601704 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000093 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000093 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000036 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000036 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000036 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000036 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69601.337449 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69601.337449 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59597.052632 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59597.052632 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61634.807209 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 61634.807209 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61634.807209 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 61634.807209 # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000090 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000090 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71285.337553 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71285.337553 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60866.877518 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60866.877518 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63003.766335 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 63003.766335 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63003.766335 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 63003.766335 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 131393279000 # Number of ticks simulated
final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1131336 # Simulator instruction rate (inst/s)
-host_op_rate 1896222 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1125528252 # Simulator tick rate (ticks/s)
-host_mem_usage 303676 # Number of bytes of host memory used
-host_seconds 116.74 # Real time elapsed on the host
+host_inst_rate 1264426 # Simulator instruction rate (inst/s)
+host_op_rate 2119294 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1257935779 # Simulator tick rate (ticks/s)
+host_mem_usage 324376 # Number of bytes of host memory used
+host_seconds 104.45 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221363385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 10563363260 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3122274945 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13685638205 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 13685638205 # Throughput (bytes/s)
-system.membus.data_through_bus 1798200879 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 230176372 # Transaction distribution
+system.membus.trans_dist::ReadResp 230176372 # Transaction distribution
+system.membus.trans_dist::WriteReq 20515731 # Transaction distribution
+system.membus.trans_dist::WriteResp 20515731 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::total 346988734 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::total 154395472 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 501384206 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::total 1387954936 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::total 410245943 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1798200879 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 250692103 # Request fanout histogram
+system.membus.snoop_fanout::mean 2.692062 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.461641 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::2 77197736 30.79% 30.79% # Request fanout histogram
+system.membus.snoop_fanout::3 173494367 69.21% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 2 # Request fanout histogram
+system.membus.snoop_fanout::max_value 3 # Request fanout histogram
+system.membus.snoop_fanout::total 250692103 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 400 # Number of system calls
sim_ticks 250953957000 # Number of ticks simulated
final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 652190 # Simulator instruction rate (inst/s)
-host_op_rate 1093130 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1239252699 # Simulator tick rate (ticks/s)
-host_mem_usage 313428 # Number of bytes of host memory used
-host_seconds 202.50 # Real time elapsed on the host
+host_inst_rate 881800 # Simulator instruction rate (inst/s)
+host_op_rate 1477977 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1675544377 # Simulator tick rate (ticks/s)
+host_mem_usage 333860 # Number of bytes of host memory used
+host_seconds 149.77 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221363385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 1207552 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 3160 # Transaction distribution
system.membus.trans_dist::ReadResp 3160 # Transaction distribution
system.membus.trans_dist::ReadExReq 1575 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 303040 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 4735 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 4735 # Request fanout histogram
system.membus.reqLayer0.occupancy 4753500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 42633500 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 1684707 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 5021 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9388 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3817 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 13205 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300416 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 422784 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300416 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 6606 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 6606 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 6606 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks)
---------- Begin Simulation Statistics ----------
-sim_seconds 1.870335 # Number of seconds simulated
-sim_ticks 1870335131500 # Number of ticks simulated
-final_tick 1870335131500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.869358 # Number of seconds simulated
+sim_ticks 1869357988000 # Number of ticks simulated
+final_tick 1869357988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1824221 # Simulator instruction rate (inst/s)
-host_op_rate 1824220 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 54024573563 # Simulator tick rate (ticks/s)
-host_mem_usage 318368 # Number of bytes of host memory used
-host_seconds 34.62 # Real time elapsed on the host
-sim_insts 63154606 # Number of instructions simulated
-sim_ops 63154606 # Number of ops (including micro ops) simulated
+host_inst_rate 2868261 # Simulator instruction rate (inst/s)
+host_op_rate 2868259 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 82489350498 # Simulator tick rate (ticks/s)
+host_mem_usage 370556 # Number of bytes of host memory used
+host_seconds 22.66 # Real time elapsed on the host
+sim_insts 64999904 # Number of instructions simulated
+sim_ops 64999904 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst 761088 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 66705472 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 765760 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 66552064 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 674112 # Number of bytes read from this memory
-system.physmem.bytes_read::total 68252608 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 761088 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 110976 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 872064 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 5204096 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst 106560 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 771648 # Number of bytes read from this memory
+system.physmem.bytes_read::total 68196992 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 765760 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 106560 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 872320 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 5174080 # Number of bytes written to this memory
system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7863424 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 11892 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 1042273 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 7833408 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 11965 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 1039876 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 10533 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1066447 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 81314 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 1665 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 12057 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1065578 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 80845 # Number of write requests responded to by this memory
system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 122866 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 406926 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 35664984 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 513 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 360423 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 36492181 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 406926 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 466261 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2782440 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::tsunami.ide 1421846 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4204286 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2782440 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 406926 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 35664984 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1422359 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 360423 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 40696467 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 40739369 # Throughput (bytes/s)
-system.membus.data_through_bus 76196274 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.physmem.num_writes::total 122397 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 409638 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 35601562 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 57004 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 412788 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 36481505 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 409638 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 57004 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 466641 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2767838 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::tsunami.ide 1422589 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4190427 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2767838 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 409638 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 35601562 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1423102 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 57004 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 412788 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 40671931 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 948901 # Transaction distribution
+system.membus.trans_dist::ReadResp 948901 # Transaction distribution
+system.membus.trans_dist::WriteReq 14588 # Transaction distribution
+system.membus.trans_dist::WriteResp 14588 # Transaction distribution
+system.membus.trans_dist::Writeback 80845 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 19618 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 14179 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 8160 # Transaction distribution
+system.membus.trans_dist::ReadExReq 126515 # Transaction distribution
+system.membus.trans_dist::ReadExResp 124290 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2256153 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 2300227 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83462 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 83462 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 2383689 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73370112 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 73456274 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2670784 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2670784 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 76127058 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 1224161 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 1224161 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 1224161 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 1000624 # number of replacements
-system.l2c.tags.tagsinuse 65381.923240 # Cycle average of tags in use
-system.l2c.tags.total_refs 2464778 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 1065766 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 2.312682 # Average number of references to valid blocks.
+system.l2c.tags.replacements 999765 # number of replacements
+system.l2c.tags.tagsinuse 65320.982867 # Cycle average of tags in use
+system.l2c.tags.total_refs 2387620 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 1064815 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 2.242286 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 56158.686870 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 4894.230886 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 4134.623273 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 174.423683 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 19.958527 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.997649 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024 65142 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 769 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 3264 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 6912 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 6213 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 47984 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024 0.993988 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 32109770 # Number of tag accesses
-system.l2c.tags.data_accesses 32109770 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst 873092 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 763091 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 101902 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 36740 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1774825 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 816663 # number of Writeback hits
-system.l2c.Writeback_hits::total 816663 # number of Writeback hits
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system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 9154569 # DTB read hits
-system.cpu0.dtb.read_misses 7079 # DTB read misses
+system.cpu0.dtb.read_hits 7758808 # DTB read hits
+system.cpu0.dtb.read_misses 7155 # DTB read misses
system.cpu0.dtb.read_acv 152 # DTB read access violations
-system.cpu0.dtb.read_accesses 508987 # DTB read accesses
-system.cpu0.dtb.write_hits 5936918 # DTB write hits
-system.cpu0.dtb.write_misses 726 # DTB write misses
-system.cpu0.dtb.write_acv 99 # DTB write access violations
-system.cpu0.dtb.write_accesses 189050 # DTB write accesses
-system.cpu0.dtb.data_hits 15091487 # DTB hits
-system.cpu0.dtb.data_misses 7805 # DTB misses
-system.cpu0.dtb.data_acv 251 # DTB access violations
-system.cpu0.dtb.data_accesses 698037 # DTB accesses
-system.cpu0.itb.fetch_hits 3855534 # ITB hits
-system.cpu0.itb.fetch_misses 3485 # ITB misses
+system.cpu0.dtb.read_accesses 531148 # DTB read accesses
+system.cpu0.dtb.write_hits 4740251 # DTB write hits
+system.cpu0.dtb.write_misses 732 # DTB write misses
+system.cpu0.dtb.write_acv 102 # DTB write access violations
+system.cpu0.dtb.write_accesses 201714 # DTB write accesses
+system.cpu0.dtb.data_hits 12499059 # DTB hits
+system.cpu0.dtb.data_misses 7887 # DTB misses
+system.cpu0.dtb.data_acv 254 # DTB access violations
+system.cpu0.dtb.data_accesses 732862 # DTB accesses
+system.cpu0.itb.fetch_hits 3525726 # ITB hits
+system.cpu0.itb.fetch_misses 3572 # ITB misses
system.cpu0.itb.fetch_acv 127 # ITB acv
-system.cpu0.itb.fetch_accesses 3859019 # ITB accesses
+system.cpu0.itb.fetch_accesses 3529298 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 3740670264 # number of cpu cycles simulated
+system.cpu0.numCycles 3738722771 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 57222643 # Number of instructions committed
-system.cpu0.committedOps 57222643 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 53250480 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses
-system.cpu0.num_func_calls 1399593 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 6808341 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 53250480 # number of integer instructions
-system.cpu0.num_fp_insts 299810 # number of float instructions
-system.cpu0.num_int_register_reads 73319539 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 39827957 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written
-system.cpu0.num_mem_refs 15135573 # number of memory refs
-system.cpu0.num_load_insts 9184516 # Number of load instructions
-system.cpu0.num_store_insts 5951057 # Number of store instructions
-system.cpu0.num_idle_cycles 3683435851.584730 # Number of idle cycles
-system.cpu0.num_busy_cycles 57234412.415270 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.015301 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.984699 # Percentage of idle cycles
-system.cpu0.Branches 8650822 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 3102524 5.42% 5.42% # Class of executed instruction
-system.cpu0.op_class::IntAlu 37811313 66.07% 71.49% # Class of executed instruction
-system.cpu0.op_class::IntMult 59497 0.10% 71.59% # Class of executed instruction
-system.cpu0.op_class::IntDiv 0 0.00% 71.59% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 30844 0.05% 71.65% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 2221 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.65% # Class of executed instruction
-system.cpu0.op_class::MemRead 9401091 16.43% 88.08% # Class of executed instruction
-system.cpu0.op_class::MemWrite 5957003 10.41% 98.49% # Class of executed instruction
-system.cpu0.op_class::IprAccess 866206 1.51% 100.00% # Class of executed instruction
+system.cpu0.committedInsts 49477745 # Number of instructions committed
+system.cpu0.committedOps 49477745 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 46201705 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses
+system.cpu0.num_func_calls 1124633 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 6043603 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 46201705 # number of integer instructions
+system.cpu0.num_fp_insts 197598 # number of float instructions
+system.cpu0.num_int_register_reads 64003225 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 34834421 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written
+system.cpu0.num_mem_refs 12536107 # number of memory refs
+system.cpu0.num_load_insts 7783754 # Number of load instructions
+system.cpu0.num_store_insts 4752353 # Number of store instructions
+system.cpu0.num_idle_cycles 3689239788.666409 # Number of idle cycles
+system.cpu0.num_busy_cycles 49482982.333591 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles
+system.cpu0.Branches 7530826 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 2589816 5.23% 5.23% # Class of executed instruction
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+system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction
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system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 57230699 # Class of executed instruction
+system.cpu0.op_class::total 49485886 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 197118 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl
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-system.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1852989089000 99.07% 99.07% # number of cycles we spent at this ipl
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-system.cpu0.kern.ipl_ticks::31 17242731500 0.92% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1870334924000 # number of cycles we spent at this ipl
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+system.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl
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+system.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.684631 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.808762 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed
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+system.cpu0.kern.ipl_used::31 0.678828 # fraction of swpipl calls that actually changed the ipl
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system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed
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+system.cpu0.kern.syscall::total 228 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
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-system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed
-system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed
-system.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed
-system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed
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-system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed
-system.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed
-system.cpu0.kern.callpal::rdusp 7 0.00% 97.18% # number of callpals executed
-system.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed
-system.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed
-system.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed
-system.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 183289 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1156 # number of protection mode switches
+system.cpu0.kern.callpal::wripir 616 0.45% 0.45% # number of callpals executed
+system.cpu0.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed
+system.cpu0.kern.callpal::wrfen 1 0.00% 0.46% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.46% # number of callpals executed
+system.cpu0.kern.callpal::swpctx 2743 2.02% 2.47% # number of callpals executed
+system.cpu0.kern.callpal::tbi 39 0.03% 2.50% # number of callpals executed
+system.cpu0.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed
+system.cpu0.kern.callpal::swpipl 121668 89.51% 92.02% # number of callpals executed
+system.cpu0.kern.callpal::rdps 6149 4.52% 96.54% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp 1 0.00% 96.54% # number of callpals executed
+system.cpu0.kern.callpal::wrusp 3 0.00% 96.54% # number of callpals executed
+system.cpu0.kern.callpal::rdusp 7 0.01% 96.55% # number of callpals executed
+system.cpu0.kern.callpal::whami 2 0.00% 96.55% # number of callpals executed
+system.cpu0.kern.callpal::rti 4175 3.07% 99.62% # number of callpals executed
+system.cpu0.kern.callpal::callsys 369 0.27% 99.89% # number of callpals executed
+system.cpu0.kern.callpal::imb 146 0.11% 100.00% # number of callpals executed
+system.cpu0.kern.callpal::total 135929 # number of callpals executed
+system.cpu0.kern.mode_switch::kernel 6593 # number of protection mode switches
+system.cpu0.kern.mode_switch::user 1173 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
-system.cpu0.kern.mode_good::kernel 1155
-system.cpu0.kern.mode_good::user 1156
+system.cpu0.kern.mode_good::kernel 1172
+system.cpu0.kern.mode_good::user 1173
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.162883 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.177764 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.280223 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1869377924000 99.95% 99.95% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 956999000 0.05% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total 0.301957 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 1868349152500 99.95% 99.95% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 1008627000 0.05% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3763 # number of times the context was actually changed
+system.cpu0.kern.swap_context 2744 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.throughput 133353257 # Throughput (bytes/s)
-system.toL2Bus.data_through_bus 246745714 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 2669568 # Total snoop data (bytes)
-system.iobus.throughput 1460501 # Throughput (bytes/s)
-system.iobus.data_through_bus 2731626 # Total data (bytes)
-system.cpu0.icache.tags.replacements 884408 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.244752 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 56345695 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 884920 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 63.673208 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.244752 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.998525 # Average percentage of cache occupancy
+system.toL2Bus.trans_dist::ReadReq 2732156 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2732156 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 777631 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 19617 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 14229 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 33846 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 295242 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 295242 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1237878 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4301883 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 762376 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 627158 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 6929295 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39612096 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155765243 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24396032 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357911 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 243131282 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 41895 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 3873157 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 3.010774 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.103239 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 3831426 98.92% 98.92% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 41731 1.08% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3873157 # Request fanout histogram
+system.iobus.trans_dist::ReadReq 7628 # Transaction distribution
+system.iobus.trans_dist::ReadResp 7628 # Transaction distribution
+system.iobus.trans_dist::WriteReq 56140 # Transaction distribution
+system.iobus.trans_dist::WriteResp 14588 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14686 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18036 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 44074 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 127536 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 58744 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9018 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 86162 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2747818 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.icache.tags.replacements 618292 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 618804 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 78.969992 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 9786048500 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.240644 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998517 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 345 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 58115703 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 58115703 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 56345695 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 56345695 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 56345695 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 56345695 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 56345695 # number of overall hits
-system.cpu0.icache.overall_hits::total 56345695 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 885004 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 885004 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 885004 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 885004 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 885004 # number of overall misses
-system.cpu0.icache.overall_misses::total 885004 # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230699 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 57230699 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 57230699 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 57230699 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 57230699 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 57230699 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.015464 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.015464 # miss rate for overall accesses
+system.cpu0.icache.tags.tag_accesses 50104825 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 50104825 # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst 48866947 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 48866947 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 48866947 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 48866947 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 48866947 # number of overall hits
+system.cpu0.icache.overall_hits::total 48866947 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 618939 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 618939 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 618939 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 618939 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 618939 # number of overall misses
+system.cpu0.icache.overall_misses::total 618939 # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 49485886 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 49485886 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 49485886 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 49485886 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 49485886 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 49485886 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012507 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.012507 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012507 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.012507 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012507 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.012507 # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements 1978697 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 507.129647 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 13123800 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 1979209 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 6.630831 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements 1781371 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 506.187328 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 10705763 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 1781883 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 6.008118 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.129647 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.990488 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187328 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 446 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 62404315 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 62404315 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 7298365 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 7298365 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 5462282 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 5462282 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186624 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 186624 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 12760647 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 12760647 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 12760647 # number of overall hits
-system.cpu0.dcache.overall_hits::total 12760647 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 1683343 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 1683343 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 285998 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 285998 # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 714 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 1969341 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 1969341 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 1969341 # number of overall misses
-system.cpu0.dcache.overall_misses::total 1969341 # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981708 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 8981708 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748280 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 5748280 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 14729988 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 14729988 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 14729988 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 14729988 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187419 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.187419 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.049754 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085785 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085785 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003811 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003811 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133696 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.133696 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133696 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.133696 # miss rate for overall accesses
+system.cpu0.dcache.tags.tag_accesses 51822042 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 51822042 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 6068881 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 6068881 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 4360082 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 4360082 # number of WriteReq hits
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+system.cpu0.dcache.LoadLockedReq_hits::total 127592 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132846 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 132846 # number of StoreCondReq hits
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+system.cpu0.dcache.WriteReq_misses::total 236541 # number of WriteReq misses
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+system.cpu0.dcache.LoadLockedReq_misses::total 12626 # number of LoadLockedReq misses
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+system.cpu0.dcache.StoreCondReq_misses::total 6924 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 1796610 # number of demand (read+write) misses
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+system.cpu0.dcache.overall_misses::cpu0.data 1796610 # number of overall misses
+system.cpu0.dcache.overall_misses::total 1796610 # number of overall misses
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+system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596623 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 4596623 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 140218 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 140218 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 139770 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 139770 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 12225573 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 12225573 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 12225573 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 12225573 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.204493 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.204493 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051460 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.051460 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.090046 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090046 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049539 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049539 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.146955 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.146955 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.146955 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.146955 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 775643 # number of writebacks
-system.cpu0.dcache.writebacks::total 775643 # number of writebacks
+system.cpu0.dcache.writebacks::writebacks 633103 # number of writebacks
+system.cpu0.dcache.writebacks::total 633103 # number of writebacks
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 1163439 # DTB read hits
-system.cpu1.dtb.read_misses 3277 # DTB read misses
+system.cpu1.dtb.read_hits 2831559 # DTB read hits
+system.cpu1.dtb.read_misses 3191 # DTB read misses
system.cpu1.dtb.read_acv 58 # DTB read access violations
-system.cpu1.dtb.read_accesses 220342 # DTB read accesses
-system.cpu1.dtb.write_hits 751446 # DTB write hits
-system.cpu1.dtb.write_misses 415 # DTB write misses
-system.cpu1.dtb.write_acv 58 # DTB write access violations
-system.cpu1.dtb.write_accesses 103280 # DTB write accesses
-system.cpu1.dtb.data_hits 1914885 # DTB hits
-system.cpu1.dtb.data_misses 3692 # DTB misses
-system.cpu1.dtb.data_acv 116 # DTB access violations
-system.cpu1.dtb.data_accesses 323622 # DTB accesses
-system.cpu1.itb.fetch_hits 1468399 # ITB hits
-system.cpu1.itb.fetch_misses 1539 # ITB misses
+system.cpu1.dtb.read_accesses 198160 # DTB read accesses
+system.cpu1.dtb.write_hits 2101673 # DTB write hits
+system.cpu1.dtb.write_misses 412 # DTB write misses
+system.cpu1.dtb.write_acv 55 # DTB write access violations
+system.cpu1.dtb.write_accesses 90619 # DTB write accesses
+system.cpu1.dtb.data_hits 4933232 # DTB hits
+system.cpu1.dtb.data_misses 3603 # DTB misses
+system.cpu1.dtb.data_acv 113 # DTB access violations
+system.cpu1.dtb.data_accesses 288779 # DTB accesses
+system.cpu1.itb.fetch_hits 1950883 # ITB hits
+system.cpu1.itb.fetch_misses 1451 # ITB misses
system.cpu1.itb.fetch_acv 57 # ITB acv
-system.cpu1.itb.fetch_accesses 1469938 # ITB accesses
+system.cpu1.itb.fetch_accesses 1952334 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 3740248099 # number of cpu cycles simulated
+system.cpu1.numCycles 3738296587 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 5931963 # Number of instructions committed
-system.cpu1.committedOps 5931963 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 5550581 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses
-system.cpu1.num_func_calls 182742 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 577192 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 5550581 # number of integer instructions
-system.cpu1.num_fp_insts 28590 # number of float instructions
-system.cpu1.num_int_register_reads 7657293 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 4163277 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written
-system.cpu1.num_mem_refs 1926244 # number of memory refs
-system.cpu1.num_load_insts 1170888 # Number of load instructions
-system.cpu1.num_store_insts 755356 # Number of store instructions
-system.cpu1.num_idle_cycles 3734311403.078359 # Number of idle cycles
-system.cpu1.num_busy_cycles 5936695.921641 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles
-system.cpu1.Branches 836749 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 239814 4.04% 4.04% # Class of executed instruction
-system.cpu1.op_class::IntAlu 3533248 59.52% 63.56% # Class of executed instruction
-system.cpu1.op_class::IntMult 9651 0.16% 63.73% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 63.73% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 7388 0.12% 63.85% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 63.85% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 63.85% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 63.85% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 1421 0.02% 63.88% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 63.88% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 63.88% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 63.88% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 63.88% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 63.88% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 63.88% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 63.88% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 63.88% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 63.88% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 63.88% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.88% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 63.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 63.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 63.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.88% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.88% # Class of executed instruction
-system.cpu1.op_class::MemRead 1191429 20.07% 83.95% # Class of executed instruction
-system.cpu1.op_class::MemWrite 755540 12.73% 96.68% # Class of executed instruction
-system.cpu1.op_class::IprAccess 197280 3.32% 100.00% # Class of executed instruction
+system.cpu1.committedInsts 15522159 # Number of instructions committed
+system.cpu1.committedOps 15522159 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 14295544 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses
+system.cpu1.num_func_calls 493140 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 1540068 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 14295544 # number of integer instructions
+system.cpu1.num_fp_insts 198941 # number of float instructions
+system.cpu1.num_int_register_reads 19514289 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 10457600 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written
+system.cpu1.num_mem_refs 4961786 # number of memory refs
+system.cpu1.num_load_insts 2849090 # Number of load instructions
+system.cpu1.num_store_insts 2112696 # Number of store instructions
+system.cpu1.num_idle_cycles 3722773649.474793 # Number of idle cycles
+system.cpu1.num_busy_cycles 15522937.525207 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles
+system.cpu1.Branches 2214163 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction
+system.cpu1.op_class::IntAlu 9156766 58.98% 64.49% # Class of executed instruction
+system.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction
+system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 1409 0.01% 64.74% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction
+system.cpu1.op_class::MemRead 2937016 18.92% 83.66% # Class of executed instruction
+system.cpu1.op_class::MemWrite 2113897 13.62% 97.27% # Class of executed instruction
+system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 5935771 # Class of executed instruction
+system.cpu1.op_class::total 15525875 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2205 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1859122617500 99.41% 99.41% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1870124036000 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei 92290 # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0 31964 39.34% 39.34% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22 1906 2.35% 41.68% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30 616 0.76% 42.44% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31 46769 57.56% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total 81255 # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0 30935 48.51% 48.51% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0 1856123490500 99.30% 99.30% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 12870743500 0.69% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1869146928500 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed
-system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed
-system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed
-system.cpu1.kern.syscall::6 10 10.00% 25.00% # number of syscalls executed
-system.cpu1.kern.syscall::17 6 6.00% 31.00% # number of syscalls executed
-system.cpu1.kern.syscall::19 2 2.00% 33.00% # number of syscalls executed
-system.cpu1.kern.syscall::23 2 2.00% 35.00% # number of syscalls executed
-system.cpu1.kern.syscall::24 2 2.00% 37.00% # number of syscalls executed
-system.cpu1.kern.syscall::33 4 4.00% 41.00% # number of syscalls executed
-system.cpu1.kern.syscall::45 17 17.00% 58.00% # number of syscalls executed
-system.cpu1.kern.syscall::47 2 2.00% 60.00% # number of syscalls executed
-system.cpu1.kern.syscall::48 2 2.00% 62.00% # number of syscalls executed
-system.cpu1.kern.syscall::59 3 3.00% 65.00% # number of syscalls executed
-system.cpu1.kern.syscall::71 24 24.00% 89.00% # number of syscalls executed
-system.cpu1.kern.syscall::74 8 8.00% 97.00% # number of syscalls executed
-system.cpu1.kern.syscall::90 1 1.00% 98.00% # number of syscalls executed
-system.cpu1.kern.syscall::132 2 2.00% 100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total 100 # number of syscalls executed
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+system.cpu1.kern.syscall::2 2 2.04% 2.04% # number of syscalls executed
+system.cpu1.kern.syscall::3 10 10.20% 12.24% # number of syscalls executed
+system.cpu1.kern.syscall::4 2 2.04% 14.29% # number of syscalls executed
+system.cpu1.kern.syscall::6 10 10.20% 24.49% # number of syscalls executed
+system.cpu1.kern.syscall::17 6 6.12% 30.61% # number of syscalls executed
+system.cpu1.kern.syscall::19 2 2.04% 32.65% # number of syscalls executed
+system.cpu1.kern.syscall::23 2 2.04% 34.69% # number of syscalls executed
+system.cpu1.kern.syscall::24 2 2.04% 36.73% # number of syscalls executed
+system.cpu1.kern.syscall::33 4 4.08% 40.82% # number of syscalls executed
+system.cpu1.kern.syscall::45 17 17.35% 58.16% # number of syscalls executed
+system.cpu1.kern.syscall::47 2 2.04% 60.20% # number of syscalls executed
+system.cpu1.kern.syscall::48 2 2.04% 62.24% # number of syscalls executed
+system.cpu1.kern.syscall::59 2 2.04% 64.29% # number of syscalls executed
+system.cpu1.kern.syscall::71 24 24.49% 88.78% # number of syscalls executed
+system.cpu1.kern.syscall::74 8 8.16% 96.94% # number of syscalls executed
+system.cpu1.kern.syscall::90 1 1.02% 97.96% # number of syscalls executed
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system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir 8 0.02% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::swpctx 470 1.46% 1.50% # number of callpals executed
-system.cpu1.kern.callpal::tbi 15 0.05% 1.54% # number of callpals executed
-system.cpu1.kern.callpal::wrent 7 0.02% 1.57% # number of callpals executed
-system.cpu1.kern.callpal::swpipl 26238 81.66% 83.22% # number of callpals executed
-system.cpu1.kern.callpal::rdps 2576 8.02% 91.24% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp 1 0.00% 91.25% # number of callpals executed
-system.cpu1.kern.callpal::wrusp 4 0.01% 91.26% # number of callpals executed
-system.cpu1.kern.callpal::rdusp 2 0.01% 91.26% # number of callpals executed
-system.cpu1.kern.callpal::whami 3 0.01% 91.27% # number of callpals executed
-system.cpu1.kern.callpal::rti 2607 8.11% 99.39% # number of callpals executed
-system.cpu1.kern.callpal::callsys 158 0.49% 99.88% # number of callpals executed
-system.cpu1.kern.callpal::imb 38 0.12% 100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir 514 0.61% 0.61% # number of callpals executed
+system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed
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+system.cpu1.kern.callpal::swpctx 2506 2.96% 3.58% # number of callpals executed
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+system.cpu1.kern.callpal::swpipl 74617 88.26% 91.86% # number of callpals executed
+system.cpu1.kern.callpal::rdps 2575 3.05% 94.91% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp 1 0.00% 94.91% # number of callpals executed
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+system.cpu1.kern.callpal::rdusp 2 0.00% 94.91% # number of callpals executed
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+system.cpu1.kern.callpal::rti 4115 4.87% 99.79% # number of callpals executed
+system.cpu1.kern.callpal::callsys 146 0.17% 99.96% # number of callpals executed
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system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 32131 # number of callpals executed
-system.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches
-system.cpu1.kern.mode_switch::user 580 # number of protection mode switches
-system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches
-system.cpu1.kern.mode_good::kernel 612
-system.cpu1.kern.mode_good::user 580
-system.cpu1.kern.mode_good::idle 32
-system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches
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+system.cpu1.kern.mode_switch::user 564 # number of protection mode switches
+system.cpu1.kern.mode_switch::idle 3056 # number of protection mode switches
+system.cpu1.kern.mode_good::kernel 1106
+system.cpu1.kern.mode_good::user 564
+system.cpu1.kern.mode_good::idle 542
+system.cpu1.kern.mode_switch_good::kernel 0.434066 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 1373909000 0.07% 0.07% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1868002186500 99.90% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 471 # number of times the context was actually changed
-system.cpu1.icache.tags.replacements 103097 # number of replacements
-system.cpu1.icache.tags.tagsinuse 427.126315 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 5832135 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 103609 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 56.289849 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 1868932699000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 427.126315 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.834231 # Average percentage of cache occupancy
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+system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode
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+system.cpu1.kern.swap_context 2507 # number of times the context was actually changed
+system.cpu1.icache.tags.replacements 380647 # number of replacements
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+system.cpu1.icache.tags.sampled_refs 381159 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 39.733253 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 1859777157500 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133719 # Average occupied blocks per requestor
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system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id
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system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 6039407 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 6039407 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 5832135 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 5832135 # number of ReadReq hits
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system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu1.dcache.tags.tagsinuse 421.558473 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 1836050 # Total number of references to valid blocks.
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-system.cpu1.dcache.tags.warmup_cycle 1851115162500 # Cycle when the warmup percentage was hit.
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-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id
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-system.cpu1.dcache.tags.data_accesses 7735314 # Number of data accesses
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-system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses)
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+system.cpu1.dcache.StoreCondReq_misses::total 7305 # number of StoreCondReq misses
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+system.cpu1.dcache.ReadReq_accesses::total 2773573 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 2032960 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 2032960 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72098 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 72098 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 71515 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 71515 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 4806533 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 4806533 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 4806533 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 4806533 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050795 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.050795 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.038524 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.038524 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152570 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152570 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102146 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.102146 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.045605 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.045605 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.045605 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.045605 # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 41020 # number of writebacks
-system.cpu1.dcache.writebacks::total 41020 # number of writebacks
+system.cpu1.dcache.writebacks::writebacks 144528 # number of writebacks
+system.cpu1.dcache.writebacks::total 144528 # number of writebacks
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
sim_seconds 1.829332 # Number of seconds simulated
-sim_ticks 1829332049000 # Number of ticks simulated
-final_tick 1829332049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 1829331993500 # Number of ticks simulated
+final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2314619 # Simulator instruction rate (inst/s)
-host_op_rate 2314617 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 70524837278 # Simulator tick rate (ticks/s)
-host_mem_usage 315304 # Number of bytes of host memory used
-host_seconds 25.94 # Real time elapsed on the host
-sim_insts 60038433 # Number of instructions simulated
-sim_ops 60038433 # Number of ops (including micro ops) simulated
+host_inst_rate 2920462 # Simulator instruction rate (inst/s)
+host_op_rate 2920460 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 88984410684 # Simulator tick rate (ticks/s)
+host_mem_usage 366200 # Number of bytes of host memory used
+host_seconds 20.56 # Real time elapsed on the host
+sim_insts 60038469 # Number of instructions simulated
+sim_ops 60038469 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 66856384 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 66856000 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 67715328 # Number of bytes read from this memory
+system.physmem.bytes_read::total 67714944 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4754240 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 4753856 # Number of bytes written to this memory
system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7413568 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7413184 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1044631 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1044625 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1058052 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 74285 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 1058046 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 74279 # Number of write requests responded to by this memory
system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 115837 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 115831 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 36546883 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 36546674 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 37016422 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 37016214 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2598894 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2598684 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::tsunami.ide 1453715 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4052609 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2598894 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 4052399 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2598684 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 36546883 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 36546674 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1454240 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 41069032 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 41099809 # Throughput (bytes/s)
-system.membus.data_through_bus 75185198 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.physmem.bw_total::total 41068613 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 948404 # Transaction distribution
+system.membus.trans_dist::ReadResp 948404 # Transaction distribution
+system.membus.trans_dist::WriteReq 9838 # Transaction distribution
+system.membus.trans_dist::WriteResp 9838 # Transaction distribution
+system.membus.trans_dist::Writeback 74279 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 132 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
+system.membus.trans_dist::ReadExReq 116985 # Transaction distribution
+system.membus.trans_dist::ReadExResp 116985 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2190605 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 2224649 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83452 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 83452 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 2308101 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72467840 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513966 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2670464 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2670464 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 75184430 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 1174168 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 1174168 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 1174168 # Request fanout histogram
system.iocache.tags.replacements 41686 # number of replacements
-system.iocache.tags.tagsinuse 1.225568 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 1.225569 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide 1.225568 # Average occupied blocks per requestor
+system.iocache.tags.warmup_cycle 1685780587017 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide 1.225569 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 9710428 # DTB read hits
+system.cpu.dtb.read_hits 9710423 # DTB read hits
system.cpu.dtb.read_misses 10329 # DTB read misses
system.cpu.dtb.read_acv 210 # DTB read access violations
system.cpu.dtb.read_accesses 728856 # DTB read accesses
-system.cpu.dtb.write_hits 6352498 # DTB write hits
+system.cpu.dtb.write_hits 6352496 # DTB write hits
system.cpu.dtb.write_misses 1142 # DTB write misses
system.cpu.dtb.write_acv 157 # DTB write access violations
system.cpu.dtb.write_accesses 291931 # DTB write accesses
-system.cpu.dtb.data_hits 16062926 # DTB hits
+system.cpu.dtb.data_hits 16062919 # DTB hits
system.cpu.dtb.data_misses 11471 # DTB misses
system.cpu.dtb.data_acv 367 # DTB access violations
system.cpu.dtb.data_accesses 1020787 # DTB accesses
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.numCycles 3658664099 # number of cpu cycles simulated
+system.cpu.numCycles 3658670345 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 60038433 # Number of instructions committed
-system.cpu.committedOps 60038433 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 55913650 # Number of integer alu accesses
+system.cpu.committedInsts 60038469 # Number of instructions committed
+system.cpu.committedOps 60038469 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 55913692 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
system.cpu.num_func_calls 1484182 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 7110776 # number of instructions that are conditional controls
-system.cpu.num_int_insts 55913650 # number of integer instructions
+system.cpu.num_conditional_control_insts 7110791 # number of instructions that are conditional controls
+system.cpu.num_int_insts 55913692 # number of integer instructions
system.cpu.num_fp_insts 324460 # number of float instructions
-system.cpu.num_int_register_reads 76954165 # number of times the integer registers were read
-system.cpu.num_int_register_writes 41740323 # number of times the integer registers were written
+system.cpu.num_int_register_reads 76954245 # number of times the integer registers were read
+system.cpu.num_int_register_writes 41740352 # number of times the integer registers were written
system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
-system.cpu.num_mem_refs 16115710 # number of memory refs
-system.cpu.num_load_insts 9747514 # Number of load instructions
-system.cpu.num_store_insts 6368196 # Number of store instructions
-system.cpu.num_idle_cycles 3598608539.425618 # Number of idle cycles
-system.cpu.num_busy_cycles 60055559.574382 # Number of busy cycles
-system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.983585 # Percentage of idle cycles
-system.cpu.Branches 9064413 # Number of branches fetched
-system.cpu.op_class::No_OpClass 3199106 5.33% 5.33% # Class of executed instruction
-system.cpu.op_class::IntAlu 39448354 65.69% 71.02% # Class of executed instruction
-system.cpu.op_class::IntMult 60680 0.10% 71.12% # Class of executed instruction
+system.cpu.num_mem_refs 16115703 # number of memory refs
+system.cpu.num_load_insts 9747509 # Number of load instructions
+system.cpu.num_store_insts 6368194 # Number of store instructions
+system.cpu.num_idle_cycles 3598621002.088897 # Number of idle cycles
+system.cpu.num_busy_cycles 60049342.911103 # Number of busy cycles
+system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.983587 # Percentage of idle cycles
+system.cpu.Branches 9064428 # Number of branches fetched
+system.cpu.op_class::No_OpClass 3199100 5.33% 5.33% # Class of executed instruction
+system.cpu.op_class::IntAlu 39448406 65.69% 71.02% # Class of executed instruction
+system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction
system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction
-system.cpu.op_class::MemRead 9975082 16.61% 87.80% # Class of executed instruction
-system.cpu.op_class::MemWrite 6374117 10.61% 98.42% # Class of executed instruction
+system.cpu.op_class::MemRead 9975077 16.61% 87.80% # Class of executed instruction
+system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction
system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 60050271 # Class of executed instruction
+system.cpu.op_class::total 60050307 # Class of executed instruction
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed
system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1811927133000 99.05% 99.05% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::0 1811929127500 99.05% 99.05% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 17304360500 0.95% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1829331841500 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total 1829331786000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 26834199500 1.47% 1.47% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1801032572000 98.45% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle 1801033399500 98.45% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.iobus.throughput 1480181 # Throughput (bytes/s)
-system.iobus.data_through_bus 2707742 # Total data (bytes)
-system.cpu.icache.tags.replacements 919591 # number of replacements
-system.cpu.icache.tags.tagsinuse 511.215239 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 59130053 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 920103 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 64.264602 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 511.215239 # Average occupied blocks per requestor
+system.iobus.trans_dist::ReadReq 7358 # Transaction distribution
+system.iobus.trans_dist::ReadResp 7358 # Transaction distribution
+system.iobus.trans_dist::WriteReq 51390 # Transaction distribution
+system.iobus.trans_dist::WriteResp 9838 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes)
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+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
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+system.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses
+system.cpu.dcache.overall_misses::total 2026074 # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 15682062 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 15682062 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 15682062 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 15682062 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180670 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.180670 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049468 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.049468 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085675 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085675 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.129195 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.129195 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.129195 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.129195 # miss rate for overall accesses
+system.cpu.dcache.demand_accesses::cpu.data 15682055 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 15682055 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 15682055 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 15682055 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 833475 # number of writebacks
-system.cpu.dcache.writebacks::total 833475 # number of writebacks
+system.cpu.dcache.writebacks::writebacks 833484 # number of writebacks
+system.cpu.dcache.writebacks::total 833484 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 134320283 # Throughput (bytes/s)
-system.cpu.toL2Bus.data_through_bus 243047022 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 2669376 # Total snoop data (bytes)
+system.cpu.toL2Bus.trans_dist::ReadReq 2666288 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2666288 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 833484 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 304346 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 304346 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1840460 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4954000 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 6794460 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894720 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184155182 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 243049902 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 41883 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 3838676 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.010870 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.103691 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 3796950 98.91% 98.91% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 41726 1.09% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 3838676 # Request fanout histogram
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 1.962815 # Number of seconds simulated
-sim_ticks 1962815218500 # Number of ticks simulated
-final_tick 1962815218500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.961827 # Number of seconds simulated
+sim_ticks 1961826628500 # Number of ticks simulated
+final_tick 1961826628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1506000 # Simulator instruction rate (inst/s)
-host_op_rate 1505999 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 49787604582 # Simulator tick rate (ticks/s)
-host_mem_usage 317424 # Number of bytes of host memory used
-host_seconds 39.42 # Real time elapsed on the host
-sim_insts 59372159 # Number of instructions simulated
-sim_ops 59372159 # Number of ops (including micro ops) simulated
+host_inst_rate 1388652 # Simulator instruction rate (inst/s)
+host_op_rate 1388652 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 44739465331 # Simulator tick rate (ticks/s)
+host_mem_usage 370560 # Number of bytes of host memory used
+host_seconds 43.85 # Real time elapsed on the host
+sim_insts 60892387 # Number of instructions simulated
+sim_ops 60892387 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst 724992 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24166912 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 833152 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24900864 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 138560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 1080576 # Number of bytes read from this memory
-system.physmem.bytes_read::total 26112000 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 724992 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 138560 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 5090112 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst 31872 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 336832 # Number of bytes read from this memory
+system.physmem.bytes_read::total 26103680 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 833152 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 31872 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 5078656 # Number of bytes written to this memory
system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7749440 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 11328 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 377608 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 7737984 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 13018 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 389076 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 2165 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 16884 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 408000 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 79533 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 498 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 5263 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 407870 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 79354 # Number of write requests responded to by this memory
system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 121085 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 369363 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 12312372 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 120906 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 424682 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 12692693 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 70592 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 550524 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 13303341 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 369363 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 70592 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 439956 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2593271 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::tsunami.ide 1354854 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3948125 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2593271 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 369363 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 12312372 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1355343 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 70592 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 550524 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 17251466 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 408000 # Number of read requests accepted
-system.physmem.writeReqs 121085 # Number of write requests accepted
-system.physmem.readBursts 408000 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 121085 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 26099968 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 12032 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7747840 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 26112000 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 7749440 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 188 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_read::cpu1.inst 16246 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 171693 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 13305804 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 424682 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 16246 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 440928 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2588738 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::tsunami.ide 1355537 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3944275 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2588738 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 424682 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 12692693 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1356026 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 16246 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 171693 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 17250079 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 407870 # Number of read requests accepted
+system.physmem.writeReqs 120906 # Number of write requests accepted
+system.physmem.readBursts 407870 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 120906 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 26092032 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 11648 # Total number of bytes read from write queue
+system.physmem.bytesWritten 7736064 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 26103680 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 7737984 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 182 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 3360 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 25223 # Per bank write bursts
-system.physmem.perBankRdBursts::1 25569 # Per bank write bursts
-system.physmem.perBankRdBursts::2 25254 # Per bank write bursts
-system.physmem.perBankRdBursts::3 25702 # Per bank write bursts
-system.physmem.perBankRdBursts::4 25695 # Per bank write bursts
-system.physmem.perBankRdBursts::5 25237 # Per bank write bursts
-system.physmem.perBankRdBursts::6 25154 # Per bank write bursts
-system.physmem.perBankRdBursts::7 25289 # Per bank write bursts
-system.physmem.perBankRdBursts::8 25197 # Per bank write bursts
-system.physmem.perBankRdBursts::9 25673 # Per bank write bursts
-system.physmem.perBankRdBursts::10 25761 # Per bank write bursts
-system.physmem.perBankRdBursts::11 25821 # Per bank write bursts
-system.physmem.perBankRdBursts::12 25887 # Per bank write bursts
-system.physmem.perBankRdBursts::13 25811 # Per bank write bursts
-system.physmem.perBankRdBursts::14 25568 # Per bank write bursts
-system.physmem.perBankRdBursts::15 24971 # Per bank write bursts
-system.physmem.perBankWrBursts::0 7862 # Per bank write bursts
-system.physmem.perBankWrBursts::1 7635 # Per bank write bursts
-system.physmem.perBankWrBursts::2 7481 # Per bank write bursts
-system.physmem.perBankWrBursts::3 8078 # Per bank write bursts
-system.physmem.perBankWrBursts::4 7635 # Per bank write bursts
-system.physmem.perBankWrBursts::5 7244 # Per bank write bursts
-system.physmem.perBankWrBursts::6 7160 # Per bank write bursts
-system.physmem.perBankWrBursts::7 6937 # Per bank write bursts
-system.physmem.perBankWrBursts::8 6882 # Per bank write bursts
-system.physmem.perBankWrBursts::9 7297 # Per bank write bursts
-system.physmem.perBankWrBursts::10 7429 # Per bank write bursts
-system.physmem.perBankWrBursts::11 7398 # Per bank write bursts
-system.physmem.perBankWrBursts::12 8124 # Per bank write bursts
-system.physmem.perBankWrBursts::13 8265 # Per bank write bursts
-system.physmem.perBankWrBursts::14 8169 # Per bank write bursts
-system.physmem.perBankWrBursts::15 7464 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 6995 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 25277 # Per bank write bursts
+system.physmem.perBankRdBursts::1 25718 # Per bank write bursts
+system.physmem.perBankRdBursts::2 25598 # Per bank write bursts
+system.physmem.perBankRdBursts::3 25075 # Per bank write bursts
+system.physmem.perBankRdBursts::4 25186 # Per bank write bursts
+system.physmem.perBankRdBursts::5 25258 # Per bank write bursts
+system.physmem.perBankRdBursts::6 25824 # Per bank write bursts
+system.physmem.perBankRdBursts::7 25548 # Per bank write bursts
+system.physmem.perBankRdBursts::8 25573 # Per bank write bursts
+system.physmem.perBankRdBursts::9 25196 # Per bank write bursts
+system.physmem.perBankRdBursts::10 25177 # Per bank write bursts
+system.physmem.perBankRdBursts::11 25610 # Per bank write bursts
+system.physmem.perBankRdBursts::12 25669 # Per bank write bursts
+system.physmem.perBankRdBursts::13 25717 # Per bank write bursts
+system.physmem.perBankRdBursts::14 26016 # Per bank write bursts
+system.physmem.perBankRdBursts::15 25246 # Per bank write bursts
+system.physmem.perBankWrBursts::0 7929 # Per bank write bursts
+system.physmem.perBankWrBursts::1 7788 # Per bank write bursts
+system.physmem.perBankWrBursts::2 7545 # Per bank write bursts
+system.physmem.perBankWrBursts::3 7026 # Per bank write bursts
+system.physmem.perBankWrBursts::4 7134 # Per bank write bursts
+system.physmem.perBankWrBursts::5 7133 # Per bank write bursts
+system.physmem.perBankWrBursts::6 7657 # Per bank write bursts
+system.physmem.perBankWrBursts::7 7252 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7395 # Per bank write bursts
+system.physmem.perBankWrBursts::9 7084 # Per bank write bursts
+system.physmem.perBankWrBursts::10 7119 # Per bank write bursts
+system.physmem.perBankWrBursts::11 7401 # Per bank write bursts
+system.physmem.perBankWrBursts::12 7832 # Per bank write bursts
+system.physmem.perBankWrBursts::13 8315 # Per bank write bursts
+system.physmem.perBankWrBursts::14 8567 # Per bank write bursts
+system.physmem.perBankWrBursts::15 7699 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 6 # Number of times write queue was full causing retry
-system.physmem.totGap 1962808109000 # Total gap between requests
+system.physmem.numWrRetry 8 # Number of times write queue was full causing retry
+system.physmem.totGap 1961819616500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 408000 # Read request sizes (log2)
+system.physmem.readPktSize::6 407870 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 121085 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 407738 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 61 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 120906 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 407616 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 59 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1952 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 2710 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 5918 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 6075 # What write queue length does an incoming req see
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-system.physmem.bytesPerActivate::samples 66023 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 512.666919 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 309.343673 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 413.043592 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 15664 23.73% 23.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 11865 17.97% 41.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 5137 7.78% 49.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3080 4.67% 54.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 3330 5.04% 59.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1778 2.69% 61.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1463 2.22% 64.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1306 1.98% 66.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 22400 33.93% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 66023 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5447 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 74.865981 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 2190.069327 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095 5442 99.91% 99.91% # Reads before turning the bus around for writes
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+system.physmem.bytesPerActivate::1024-1151 22347 33.64% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 66427 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 5433 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 75.036996 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5447 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5447 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 22.225078 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 19.080270 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 19.855094 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 4780 87.75% 87.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 19 0.35% 88.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 16 0.29% 88.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 235 4.31% 92.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 38 0.70% 93.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 9 0.17% 93.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 13 0.24% 93.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 10 0.18% 94.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 23 0.42% 94.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 3 0.06% 94.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 2 0.04% 94.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 1 0.02% 94.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 7 0.13% 94.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 5 0.09% 94.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 4 0.07% 94.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 29 0.53% 95.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 14 0.26% 95.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 6 0.11% 95.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 6 0.11% 95.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 182 3.34% 99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 1 0.02% 99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 2 0.04% 99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 2 0.04% 99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 1 0.02% 99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 1 0.02% 99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 10 0.18% 99.49% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::136-139 5 0.09% 99.61% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::180-183 1 0.02% 99.94% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::mean 22.248482 # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::36-39 9 0.17% 93.61% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::224-227 2 0.04% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5447 # Writes before turning the bus around for reads
-system.physmem.totQLat 2167934250 # Total ticks spent queuing
-system.physmem.totMemAccLat 9814409250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2039060000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 5316.01 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total 5433 # Writes before turning the bus around for reads
+system.physmem.totQLat 2198653000 # Total ticks spent queuing
+system.physmem.totMemAccLat 9842803000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2038440000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 5392.98 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 24066.01 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 24142.98 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 13.30 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 13.30 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 13.31 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 3.94 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.13 # Data bus utilization in percentage
system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.06 # Average write queue length when enqueuing
-system.physmem.readRowHits 365758 # Number of row buffer hits during reads
-system.physmem.writeRowHits 97091 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 89.69 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 80.18 # Row buffer hit rate for writes
-system.physmem.avgGap 3709816.21 # Average gap between requests
-system.physmem.pageHitRate 87.51 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 1840831671000 # Time in different power states
-system.physmem.memoryStateTime::REF 65542620000 # Time in different power states
+system.physmem.avgWrQLen 26.12 # Average write queue length when enqueuing
+system.physmem.readRowHits 365377 # Number of row buffer hits during reads
+system.physmem.writeRowHits 96760 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 89.62 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 80.03 # Row buffer hit rate for writes
+system.physmem.avgGap 3710114.71 # Average gap between requests
+system.physmem.pageHitRate 87.43 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 1840052567250 # Time in different power states
+system.physmem.memoryStateTime::REF 65509600000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 56438386500 # Time in different power states
+system.physmem.memoryStateTime::ACT 56261656500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 17291736 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 292660 # Transaction distribution
-system.membus.trans_dist::ReadResp 292660 # Transaction distribution
-system.membus.trans_dist::WriteReq 12414 # Transaction distribution
-system.membus.trans_dist::WriteResp 12414 # Transaction distribution
-system.membus.trans_dist::Writeback 79533 # Transaction distribution
+system.membus.trans_dist::ReadReq 292757 # Transaction distribution
+system.membus.trans_dist::ReadResp 292757 # Transaction distribution
+system.membus.trans_dist::WriteReq 14067 # Transaction distribution
+system.membus.trans_dist::WriteResp 14067 # Transaction distribution
+system.membus.trans_dist::Writeback 79354 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4556 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 1019 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 3360 # Transaction distribution
-system.membus.trans_dist::ReadExReq 122803 # Transaction distribution
-system.membus.trans_dist::ReadExResp 122701 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39228 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 904540 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 943768 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83295 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 83295 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1027063 # Packet count per connected master and slave (bytes)
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-system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60270.301213 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60270.301213 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70111.396552 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60199.384049 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60199.384049 # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 70111.396552 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 70111.396552 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 6067147 # DTB read hits
+system.cpu0.dtb.read_hits 7562596 # DTB read hits
system.cpu0.dtb.read_misses 7765 # DTB read misses
system.cpu0.dtb.read_acv 210 # DTB read access violations
system.cpu0.dtb.read_accesses 524069 # DTB read accesses
-system.cpu0.dtb.write_hits 4265547 # DTB write hits
+system.cpu0.dtb.write_hits 5147185 # DTB write hits
system.cpu0.dtb.write_misses 910 # DTB write misses
system.cpu0.dtb.write_acv 133 # DTB write access violations
system.cpu0.dtb.write_accesses 202595 # DTB write accesses
-system.cpu0.dtb.data_hits 10332694 # DTB hits
+system.cpu0.dtb.data_hits 12709781 # DTB hits
system.cpu0.dtb.data_misses 8675 # DTB misses
system.cpu0.dtb.data_acv 343 # DTB access violations
system.cpu0.dtb.data_accesses 726664 # DTB accesses
-system.cpu0.itb.fetch_hits 3354719 # ITB hits
+system.cpu0.itb.fetch_hits 3660706 # ITB hits
system.cpu0.itb.fetch_misses 3984 # ITB misses
system.cpu0.itb.fetch_acv 184 # ITB acv
-system.cpu0.itb.fetch_accesses 3358703 # ITB accesses
+system.cpu0.itb.fetch_accesses 3664690 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 3925630437 # number of cpu cycles simulated
+system.cpu0.numCycles 3923653257 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 38276405 # Number of instructions committed
-system.cpu0.committedOps 38276405 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 35596815 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 153493 # Number of float alu accesses
-system.cpu0.num_func_calls 936479 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4465105 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 35596815 # number of integer instructions
-system.cpu0.num_fp_insts 153493 # number of float instructions
-system.cpu0.num_int_register_reads 48919188 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 26532196 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 75000 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 75910 # number of times the floating registers were written
-system.cpu0.num_mem_refs 10365856 # number of memory refs
-system.cpu0.num_load_insts 6090539 # Number of load instructions
-system.cpu0.num_store_insts 4275317 # Number of store instructions
-system.cpu0.num_idle_cycles 3742236660.998093 # Number of idle cycles
-system.cpu0.num_busy_cycles 183393776.001907 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.046717 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.953283 # Percentage of idle cycles
-system.cpu0.Branches 5694884 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 2096297 5.48% 5.48% # Class of executed instruction
-system.cpu0.op_class::IntAlu 24983670 65.26% 70.73% # Class of executed instruction
-system.cpu0.op_class::IntMult 39322 0.10% 70.83% # Class of executed instruction
-system.cpu0.op_class::IntDiv 0 0.00% 70.83% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 24596 0.06% 70.90% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 1883 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.90% # Class of executed instruction
-system.cpu0.op_class::MemRead 6232893 16.28% 87.18% # Class of executed instruction
-system.cpu0.op_class::MemWrite 4280562 11.18% 98.36% # Class of executed instruction
-system.cpu0.op_class::IprAccess 626200 1.64% 100.00% # Class of executed instruction
+system.cpu0.committedInsts 48127777 # Number of instructions committed
+system.cpu0.committedOps 48127777 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 44643925 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 213512 # Number of float alu accesses
+system.cpu0.num_func_calls 1209739 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 5647172 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 44643925 # number of integer instructions
+system.cpu0.num_fp_insts 213512 # number of float instructions
+system.cpu0.num_int_register_reads 61387452 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 33242964 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 104337 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 106136 # number of times the floating registers were written
+system.cpu0.num_mem_refs 12750882 # number of memory refs
+system.cpu0.num_load_insts 7590433 # Number of load instructions
+system.cpu0.num_store_insts 5160449 # Number of store instructions
+system.cpu0.num_idle_cycles 3699495012.998114 # Number of idle cycles
+system.cpu0.num_busy_cycles 224158244.001886 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.057130 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.942870 # Percentage of idle cycles
+system.cpu0.Branches 7246936 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 2741568 5.70% 5.70% # Class of executed instruction
+system.cpu0.op_class::IntAlu 31634980 65.72% 71.41% # Class of executed instruction
+system.cpu0.op_class::IntMult 52525 0.11% 71.52% # Class of executed instruction
+system.cpu0.op_class::IntDiv 0 0.00% 71.52% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 26830 0.06% 71.58% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 71.58% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 71.58% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 71.58% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 1883 0.00% 71.58% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 71.58% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 71.58% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 71.58% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 71.58% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 71.58% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 71.58% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 71.58% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 71.58% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 71.58% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 71.58% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.58% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 71.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.58% # Class of executed instruction
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+system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 71.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.58% # Class of executed instruction
+system.cpu0.op_class::MemRead 7767201 16.14% 87.72% # Class of executed instruction
+system.cpu0.op_class::MemWrite 5166567 10.73% 98.45% # Class of executed instruction
+system.cpu0.op_class::IprAccess 745241 1.55% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 38285423 # Class of executed instruction
+system.cpu0.op_class::total 48136795 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 4863 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 138357 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 44808 38.76% 38.76% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 131 0.11% 38.88% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1975 1.71% 40.58% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 16 0.01% 40.60% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 68665 59.40% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 115595 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 44283 48.84% 48.84% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 131 0.14% 48.98% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1975 2.18% 51.16% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 16 0.02% 51.18% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 44267 48.82% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 90672 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1909699143000 97.29% 97.29% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 95243500 0.00% 97.30% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 764380500 0.04% 97.34% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 12585500 0.00% 97.34% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 52243094000 2.66% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1962814446500 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.988283 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce 6805 # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei 166328 # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0 57239 40.25% 40.25% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21 131 0.09% 40.34% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22 1975 1.39% 41.73% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30 424 0.30% 42.03% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 82449 57.97% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 142218 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 56706 49.09% 49.09% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22 1975 1.71% 50.91% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30 424 0.37% 51.28% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31 56283 48.72% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total 115519 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0 1902225794500 96.96% 96.96% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 94977500 0.00% 96.97% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 767421000 0.04% 97.01% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30 314336500 0.02% 97.02% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 58423341500 2.98% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1961825871000 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0 0.990688 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.644681 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.784394 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31 0.682640 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total 0.812267 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed
system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 234 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir 86 0.07% 0.07% # number of callpals executed
-system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed
-system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 2216 1.80% 1.87% # number of callpals executed
-system.cpu0.kern.callpal::tbi 51 0.04% 1.92% # number of callpals executed
-system.cpu0.kern.callpal::wrent 7 0.01% 1.92% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 109456 88.95% 90.88% # number of callpals executed
-system.cpu0.kern.callpal::rdps 6662 5.41% 96.29% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp 1 0.00% 96.29% # number of callpals executed
-system.cpu0.kern.callpal::wrusp 4 0.00% 96.29% # number of callpals executed
-system.cpu0.kern.callpal::rdusp 9 0.01% 96.30% # number of callpals executed
-system.cpu0.kern.callpal::whami 2 0.00% 96.30% # number of callpals executed
-system.cpu0.kern.callpal::rti 4016 3.26% 99.57% # number of callpals executed
-system.cpu0.kern.callpal::callsys 394 0.32% 99.89% # number of callpals executed
-system.cpu0.kern.callpal::imb 139 0.11% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 123047 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 5724 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1372 # number of protection mode switches
+system.cpu0.kern.callpal::wripir 506 0.34% 0.34% # number of callpals executed
+system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed
+system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed
+system.cpu0.kern.callpal::swpctx 3105 2.06% 2.40% # number of callpals executed
+system.cpu0.kern.callpal::tbi 51 0.03% 2.43% # number of callpals executed
+system.cpu0.kern.callpal::wrent 7 0.00% 2.44% # number of callpals executed
+system.cpu0.kern.callpal::swpipl 135265 89.81% 92.25% # number of callpals executed
+system.cpu0.kern.callpal::rdps 6701 4.45% 96.70% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp 1 0.00% 96.70% # number of callpals executed
+system.cpu0.kern.callpal::wrusp 4 0.00% 96.70% # number of callpals executed
+system.cpu0.kern.callpal::rdusp 9 0.01% 96.71% # number of callpals executed
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+system.cpu0.kern.callpal::rti 4423 2.94% 99.65% # number of callpals executed
+system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed
+system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed
+system.cpu0.kern.callpal::total 150611 # number of callpals executed
+system.cpu0.kern.mode_switch::kernel 7020 # number of protection mode switches
+system.cpu0.kern.mode_switch::user 1371 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
-system.cpu0.kern.mode_good::kernel 1371
-system.cpu0.kern.mode_good::user 1372
+system.cpu0.kern.mode_good::kernel 1370
+system.cpu0.kern.mode_good::user 1371
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.239518 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.195157 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.386556 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1959023925000 99.81% 99.81% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 3790517000 0.19% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total 0.326660 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 1958053140500 99.81% 99.81% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 3772726000 0.19% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 2217 # number of times the context was actually changed
+system.cpu0.kern.swap_context 3106 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.throughput 109416622 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 2148133 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2148118 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 12414 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 12414 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 850078 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 41558 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 4615 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 1065 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 5680 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 322069 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 322069 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078328 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2181300 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 927173 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1598235 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 5785036 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 34505856 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 81606637 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29669504 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 63812309 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 209594306 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 209584002 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 5180608 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 5075622491 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks)
+system.toL2Bus.trans_dist::ReadReq 2102030 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2102015 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 14067 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 14067 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 792816 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 41560 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 16382 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 11336 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 27718 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 297616 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 297616 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1407417 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3134555 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 624007 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 452565 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 5618544 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 45036672 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120042720 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 19968192 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16553666 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 201601250 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 98838 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 3254541 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 3.012823 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.112512 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 3212807 98.72% 98.72% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 41734 1.28% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3254541 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 4795402363 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy 715500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 2428486244 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 4030575545 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 2086565739 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 3169257997 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 5536514081 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 1404115991 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 2646502814 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%)
-system.iobus.throughput 1391048 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 7376 # Transaction distribution
-system.iobus.trans_dist::ReadResp 7376 # Transaction distribution
-system.iobus.trans_dist::WriteReq 53966 # Transaction distribution
-system.iobus.trans_dist::WriteResp 53966 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10614 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 484 # Packet count per connected master and slave (bytes)
+system.toL2Bus.respLayer3.occupancy 776560164 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 7373 # Transaction distribution
+system.iobus.trans_dist::ReadResp 7373 # Transaction distribution
+system.iobus.trans_dist::WriteReq 55619 # Transaction distribution
+system.iobus.trans_dist::WriteResp 55619 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13922 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 39228 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 122684 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42456 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1936 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 68738 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 2730370 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 2730370 # Total data (bytes)
-system.iobus.reqLayer0.occupancy 9969000 # Layer occupancy (ticks)
+system.iobus.pkt_count_system.bridge.master::total 42532 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 125984 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55688 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 81954 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2743570 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 13277000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 362000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer29.occupancy 374413689 # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy 374410189 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 26814000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 28465000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 42018250 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 42017000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.icache.tags.replacements 538541 # number of replacements
-system.cpu0.icache.tags.tagsinuse 508.393356 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 37746250 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 539053 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 70.023263 # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements 703089 # number of replacements
+system.cpu0.icache.tags.tagsinuse 508.385515 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 47433077 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 703601 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 67.414738 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.393356 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992956 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.992956 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.385515 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992940 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.992940 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 442 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 38824598 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 38824598 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 37746250 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 37746250 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 37746250 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 37746250 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 37746250 # number of overall hits
-system.cpu0.icache.overall_hits::total 37746250 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 539174 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 539174 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 539174 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 539174 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 539174 # number of overall misses
-system.cpu0.icache.overall_misses::total 539174 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7756302744 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 7756302744 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 7756302744 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 7756302744 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 7756302744 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 7756302744 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 38285424 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 38285424 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 38285424 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 38285424 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 38285424 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 38285424 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014083 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.014083 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014083 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.014083 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014083 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.014083 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14385.528130 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14385.528130 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14385.528130 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14385.528130 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14385.528130 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14385.528130 # average overall miss latency
+system.cpu0.icache.tags.tag_accesses 48840515 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 48840515 # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst 47433077 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 47433077 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 47433077 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 47433077 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 47433077 # number of overall hits
+system.cpu0.icache.overall_hits::total 47433077 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 703719 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 703719 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 703719 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 703719 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 703719 # number of overall misses
+system.cpu0.icache.overall_misses::total 703719 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10017635497 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 10017635497 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 10017635497 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 10017635497 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 10017635497 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 10017635497 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 48136796 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 48136796 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 48136796 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 48136796 # number of demand (read+write) accesses
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+system.cpu0.icache.overall_accesses::total 48136796 # number of overall (read+write) accesses
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+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14235.277855 # average overall miss latency
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system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
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-system.cpu0.icache.ReadReq_mshr_miss_latency::total 6673548256 # number of ReadReq MSHR miss cycles
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-system.cpu0.icache.demand_mshr_miss_latency::total 6673548256 # number of demand (read+write) MSHR miss cycles
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system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit.
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-system.cpu0.dcache.overall_avg_miss_latency::total 37535.011441 # average overall miss latency
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+system.cpu0.dcache.demand_avg_miss_latency::total 31306.571546 # average overall miss latency
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 405151 # number of writebacks
-system.cpu0.dcache.writebacks::total 405151 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 645318 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 645318 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 224183 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 224183 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7829 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7829 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 497 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 497 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 869501 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 869501 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 869501 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 869501 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21958327500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21958327500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8765186517 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8765186517 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 87163500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 87163500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2590438 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2590438 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30723514017 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 30723514017 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30723514017 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 30723514017 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1004927000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1004927000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1718158000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1718158000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2723085000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2723085000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.108546 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.108546 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.054283 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.054283 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059032 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059032 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003763 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003763 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086303 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.086303 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086303 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.086303 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34027.142432 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34027.142432 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39098.354991 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39098.354991 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11133.414229 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11133.414229 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5212.148893 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5212.148893 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35334.650583 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35334.650583 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35334.650583 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35334.650583 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 686359 # number of writebacks
+system.cpu0.dcache.writebacks::total 686359 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942620 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 942620 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 258040 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 258040 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13696 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13696 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5452 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 5452 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 1200660 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 1200660 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 1200660 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 1200660 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25222171750 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25222171750 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9786377058 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9786377058 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 122453500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 122453500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31105611 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31105611 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35008548808 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 35008548808 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35008548808 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 35008548808 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465625500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465625500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2277904000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2277904000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3743529500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3743529500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127036 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127036 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051717 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051717 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088214 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088214 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035241 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035241 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096753 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.096753 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096753 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.096753 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26757.518141 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26757.518141 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37925.814052 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37925.814052 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8940.822138 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8940.822138 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5705.357850 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5705.357850 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29157.753909 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29157.753909 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29157.753909 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29157.753909 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 3617054 # DTB read hits
+system.cpu1.dtb.read_hits 2348280 # DTB read hits
system.cpu1.dtb.read_misses 2620 # DTB read misses
system.cpu1.dtb.read_acv 0 # DTB read access violations
system.cpu1.dtb.read_accesses 205337 # DTB read accesses
-system.cpu1.dtb.write_hits 2433875 # DTB write hits
+system.cpu1.dtb.write_hits 1676993 # DTB write hits
system.cpu1.dtb.write_misses 235 # DTB write misses
system.cpu1.dtb.write_acv 24 # DTB write access violations
system.cpu1.dtb.write_accesses 89739 # DTB write accesses
-system.cpu1.dtb.data_hits 6050929 # DTB hits
+system.cpu1.dtb.data_hits 4025273 # DTB hits
system.cpu1.dtb.data_misses 2855 # DTB misses
system.cpu1.dtb.data_acv 24 # DTB access violations
system.cpu1.dtb.data_accesses 295076 # DTB accesses
-system.cpu1.itb.fetch_hits 1988100 # ITB hits
+system.cpu1.itb.fetch_hits 1801078 # ITB hits
system.cpu1.itb.fetch_misses 1064 # ITB misses
system.cpu1.itb.fetch_acv 0 # ITB acv
-system.cpu1.itb.fetch_accesses 1989164 # ITB accesses
+system.cpu1.itb.fetch_accesses 1802142 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 3923841470 # number of cpu cycles simulated
+system.cpu1.numCycles 3921880878 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 21095754 # Number of instructions committed
-system.cpu1.committedOps 21095754 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 19410964 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 175175 # Number of float alu accesses
-system.cpu1.num_func_calls 648514 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 2286581 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 19410964 # number of integer instructions
-system.cpu1.num_fp_insts 175175 # number of float instructions
-system.cpu1.num_int_register_reads 26520307 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 14289908 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 90745 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 92744 # number of times the floating registers were written
-system.cpu1.num_mem_refs 6073169 # number of memory refs
-system.cpu1.num_load_insts 3630901 # Number of load instructions
-system.cpu1.num_store_insts 2442268 # Number of store instructions
-system.cpu1.num_idle_cycles 3837673362.965370 # Number of idle cycles
-system.cpu1.num_busy_cycles 86168107.034630 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.021960 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.978040 # Percentage of idle cycles
-system.cpu1.Branches 3165037 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 1250062 5.92% 5.92% # Class of executed instruction
-system.cpu1.op_class::IntAlu 13186802 62.50% 68.43% # Class of executed instruction
-system.cpu1.op_class::IntMult 30198 0.14% 68.57% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 68.57% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 13644 0.06% 68.63% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 68.63% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 68.63% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 68.63% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 1759 0.01% 68.64% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 68.64% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 68.64% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 68.64% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 68.64% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 68.64% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 68.64% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 68.64% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 68.64% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 68.64% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 68.64% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.64% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 68.64% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.64% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.64% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.64% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.64% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.64% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 68.64% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 68.64% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.64% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.64% # Class of executed instruction
-system.cpu1.op_class::MemRead 3726078 17.66% 86.30% # Class of executed instruction
-system.cpu1.op_class::MemWrite 2443288 11.58% 97.88% # Class of executed instruction
-system.cpu1.op_class::IprAccess 446802 2.12% 100.00% # Class of executed instruction
+system.cpu1.committedInsts 12764610 # Number of instructions committed
+system.cpu1.committedOps 12764610 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 11762987 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 170364 # Number of float alu accesses
+system.cpu1.num_func_calls 404048 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 1265459 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 11762987 # number of integer instructions
+system.cpu1.num_fp_insts 170364 # number of float instructions
+system.cpu1.num_int_register_reads 16177090 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 8656212 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 88600 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 90534 # number of times the floating registers were written
+system.cpu1.num_mem_refs 4047820 # number of memory refs
+system.cpu1.num_load_insts 2361802 # Number of load instructions
+system.cpu1.num_store_insts 1686018 # Number of store instructions
+system.cpu1.num_idle_cycles 3873240792.459649 # Number of idle cycles
+system.cpu1.num_busy_cycles 48640085.540351 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.012402 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.987598 # Percentage of idle cycles
+system.cpu1.Branches 1821460 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 690637 5.41% 5.41% # Class of executed instruction
+system.cpu1.op_class::IntAlu 7566798 59.27% 64.68% # Class of executed instruction
+system.cpu1.op_class::IntMult 21839 0.17% 64.85% # Class of executed instruction
+system.cpu1.op_class::IntDiv 0 0.00% 64.85% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 13058 0.10% 64.95% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 64.95% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 64.95% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 64.95% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 1759 0.01% 64.96% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 64.96% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 64.96% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 64.96% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 64.96% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 64.96% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 64.96% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 64.96% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 64.96% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 64.96% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 64.96% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.96% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 64.96% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.96% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.96% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.96% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.96% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.96% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.96% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 64.96% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.96% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.96% # Class of executed instruction
+system.cpu1.op_class::MemRead 2432293 19.05% 84.01% # Class of executed instruction
+system.cpu1.op_class::MemWrite 1686990 13.21% 97.23% # Class of executed instruction
+system.cpu1.op_class::IprAccess 354115 2.77% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 21098633 # Class of executed instruction
+system.cpu1.op_class::total 12767489 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 3863 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 100733 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 37218 40.29% 40.29% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1970 2.13% 42.42% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 86 0.09% 42.51% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 53108 57.49% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 92382 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 36366 48.68% 48.68% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1970 2.64% 51.32% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 86 0.12% 51.43% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 36280 48.57% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 74702 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1906657223000 97.18% 97.18% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 706239500 0.04% 97.22% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 59367000 0.00% 97.22% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 54497875500 2.78% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1961920705000 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.977108 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei 77083 # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0 26133 38.19% 38.19% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22 1969 2.88% 41.07% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30 506 0.74% 41.81% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31 39822 58.19% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total 68430 # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0 25289 48.13% 48.13% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22 1969 3.75% 51.87% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30 506 0.96% 52.84% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31 24783 47.16% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total 52547 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0 1909614154000 97.38% 97.38% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 700846000 0.04% 97.42% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30 353816000 0.02% 97.44% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 50271593000 2.56% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1960940409000 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0 0.967704 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.683136 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total 0.808621 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31 0.622344 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total 0.767894 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed
system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed
system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed
system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 92 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed
-system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed
-system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed
-system.cpu1.kern.callpal::swpctx 2020 2.13% 2.15% # number of callpals executed
-system.cpu1.kern.callpal::tbi 3 0.00% 2.16% # number of callpals executed
-system.cpu1.kern.callpal::wrent 7 0.01% 2.16% # number of callpals executed
-system.cpu1.kern.callpal::swpipl 87059 91.90% 94.06% # number of callpals executed
-system.cpu1.kern.callpal::rdps 2187 2.31% 96.37% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp 1 0.00% 96.37% # number of callpals executed
-system.cpu1.kern.callpal::wrusp 3 0.00% 96.38% # number of callpals executed
-system.cpu1.kern.callpal::whami 3 0.00% 96.38% # number of callpals executed
-system.cpu1.kern.callpal::rti 3266 3.45% 99.83% # number of callpals executed
-system.cpu1.kern.callpal::callsys 121 0.13% 99.95% # number of callpals executed
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+system.cpu1.kern.callpal::swpctx 1955 2.77% 3.37% # number of callpals executed
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+system.cpu1.kern.callpal::rti 3685 5.21% 99.77% # number of callpals executed
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system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 94732 # number of callpals executed
-system.cpu1.kern.mode_switch::kernel 2415 # number of protection mode switches
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system.cpu1.kern.mode_switch::user 367 # number of protection mode switches
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-system.cpu1.kern.mode_good::kernel 415
+system.cpu1.kern.mode_switch::idle 2888 # number of protection mode switches
+system.cpu1.kern.mode_good::kernel 797
system.cpu1.kern.mode_good::user 367
-system.cpu1.kern.mode_good::idle 48
-system.cpu1.kern.mode_switch_good::kernel 0.171843 # fraction of useful protection mode switches
+system.cpu1.kern.mode_good::idle 430
+system.cpu1.kern.mode_switch_good::kernel 0.415537 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
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-system.cpu1.kern.mode_switch_good::total 0.172235 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 65779284000 3.35% 3.35% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 1486343500 0.08% 3.43% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1893759051500 96.57% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 2021 # number of times the context was actually changed
-system.cpu1.icache.tags.replacements 463035 # number of replacements
-system.cpu1.icache.tags.tagsinuse 500.061178 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 20635046 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 463547 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 44.515542 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 97712638250 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 500.061178 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.976682 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.976682 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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-system.cpu1.icache.tags.age_task_id_blocks_1024::3 404 # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 21562220 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 21562220 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 20635046 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 20635046 # number of ReadReq hits
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-system.cpu1.icache.ReadReq_miss_rate::total 0.021972 # miss rate for ReadReq accesses
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-system.cpu1.icache.overall_miss_rate::total 0.021972 # miss rate for overall accesses
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-system.cpu1.icache.ReadReq_avg_miss_latency::total 13380.133047 # average ReadReq miss latency
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-system.cpu1.icache.demand_avg_miss_latency::total 13380.133047 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13380.133047 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13380.133047 # average overall miss latency
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+system.cpu1.icache.tags.sampled_refs 311964 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 39.926033 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 1960014862500 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.345950 # Average occupied blocks per requestor
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+system.cpu1.icache.tags.age_task_id_blocks_1024::3 440 # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
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+system.cpu1.icache.tags.data_accesses 13079493 # Number of data accesses
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+system.cpu1.icache.overall_miss_rate::total 0.024437 # miss rate for overall accesses
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+system.cpu1.icache.ReadReq_avg_miss_latency::total 13158.328070 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13158.328070 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13158.328070 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13158.328070 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13158.328070 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463587 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 463587 # number of ReadReq MSHR misses
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-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5274833261 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 5274833261 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5274833261 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 5274833261 # number of overall MSHR miss cycles
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-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021972 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.021972 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.021972 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11378.302802 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11378.302802 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11378.302802 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 312004 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total 312004 # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 312004 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total 312004 # number of demand (read+write) MSHR misses
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+system.cpu1.icache.overall_mshr_misses::total 312004 # number of overall MSHR misses
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+system.cpu1.icache.ReadReq_mshr_miss_latency::total 3481247009 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3481247009 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 3481247009 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3481247009 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 3481247009 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024437 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024437 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024437 # mshr miss rate for demand accesses
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+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11157.699930 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11157.699930 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11157.699930 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11157.699930 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11157.699930 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11157.699930 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements 581700 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 492.027042 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 5462019 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 582040 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 9.384267 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 61159690250 # Cycle when the warmup percentage was hit.
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-system.cpu1.dcache.tags.occ_task_id_blocks::1024 340 # Occupied blocks per task id
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-system.cpu1.dcache.tags.tag_accesses 24828314 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 24828314 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 3080149 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 3080149 # number of ReadReq hits
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-system.cpu1.dcache.StoreCondReq_hits::total 71555 # number of StoreCondReq hits
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-system.cpu1.dcache.overall_hits::total 5340135 # number of overall hits
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-system.cpu1.dcache.LoadLockedReq_misses::total 11671 # number of LoadLockedReq misses
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-system.cpu1.dcache.StoreCondReq_misses::total 568 # number of StoreCondReq misses
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-system.cpu1.dcache.demand_misses::total 575679 # number of demand (read+write) misses
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-system.cpu1.dcache.overall_misses::total 575679 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5938208750 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 5938208750 # number of ReadReq miss cycles
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-system.cpu1.dcache.StoreCondReq_miss_latency::total 4181580 # number of StoreCondReq miss cycles
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-system.cpu1.dcache.overall_miss_latency::total 8277022984 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 3553327 # number of ReadReq accesses(hits+misses)
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-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12549.629843 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12549.629843 # average ReadReq miss latency
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-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12843.179676 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12843.179676 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7361.936620 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7361.936620 # average StoreCondReq miss latency
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-system.cpu1.dcache.demand_avg_miss_latency::total 14377.844222 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14377.844222 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 14377.844222 # average overall miss latency
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+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.146225 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.146225 # average ReadReq miss latency
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+system.cpu1.dcache.WriteReq_avg_miss_latency::total 18233.684281 # average WriteReq miss latency
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+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9077.183480 # average LoadLockedReq miss latency
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+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7359.943746 # average StoreCondReq miss latency
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+system.cpu1.dcache.demand_avg_miss_latency::total 14096.351833 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14096.351833 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 14096.351833 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 444927 # number of writebacks
-system.cpu1.dcache.writebacks::total 444927 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 473178 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 473178 # number of ReadReq MSHR misses
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-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11671 # number of LoadLockedReq MSHR misses
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-system.cpu1.dcache.StoreCondReq_mshr_misses::total 568 # number of StoreCondReq MSHR misses
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-system.cpu1.dcache.demand_mshr_misses::total 575679 # number of demand (read+write) MSHR misses
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-system.cpu1.dcache.overall_mshr_misses::total 575679 # number of overall MSHR misses
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-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 126550250 # number of LoadLockedReq MSHR miss cycles
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-system.cpu1.dcache.demand_mshr_miss_latency::total 7118815016 # number of demand (read+write) MSHR miss cycles
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-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.160762 # mshr miss rate for LoadLockedReq accesses
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-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10548.878540 # average ReadReq mshr miss latency
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-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20754.117189 # average WriteReq mshr miss latency
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-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10843.136835 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5361.654930 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5361.654930 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12365.945285 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12365.945285 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12365.945285 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12365.945285 # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 106457 # number of writebacks
+system.cpu1.dcache.writebacks::total 106457 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 113756 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 113756 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 55958 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 55958 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8862 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8862 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5884 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 5884 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 169714 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 169714 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 169714 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 169714 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1144439250 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1144439250 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 906162495 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 906162495 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62718000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62718000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31536091 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31536091 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2050601745 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 2050601745 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2050601745 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 2050601745 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18765500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18765500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 713325000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 713325000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 732090500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 732090500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049389 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049389 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034468 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034468 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.158720 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.158720 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106277 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106277 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043220 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.043220 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043220 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.043220 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10060.473733 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10060.473733 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16193.618339 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16193.618339 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7077.183480 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7077.183480 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5359.634772 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5359.634772 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12082.690556 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12082.690556 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12082.690556 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12082.690556 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
---------- Begin Simulation Statistics ----------
sim_seconds 1.919439 # Number of seconds simulated
-sim_ticks 1919438772000 # Number of ticks simulated
-final_tick 1919438772000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 1919439025000 # Number of ticks simulated
+final_tick 1919439025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1398299 # Simulator instruction rate (inst/s)
-host_op_rate 1398299 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47840414078 # Simulator tick rate (ticks/s)
-host_mem_usage 314348 # Number of bytes of host memory used
-host_seconds 40.12 # Real time elapsed on the host
-sim_insts 56102112 # Number of instructions simulated
-sim_ops 56102112 # Number of ops (including micro ops) simulated
+host_inst_rate 1426339 # Simulator instruction rate (inst/s)
+host_op_rate 1426339 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 48799693433 # Simulator tick rate (ticks/s)
+host_mem_usage 367228 # Number of bytes of host memory used
+host_seconds 39.33 # Real time elapsed on the host
+sim_insts 56102180 # Number of instructions simulated
+sim_ops 56102180 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 850816 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24875968 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24875904 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 25727744 # Number of bytes read from this memory
+system.physmem.bytes_read::total 25727680 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 850816 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 850816 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4747712 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 4747520 # Number of bytes written to this memory
system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7407040 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 13294 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 388687 # Number of read requests responded to by this memory
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system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 401996 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 74183 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 401995 # Number of read requests responded to by this memory
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system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 115735 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 115732 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 443263 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 12960022 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 12959987 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 13403785 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 13403750 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 443263 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 443263 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2473490 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::tsunami.ide 1385472 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3858961 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2473490 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2473389 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::tsunami.ide 1385471 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3858861 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2473389 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 443263 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 12960022 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 12959987 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1385972 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 17262746 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 401996 # Number of read requests accepted
-system.physmem.writeReqs 115735 # Number of write requests accepted
-system.physmem.readBursts 401996 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 115735 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 25716224 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 11520 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7405312 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 25727744 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 7407040 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 180 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total 17262610 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 401995 # Number of read requests accepted
+system.physmem.writeReqs 115732 # Number of write requests accepted
+system.physmem.readBursts 401995 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 115732 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 25715968 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 11712 # Total number of bytes read from write queue
+system.physmem.bytesWritten 7405120 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 25727680 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 7406848 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 183 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 132 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 25161 # Per bank write bursts
-system.physmem.perBankRdBursts::1 25541 # Per bank write bursts
+system.physmem.perBankRdBursts::1 25539 # Per bank write bursts
system.physmem.perBankRdBursts::2 25618 # Per bank write bursts
-system.physmem.perBankRdBursts::3 25537 # Per bank write bursts
-system.physmem.perBankRdBursts::4 24981 # Per bank write bursts
-system.physmem.perBankRdBursts::5 24976 # Per bank write bursts
+system.physmem.perBankRdBursts::3 25536 # Per bank write bursts
+system.physmem.perBankRdBursts::4 24982 # Per bank write bursts
+system.physmem.perBankRdBursts::5 24977 # Per bank write bursts
system.physmem.perBankRdBursts::6 24228 # Per bank write bursts
system.physmem.perBankRdBursts::7 24506 # Per bank write bursts
-system.physmem.perBankRdBursts::8 25159 # Per bank write bursts
-system.physmem.perBankRdBursts::9 24820 # Per bank write bursts
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system.physmem.perBankRdBursts::10 25363 # Per bank write bursts
-system.physmem.perBankRdBursts::11 24840 # Per bank write bursts
-system.physmem.perBankRdBursts::12 24420 # Per bank write bursts
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+system.physmem.perBankRdBursts::12 24418 # Per bank write bursts
system.physmem.perBankRdBursts::13 25388 # Per bank write bursts
system.physmem.perBankRdBursts::14 25795 # Per bank write bursts
-system.physmem.perBankRdBursts::15 25483 # Per bank write bursts
+system.physmem.perBankRdBursts::15 25481 # Per bank write bursts
system.physmem.perBankWrBursts::0 7550 # Per bank write bursts
system.physmem.perBankWrBursts::1 7529 # Per bank write bursts
system.physmem.perBankWrBursts::2 7880 # Per bank write bursts
system.physmem.perBankWrBursts::4 7115 # Per bank write bursts
system.physmem.perBankWrBursts::5 6983 # Per bank write bursts
system.physmem.perBankWrBursts::6 6321 # Per bank write bursts
-system.physmem.perBankWrBursts::7 6319 # Per bank write bursts
+system.physmem.perBankWrBursts::7 6315 # Per bank write bursts
system.physmem.perBankWrBursts::8 7293 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6554 # Per bank write bursts
+system.physmem.perBankWrBursts::9 6555 # Per bank write bursts
system.physmem.perBankWrBursts::10 7205 # Per bank write bursts
system.physmem.perBankWrBursts::11 6861 # Per bank write bursts
system.physmem.perBankWrBursts::12 6964 # Per bank write bursts
system.physmem.perBankWrBursts::14 7980 # Per bank write bursts
system.physmem.perBankWrBursts::15 7780 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
-system.physmem.totGap 1919426851000 # Total gap between requests
+system.physmem.numWrRetry 12 # Number of times write queue was full causing retry
+system.physmem.totGap 1919427104000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 401996 # Read request sizes (log2)
+system.physmem.readPktSize::6 401995 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 115735 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 401802 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 115732 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 401798 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::53 111 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 122 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 116 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 111 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 111 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 94 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 70 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 63869 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 518.585480 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 313.979775 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 413.923527 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 14875 23.29% 23.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 11515 18.03% 41.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 4721 7.39% 48.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3142 4.92% 53.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 3018 4.73% 58.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1863 2.92% 61.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1301 2.04% 63.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1404 2.20% 65.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 22030 34.49% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 63869 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5101 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 78.768477 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 2955.016496 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191 5098 99.94% 99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::44 189 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 216 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 208 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 201 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 197 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 176 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 132 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 105 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 93 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 101 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 109 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 112 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 113 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 91 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 72 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 62 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 35 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 63991 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 517.589786 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 312.394273 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 414.375602 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 15074 23.56% 23.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 11584 18.10% 41.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 4587 7.17% 48.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3091 4.83% 53.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 3045 4.76% 58.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1807 2.82% 61.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1323 2.07% 63.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1474 2.30% 65.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 22006 34.39% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 63991 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 5109 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 78.644353 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 2952.702952 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191 5106 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5101 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5101 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 22.683395 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 19.235797 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 21.276820 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 4452 87.28% 87.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 22 0.43% 87.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 15 0.29% 88.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 224 4.39% 92.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 41 0.80% 93.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 6 0.12% 93.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 9 0.18% 93.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 7 0.14% 93.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 19 0.37% 94.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 2 0.04% 94.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 4 0.08% 94.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 2 0.04% 94.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 11 0.22% 94.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 3 0.06% 94.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 7 0.14% 94.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 30 0.59% 95.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 13 0.25% 95.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 3 0.06% 95.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 1 0.02% 95.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 166 3.25% 98.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 10 0.20% 98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 2 0.04% 98.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 6 0.12% 99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 4 0.08% 99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 2 0.04% 99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 6 0.12% 99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 9 0.18% 99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 9 0.18% 99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151 1 0.02% 99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155 3 0.06% 99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 2 0.04% 99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 3 0.06% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167 1 0.02% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171 1 0.02% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::220-223 1 0.02% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227 4 0.08% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5101 # Writes before turning the bus around for reads
-system.physmem.totQLat 2117396500 # Total ticks spent queuing
-system.physmem.totMemAccLat 9651446500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2009080000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 5269.57 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 5109 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 5109 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 22.647289 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 19.199358 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 21.195525 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 4460 87.30% 87.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 21 0.41% 87.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 12 0.23% 87.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 224 4.38% 92.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 41 0.80% 93.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 20 0.39% 93.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 7 0.14% 93.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 6 0.12% 93.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 14 0.27% 94.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 4 0.08% 94.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 3 0.06% 94.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 1 0.02% 94.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 9 0.18% 94.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 5 0.10% 94.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 4 0.08% 94.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 25 0.49% 95.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 9 0.18% 95.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 15 0.29% 95.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 168 3.29% 98.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 2 0.04% 98.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 1 0.02% 98.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 2 0.04% 98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 1 0.02% 98.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 2 0.04% 98.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 8 0.16% 99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 5 0.10% 99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 5 0.10% 99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 9 0.18% 99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 13 0.25% 99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151 1 0.02% 99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155 1 0.02% 99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 2 0.04% 99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163 5 0.10% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175 1 0.02% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227 3 0.06% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 5109 # Writes before turning the bus around for reads
+system.physmem.totQLat 2129492750 # Total ticks spent queuing
+system.physmem.totMemAccLat 9663467750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2009060000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 5299.72 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 24019.57 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 24049.72 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 13.40 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 13.40 # Average system read bandwidth in MiByte/s
system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.42 # Average write queue length when enqueuing
-system.physmem.readRowHits 360116 # Number of row buffer hits during reads
-system.physmem.writeRowHits 93539 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 89.62 # Row buffer hit rate for reads
+system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing
+system.physmem.readRowHits 359991 # Number of row buffer hits during reads
+system.physmem.writeRowHits 93535 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 89.59 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 80.82 # Row buffer hit rate for writes
-system.physmem.avgGap 3707382.50 # Average gap between requests
-system.physmem.pageHitRate 87.65 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 1800046548500 # Time in different power states
+system.physmem.avgGap 3707411.64 # Average gap between requests
+system.physmem.pageHitRate 87.63 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 1800186005000 # Time in different power states
system.physmem.memoryStateTime::REF 64094160000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 55294756500 # Time in different power states
+system.physmem.memoryStateTime::ACT 55155300000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 17291227 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 292357 # Transaction distribution
system.membus.trans_dist::ReadResp 292357 # Transaction distribution
system.membus.trans_dist::WriteReq 9649 # Transaction distribution
system.membus.trans_dist::WriteResp 9649 # Transaction distribution
-system.membus.trans_dist::Writeback 74183 # Transaction distribution
+system.membus.trans_dist::Writeback 74180 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
system.membus.trans_dist::UpgradeReq 132 # Transaction distribution
system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
-system.membus.trans_dist::ReadExReq 116727 # Transaction distribution
-system.membus.trans_dist::ReadExResp 116727 # Transaction distribution
+system.membus.trans_dist::ReadExReq 116726 # Transaction distribution
+system.membus.trans_dist::ReadExResp 116726 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878409 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911567 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878404 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911562 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 994859 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30474496 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30519052 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 33179340 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 33179340 # Total data (bytes)
-system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 32375500 # Layer occupancy (ticks)
+system.membus.pkt_count::total 994854 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30474240 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30518796 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 33179084 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 158 # Total snoops (count)
+system.membus.snoop_fanout::samples 518029 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 518029 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 518029 # Request fanout histogram
+system.membus.reqLayer0.occupancy 30371000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 1450892000 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 1451093000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3751806368 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 3752017868 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 43113000 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 43114250 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 41685 # number of replacements
-system.iocache.tags.tagsinuse 1.344805 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 1.344808 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 1753524887000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide 1.344805 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide 0.084050 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.084050 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 1753524972000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide 1.344808 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide 0.084051 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.084051 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 375525 # Number of tag accesses
-system.iocache.tags.data_accesses 375525 # Number of data accesses
+system.iocache.tags.tag_accesses 375557 # Number of tag accesses
+system.iocache.tags.data_accesses 375557 # Number of data accesses
system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::tsunami.ide 4 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total 4 # number of WriteInvalidateReq misses
system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
system.iocache.demand_misses::total 173 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
system.iocache.overall_misses::total 173 # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles
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-system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles
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-system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles
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+system.iocache.overall_miss_latency::total 24523133 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
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-system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
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system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
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system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 141752.213873 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 141752.213873 # average ReadReq miss latency
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+system.iocache.overall_avg_miss_latency::total 141752.213873 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles
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-system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 15526633 # number of ReadReq MSHR miss cycles
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+system.iocache.demand_mshr_miss_latency::total 15526633 # number of demand (read+write) MSHR miss cycles
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+system.iocache.overall_mshr_miss_latency::total 15526633 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999904 # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999904 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency
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-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60323.698161 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 89749.323699 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60458.661533 # average WriteInvalidateReq mshr miss latency
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+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 9052614 # DTB read hits
-system.cpu.dtb.read_misses 10356 # DTB read misses
+system.cpu.dtb.read_hits 9052455 # DTB read hits
+system.cpu.dtb.read_misses 10357 # DTB read misses
system.cpu.dtb.read_acv 210 # DTB read access violations
-system.cpu.dtb.read_accesses 728915 # DTB read accesses
-system.cpu.dtb.write_hits 6349217 # DTB write hits
-system.cpu.dtb.write_misses 1144 # DTB write misses
+system.cpu.dtb.read_accesses 728916 # DTB read accesses
+system.cpu.dtb.write_hits 6349129 # DTB write hits
+system.cpu.dtb.write_misses 1143 # DTB write misses
system.cpu.dtb.write_acv 157 # DTB write access violations
-system.cpu.dtb.write_accesses 291933 # DTB write accesses
-system.cpu.dtb.data_hits 15401831 # DTB hits
+system.cpu.dtb.write_accesses 291932 # DTB write accesses
+system.cpu.dtb.data_hits 15401584 # DTB hits
system.cpu.dtb.data_misses 11500 # DTB misses
system.cpu.dtb.data_acv 367 # DTB access violations
system.cpu.dtb.data_accesses 1020848 # DTB accesses
-system.cpu.itb.fetch_hits 4974960 # ITB hits
+system.cpu.itb.fetch_hits 4974880 # ITB hits
system.cpu.itb.fetch_misses 5010 # ITB misses
system.cpu.itb.fetch_acv 184 # ITB acv
-system.cpu.itb.fetch_accesses 4979970 # ITB accesses
+system.cpu.itb.fetch_accesses 4979890 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.numCycles 3838877544 # number of cpu cycles simulated
+system.cpu.numCycles 3838878050 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 56102112 # Number of instructions committed
-system.cpu.committedOps 56102112 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 51977185 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
-system.cpu.num_func_calls 1481236 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 6460933 # number of instructions that are conditional controls
-system.cpu.num_int_insts 51977185 # number of integer instructions
-system.cpu.num_fp_insts 324460 # number of float instructions
-system.cpu.num_int_register_reads 71206533 # number of times the integer registers were read
-system.cpu.num_int_register_writes 38459103 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
-system.cpu.num_mem_refs 15454487 # number of memory refs
-system.cpu.num_load_insts 9089505 # Number of load instructions
-system.cpu.num_store_insts 6364982 # Number of store instructions
-system.cpu.num_idle_cycles 3587234430.998131 # Number of idle cycles
-system.cpu.num_busy_cycles 251643113.001869 # Number of busy cycles
-system.cpu.not_idle_fraction 0.065551 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.934449 # Percentage of idle cycles
-system.cpu.Branches 8412678 # Number of branches fetched
-system.cpu.op_class::No_OpClass 3197715 5.70% 5.70% # Class of executed instruction
-system.cpu.op_class::IntAlu 36172357 64.46% 70.16% # Class of executed instruction
-system.cpu.op_class::IntMult 61004 0.11% 70.27% # Class of executed instruction
+system.cpu.committedInsts 56102180 # Number of instructions committed
+system.cpu.committedOps 56102180 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 51977296 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 324326 # Number of float alu accesses
+system.cpu.num_func_calls 1481232 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 6461044 # number of instructions that are conditional controls
+system.cpu.num_int_insts 51977296 # number of integer instructions
+system.cpu.num_fp_insts 324326 # number of float instructions
+system.cpu.num_int_register_reads 71206831 # number of times the integer registers were read
+system.cpu.num_int_register_writes 38459262 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 163576 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 166452 # number of times the floating registers were written
+system.cpu.num_mem_refs 15454224 # number of memory refs
+system.cpu.num_load_insts 9089337 # Number of load instructions
+system.cpu.num_store_insts 6364887 # Number of store instructions
+system.cpu.num_idle_cycles 3587231475.998131 # Number of idle cycles
+system.cpu.num_busy_cycles 251646574.001869 # Number of busy cycles
+system.cpu.not_idle_fraction 0.065552 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.934448 # Percentage of idle cycles
+system.cpu.Branches 8412776 # Number of branches fetched
+system.cpu.op_class::No_OpClass 3197684 5.70% 5.70% # Class of executed instruction
+system.cpu.op_class::IntAlu 36172751 64.46% 70.16% # Class of executed instruction
+system.cpu.op_class::IntMult 60997 0.11% 70.27% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction
-system.cpu.op_class::FloatAdd 38087 0.07% 70.34% # Class of executed instruction
+system.cpu.op_class::FloatAdd 38083 0.07% 70.34% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction
-system.cpu.op_class::MemRead 9316582 16.60% 86.95% # Class of executed instruction
-system.cpu.op_class::MemWrite 6371054 11.35% 98.30% # Class of executed instruction
-system.cpu.op_class::IprAccess 953544 1.70% 100.00% # Class of executed instruction
+system.cpu.op_class::MemRead 9316413 16.60% 86.95% # Class of executed instruction
+system.cpu.op_class::MemWrite 6370959 11.35% 98.30% # Class of executed instruction
+system.cpu.op_class::IprAccess 953524 1.70% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 56113979 # Class of executed instruction
+system.cpu.op_class::total 56114047 # Class of executed instruction
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei 212019 # number of hwrei instructions executed
+system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei 212017 # number of hwrei instructions executed
system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl
system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 149118 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1857248521000 96.76% 96.76% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21 91287500 0.00% 96.76% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22 737179000 0.04% 96.80% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 61361050500 3.20% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1919438038000 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::0 1857251860000 96.76% 96.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21 91366000 0.00% 96.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22 736784000 0.04% 96.80% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 61358281000 3.20% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total 1919438291000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed
-system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
+system.cpu.kern.callpal::swpctx 4175 2.16% 2.17% # number of callpals executed
+system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
system.cpu.kern.callpal::swpipl 175949 91.22% 93.41% # number of callpals executed
system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed
system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.callpal::total 192894 # number of callpals executed
-system.cpu.kern.mode_switch::kernel 5902 # number of protection mode switches
+system.cpu.kern.callpal::total 192892 # number of callpals executed
+system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches
system.cpu.kern.mode_switch::user 1742 # number of protection mode switches
-system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
-system.cpu.kern.mode_good::kernel 1912
+system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches
+system.cpu.kern.mode_good::kernel 1911
system.cpu.kern.mode_good::user 1742
-system.cpu.kern.mode_good::idle 170
-system.cpu.kern.mode_switch_good::kernel 0.323958 # fraction of useful protection mode switches
+system.cpu.kern.mode_good::idle 169
+system.cpu.kern.mode_switch_good::kernel 0.323734 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total 0.392567 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 46116573000 2.40% 2.40% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 5192895500 0.27% 2.67% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1868128567500 97.33% 100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context 4178 # number of times the context was actually changed
+system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total 0.392443 # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel 46142250000 2.40% 2.40% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user 5192719000 0.27% 2.67% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle 1868103320000 97.33% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context 4176 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.iobus.throughput 1409873 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
-system.iobus.trans_dist::WriteReq 51201 # Transaction distribution
+system.iobus.trans_dist::WriteReq 51197 # Transaction distribution
system.iobus.trans_dist::WriteResp 51201 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 4 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes)
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-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56674.052112 # average ReadExReq mshr miss latency
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+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53795.675516 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54012.558149 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60355.649165 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53795.675516 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54012.558149 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 1390084 # number of replacements
+system.cpu.dcache.tags.replacements 1390025 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.978881 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 14030288 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1390596 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 10.089406 # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs 14030084 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1390537 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 10.089688 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.978881 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy
system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 63074137 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 63074137 # Number of data accesses
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-system.cpu.dcache.ReadReq_hits::total 7802568 # number of ReadReq hits
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-system.cpu.dcache.LoadLockedReq_hits::total 183034 # number of LoadLockedReq hits
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-system.cpu.dcache.StoreCondReq_hits::total 199227 # number of StoreCondReq hits
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-system.cpu.dcache.overall_avg_miss_latency::total 29055.226541 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120512 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120512 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049468 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049468 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085970 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085970 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.091427 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.091427 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25001.869504 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25001.869504 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33730.654123 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33730.654123 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11259.265176 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11259.265176 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26935.366419 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26935.366419 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26935.366419 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26935.366419 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 106562255 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 2021905 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2021888 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 2021774 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2021757 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 834526 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41563 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 834448 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41564 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 304190 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 304190 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856770 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3649068 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 5505838 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59416000 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142462412 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 201878412 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 201868428 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 2671296 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 2424407500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::ReadExReq 304189 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 304189 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856624 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648872 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 5505496 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59411328 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142453644 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 201864972 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 41913 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 3195062 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.013063 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.113544 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 3153325 98.69% 98.69% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 41737 1.31% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 3195062 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 2424224500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1395179500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1395050000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2186860632 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 2186768132 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.900855 # Number of seconds simulated
-sim_ticks 900854787500 # Number of ticks simulated
-final_tick 900854787500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.900830 # Number of seconds simulated
+sim_ticks 900829868000 # Number of ticks simulated
+final_tick 900829868000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 875862 # Simulator instruction rate (inst/s)
-host_op_rate 1055198 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 12821864647 # Simulator tick rate (ticks/s)
-host_mem_usage 433912 # Number of bytes of host memory used
-host_seconds 70.26 # Real time elapsed on the host
-sim_insts 61537412 # Number of instructions simulated
-sim_ops 74137396 # Number of ops (including micro ops) simulated
+host_inst_rate 1355321 # Simulator instruction rate (inst/s)
+host_op_rate 1632835 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 19839612971 # Simulator tick rate (ticks/s)
+host_mem_usage 467260 # Number of bytes of host memory used
+host_seconds 45.41 # Real time elapsed on the host
+sim_insts 61539136 # Number of instructions simulated
+sim_ops 74139862 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 460108 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 6580092 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 258564 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 2992120 # Number of bytes read from this memory
-system.physmem.bytes_read::total 49612932 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 460108 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 258564 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 718672 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4174784 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 3027048 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7201872 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 13417 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 102873 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 4131 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 46770 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 5082398 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 65231 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 756762 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 822003 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 43649210 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 284 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 213 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 510746 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 7304276 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 287021 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 3321423 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 55073173 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 510746 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 287021 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 797767 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4634247 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 3360195 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 44 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 7994487 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4634247 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 43649210 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 284 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 213 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 510746 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 10664471 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 287021 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 3321468 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 63067661 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 65740815 # Throughput (bytes/s)
-system.membus.data_through_bus 59222928 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 468620 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 6508860 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 266564 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 2938616 # Number of bytes read from this memory
+system.physmem.bytes_read::total 49504452 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 468620 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 266564 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 735184 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3365568 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 3027048 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6392656 # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 13550 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 101760 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 4256 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 45934 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 5080703 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 52587 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 756762 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 809359 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 43650418 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 71 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 142 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 520209 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 7225404 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 295909 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 3262121 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 54954275 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 520209 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 295909 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 816119 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3736075 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 3360288 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 44 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 7096408 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3736075 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 43650418 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 71 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 142 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 520209 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 10585693 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 295909 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 3262165 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 62050682 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 6129610 # Transaction distribution
+system.membus.trans_dist::ReadResp 6129610 # Transaction distribution
+system.membus.trans_dist::WriteReq 767040 # Transaction distribution
+system.membus.trans_dist::WriteResp 767040 # Transaction distribution
+system.membus.trans_dist::Writeback 52587 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 37380 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 20039 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 14449 # Transaction distribution
+system.membus.trans_dist::ReadExReq 163617 # Transaction distribution
+system.membus.trans_dist::ReadExResp 136674 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382414 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8564 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 682 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1995948 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 4387646 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 9830400 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 9830400 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 14218046 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2389580 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 17128 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1364 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16575508 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 18983656 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 39321600 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 39321600 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 58305256 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 295628 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 295628 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 295628 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 70256 # number of replacements
-system.l2c.tags.tagsinuse 51491.506872 # Cycle average of tags in use
-system.l2c.tags.total_refs 1633923 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 135467 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 12.061410 # Average number of references to valid blocks.
+system.l2c.tags.replacements 60014 # number of replacements
+system.l2c.tags.tagsinuse 50124.590156 # Cycle average of tags in use
+system.l2c.tags.total_refs 136044 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 120331 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 1.130581 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 39155.338647 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.673377 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001056 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 4830.605577 # Average occupied blocks per requestor
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+system.l2c.SCUpgradeReq_accesses::cpu0.data 714 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data 793 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 1507 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 100168 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 50523 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 150691 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 60 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 34 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 19288 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 147551 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 68 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 43 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 22698 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 63808 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 253550 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 60 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 34 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 19288 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 147551 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 68 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 43 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 22698 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 63808 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 253550 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.016667 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.058824 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.358098 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.199607 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.183232 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.111253 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.213934 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.963645 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.973870 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.968990 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.971989 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.974779 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total 0.973457 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.926803 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.880332 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.911222 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.016667 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.058824 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.358098 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.693279 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.183232 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.720207 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.628349 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.016667 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.058824 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.358098 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.693279 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.183232 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.720207 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.628349 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 65231 # number of writebacks
-system.l2c.writebacks::total 65231 # number of writebacks
+system.l2c.writebacks::writebacks 52587 # number of writebacks
+system.l2c.writebacks::total 52587 # number of writebacks
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.toL2Bus.throughput 156214740 # Throughput (bytes/s)
-system.toL2Bus.data_through_bus 140726796 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.iobus.throughput 46301771 # Throughput (bytes/s)
-system.iobus.data_through_bus 41711172 # Total data (bytes)
+system.toL2Bus.trans_dist::ReadReq 1357667 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 1357667 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 767040 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 767040 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 175673 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 37136 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 20079 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 57215 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 177634 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 177634 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 2263595 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 2631190 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 4894785 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 23563666 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 15087382 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 38651048 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 0 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 575784 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 575784 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 575784 # Request fanout histogram
+system.iobus.trans_dist::ReadReq 6098452 # Transaction distribution
+system.iobus.trans_dist::ReadResp 6098452 # Transaction distribution
+system.iobus.trans_dist::WriteReq 7955 # Transaction distribution
+system.iobus.trans_dist::WriteResp 7955 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30522 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7906 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 684 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 488 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2382414 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 9830400 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total 9830400 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 12212814 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40294 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15812 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 1368 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 268 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 2389580 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 39321600 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::total 39321600 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 41711180 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 7391669 # DTB read hits
-system.cpu0.dtb.read_misses 1915 # DTB read misses
-system.cpu0.dtb.write_hits 6659638 # DTB write hits
+system.cpu0.dtb.read_hits 7391828 # DTB read hits
+system.cpu0.dtb.read_misses 1916 # DTB read misses
+system.cpu0.dtb.write_hits 6659769 # DTB write hits
system.cpu0.dtb.write_misses 1130 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.prefetch_faults 84 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 185 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 7393584 # DTB read accesses
-system.cpu0.dtb.write_accesses 6660768 # DTB write accesses
+system.cpu0.dtb.read_accesses 7393744 # DTB read accesses
+system.cpu0.dtb.write_accesses 6660899 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 14051307 # DTB hits
-system.cpu0.dtb.misses 3045 # DTB misses
-system.cpu0.dtb.accesses 14054352 # DTB accesses
+system.cpu0.dtb.hits 14051597 # DTB hits
+system.cpu0.dtb.misses 3046 # DTB misses
+system.cpu0.dtb.accesses 14054643 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 37936012 # ITB inst hits
+system.cpu0.itb.inst_hits 37936653 # ITB inst hits
system.cpu0.itb.inst_misses 1207 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 37937219 # ITB inst accesses
-system.cpu0.itb.hits 37936012 # DTB hits
+system.cpu0.itb.inst_accesses 37937860 # ITB inst accesses
+system.cpu0.itb.hits 37936653 # DTB hits
system.cpu0.itb.misses 1207 # DTB misses
-system.cpu0.itb.accesses 37937219 # DTB accesses
-system.cpu0.numCycles 1801227301 # number of cpu cycles simulated
+system.cpu0.itb.accesses 37937860 # DTB accesses
+system.cpu0.numCycles 1801220958 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 37698803 # Number of instructions committed
-system.cpu0.committedOps 44946380 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 39863943 # Number of integer alu accesses
+system.cpu0.committedInsts 37699441 # Number of instructions committed
+system.cpu0.committedOps 44947195 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 39864660 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 4171 # Number of float alu accesses
-system.cpu0.num_func_calls 1205467 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4697957 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 39863943 # number of integer instructions
+system.cpu0.num_func_calls 1205511 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 4698026 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 39864660 # number of integer instructions
system.cpu0.num_fp_insts 4171 # number of float instructions
-system.cpu0.num_int_register_reads 70363299 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 26108579 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 70364659 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 26109079 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3915 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 256 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 134797325 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 18388517 # number of times the CC registers were written
-system.cpu0.num_mem_refs 14597479 # number of memory refs
-system.cpu0.num_load_insts 7571296 # Number of load instructions
-system.cpu0.num_store_insts 7026183 # Number of store instructions
-system.cpu0.num_idle_cycles 1756006001.161348 # Number of idle cycles
-system.cpu0.num_busy_cycles 45221299.838652 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.025106 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.974894 # Percentage of idle cycles
-system.cpu0.Branches 6054325 # Number of branches fetched
+system.cpu0.num_cc_register_reads 134799783 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 18388749 # number of times the CC registers were written
+system.cpu0.num_mem_refs 14597797 # number of memory refs
+system.cpu0.num_load_insts 7571468 # Number of load instructions
+system.cpu0.num_store_insts 7026329 # Number of store instructions
+system.cpu0.num_idle_cycles 1756040520.255098 # Number of idle cycles
+system.cpu0.num_busy_cycles 45180437.744902 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.025083 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.974917 # Percentage of idle cycles
+system.cpu0.Branches 6054439 # Number of branches fetched
system.cpu0.op_class::No_OpClass 13280 0.03% 0.03% # Class of executed instruction
-system.cpu0.op_class::IntAlu 30338974 67.42% 67.45% # Class of executed instruction
+system.cpu0.op_class::IntAlu 30339474 67.42% 67.45% # Class of executed instruction
system.cpu0.op_class::IntMult 51765 0.12% 67.56% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 67.56% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 67.56% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 67.56% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.56% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.56% # Class of executed instruction
-system.cpu0.op_class::MemRead 7571296 16.82% 84.39% # Class of executed instruction
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-system.cpu0.dcache.overall_hits::cpu0.data 12545680 # number of overall hits
-system.cpu0.dcache.overall_hits::total 12545680 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 173318 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 173318 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 159147 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 159147 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 50343 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 50343 # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9388 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 9388 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7646 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 7646 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 332465 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 332465 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 382808 # number of overall misses
-system.cpu0.dcache.overall_misses::total 382808 # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 7042193 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 7042193 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 5757208 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 5757208 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 458.751149 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.895998 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.895998 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024 310 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024 0.605469 # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses 26837769 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 26837769 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 6854480 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 6854480 # number of ReadReq hits
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+system.cpu0.dcache.WriteReq_hits::total 5591690 # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data 77211 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total 77211 # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 134223 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 134223 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 135188 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 135188 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 12446170 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 12446170 # number of demand (read+write) hits
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+system.cpu0.dcache.overall_hits::total 12523381 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 187851 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 187851 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 165642 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 165642 # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data 51876 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total 51876 # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10381 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 10381 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 8852 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 8852 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 353493 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 353493 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 405369 # number of overall misses
+system.cpu0.dcache.overall_misses::total 405369 # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 7042331 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 7042331 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 5757332 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 5757332 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 129087 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 129087 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 144583 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 144583 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144033 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 144033 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 12799401 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 12799401 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 12928488 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 12928488 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.024611 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.024611 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027643 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.027643 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.389993 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.389993 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064932 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064932 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053085 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053085 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025975 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.025975 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029610 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.029610 # miss rate for overall accesses
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 144604 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 144604 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144040 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 144040 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 12799663 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 12799663 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 12928750 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 12928750 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026675 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.026675 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028771 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.028771 # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.401869 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.401869 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.071789 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.071789 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.061455 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.061455 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027617 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.027617 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031354 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.031354 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 321785 # number of writebacks
-system.cpu0.dcache.writebacks::total 321785 # number of writebacks
+system.cpu0.dcache.writebacks::writebacks 323282 # number of writebacks
+system.cpu0.dcache.writebacks::total 323282 # number of writebacks
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.toL2Bus.trans_dist::ReadReq 689270 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 689270 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 763494 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 763494 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 323282 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 12769 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 8852 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 21621 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 152873 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 152873 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 706618 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2854542 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 4790 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 11848 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 3577798 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 22212896 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 49695730 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9580 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 23696 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 71941902 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 229047 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 1276029 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 5.135706 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.342476 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5 1102864 86.43% 86.43% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6 173165 13.57% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 1276029 # Request fanout histogram
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 6028686 # DTB read hits
-system.cpu1.dtb.read_misses 5403 # DTB read misses
-system.cpu1.dtb.write_hits 4781604 # DTB write hits
+system.cpu1.dtb.read_hits 6029083 # DTB read hits
+system.cpu1.dtb.read_misses 5405 # DTB read misses
+system.cpu1.dtb.write_hits 4781968 # DTB write hits
system.cpu1.dtb.write_misses 1104 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.prefetch_faults 185 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 6034089 # DTB read accesses
-system.cpu1.dtb.write_accesses 4782708 # DTB write accesses
+system.cpu1.dtb.read_accesses 6034488 # DTB read accesses
+system.cpu1.dtb.write_accesses 4783072 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 10810290 # DTB hits
-system.cpu1.dtb.misses 6507 # DTB misses
-system.cpu1.dtb.accesses 10816797 # DTB accesses
+system.cpu1.dtb.hits 10811051 # DTB hits
+system.cpu1.dtb.misses 6509 # DTB misses
+system.cpu1.dtb.accesses 10817560 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 24626141 # ITB inst hits
+system.cpu1.itb.inst_hits 24627232 # ITB inst hits
system.cpu1.itb.inst_misses 3166 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 24629307 # ITB inst accesses
-system.cpu1.itb.hits 24626141 # DTB hits
+system.cpu1.itb.inst_accesses 24630398 # ITB inst accesses
+system.cpu1.itb.hits 24627232 # DTB hits
system.cpu1.itb.misses 3166 # DTB misses
-system.cpu1.itb.accesses 24629307 # DTB accesses
-system.cpu1.numCycles 1801709576 # number of cpu cycles simulated
+system.cpu1.itb.accesses 24630398 # DTB accesses
+system.cpu1.numCycles 1801708036 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 23838609 # Number of instructions committed
-system.cpu1.committedOps 29191016 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 25547086 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 5650 # Number of float alu accesses
-system.cpu1.num_func_calls 987842 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 2987341 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 25547086 # number of integer instructions
-system.cpu1.num_fp_insts 5650 # number of float instructions
-system.cpu1.num_int_register_reads 48277330 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 17495174 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 3706 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 1948 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 86963152 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 11050350 # number of times the CC registers were written
-system.cpu1.num_mem_refs 11165955 # number of memory refs
-system.cpu1.num_load_insts 6206289 # Number of load instructions
-system.cpu1.num_store_insts 4959666 # Number of store instructions
-system.cpu1.num_idle_cycles 1771680344.893366 # Number of idle cycles
-system.cpu1.num_busy_cycles 30029231.106634 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.016667 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.983333 # Percentage of idle cycles
-system.cpu1.Branches 4459555 # Number of branches fetched
+system.cpu1.committedInsts 23839695 # Number of instructions committed
+system.cpu1.committedOps 29192667 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 25548618 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 5779 # Number of float alu accesses
+system.cpu1.num_func_calls 987959 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 2987443 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 25548618 # number of integer instructions
+system.cpu1.num_fp_insts 5779 # number of float instructions
+system.cpu1.num_int_register_reads 48280801 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 17496069 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 3771 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 2012 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 86968126 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 11050847 # number of times the CC registers were written
+system.cpu1.num_mem_refs 11166773 # number of memory refs
+system.cpu1.num_load_insts 6206724 # Number of load instructions
+system.cpu1.num_store_insts 4960049 # Number of store instructions
+system.cpu1.num_idle_cycles 1771724648.110516 # Number of idle cycles
+system.cpu1.num_busy_cycles 29983387.889484 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.016642 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.983358 # Percentage of idle cycles
+system.cpu1.Branches 4459767 # Number of branches fetched
system.cpu1.op_class::No_OpClass 15552 0.05% 0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu 18046643 61.66% 61.71% # Class of executed instruction
-system.cpu1.op_class::IntMult 40424 0.14% 61.85% # Class of executed instruction
+system.cpu1.op_class::IntAlu 18047467 61.65% 61.71% # Class of executed instruction
+system.cpu1.op_class::IntMult 40427 0.14% 61.85% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 61.85% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 61.85% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 61.85% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 61.85% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 61.85% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 1539 0.01% 61.85% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 1550 0.01% 61.85% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 61.85% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 61.85% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 61.85% # Class of executed instruction
-system.cpu1.op_class::MemRead 6206289 21.20% 83.06% # Class of executed instruction
-system.cpu1.op_class::MemWrite 4959666 16.94% 100.00% # Class of executed instruction
+system.cpu1.op_class::MemRead 6206724 21.20% 83.06% # Class of executed instruction
+system.cpu1.op_class::MemWrite 4960049 16.94% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 29270113 # Class of executed instruction
+system.cpu1.op_class::total 29271769 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
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-system.cpu1.dcache.WriteReq_hits::total 4543395 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 35603 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 35603 # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94939 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 94939 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 95657 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 95657 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 9155352 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 9155352 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 9190955 # number of overall hits
-system.cpu1.dcache.overall_hits::total 9190955 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 143554 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 143554 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 130048 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 130048 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 27770 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 27770 # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10527 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 10527 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9468 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 9468 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 273602 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 273602 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 301372 # number of overall misses
-system.cpu1.dcache.overall_misses::total 301372 # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 4755511 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 4755511 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 4673443 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 4673443 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.tags.tag_accesses 19727044 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 19727044 # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data 4592285 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 4592285 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 4538287 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 4538287 # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data 35329 # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total 35329 # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94231 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 94231 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 93873 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 93873 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 9130572 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 9130572 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 9165901 # number of overall hits
+system.cpu1.dcache.overall_hits::total 9165901 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 163656 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 163656 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 135550 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 135550 # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data 28044 # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total 28044 # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11201 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 11201 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 11227 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 11227 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 299206 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 299206 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 327250 # number of overall misses
+system.cpu1.dcache.overall_misses::total 327250 # number of overall misses
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 4755941 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 4755941 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 4673837 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 4673837 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 63373 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 63373 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105466 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 105466 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105125 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 105125 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 9428954 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 9428954 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 9492327 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 9492327 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.030187 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.030187 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027827 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.027827 # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.438199 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.438199 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.099814 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.099814 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.090064 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.090064 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029017 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.029017 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031749 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.031749 # miss rate for overall accesses
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105432 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 105432 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105100 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 105100 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 9429778 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 9429778 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 9493151 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 9493151 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034411 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.034411 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029002 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.029002 # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.442523 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.442523 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.106239 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.106239 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106822 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106822 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031730 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.031730 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034472 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.034472 # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 249941 # number of writebacks
-system.cpu1.dcache.writebacks::total 249941 # number of writebacks
+system.cpu1.dcache.writebacks::writebacks 209707 # number of writebacks
+system.cpu1.dcache.writebacks::total 209707 # number of writebacks
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.toL2Bus.trans_dist::ReadReq 1728836 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 1728836 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 3546 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 3546 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 209707 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 18773 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 11227 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 30000 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 116777 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 116777 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 797550 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 3132383 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12644 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 25448 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 3968025 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 25515060 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 36101346 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 25288 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50896 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 61692590 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 259574 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 1204043 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 5.188487 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.391100 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5 977097 81.15% 81.15% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6 226946 18.85% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 1204043 # Request fanout histogram
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
---------- Begin Simulation Statistics ----------
-sim_seconds 2.321351 # Number of seconds simulated
-sim_ticks 2321351025500 # Number of ticks simulated
-final_tick 2321351025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.321335 # Number of seconds simulated
+sim_ticks 2321335404000 # Number of ticks simulated
+final_tick 2321335404000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 818788 # Simulator instruction rate (inst/s)
-host_op_rate 985991 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 31464875718 # Simulator tick rate (ticks/s)
-host_mem_usage 430844 # Number of bytes of host memory used
-host_seconds 73.78 # Real time elapsed on the host
+host_inst_rate 1308981 # Simulator instruction rate (inst/s)
+host_op_rate 1576286 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 50301976363 # Simulator tick rate (ticks/s)
+host_mem_usage 455960 # Number of bytes of host memory used
+host_seconds 46.15 # Real time elapsed on the host
sim_insts 60406834 # Number of instructions simulated
sim_ops 72742429 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 110100480 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
system.physmem.num_writes::writebacks 57873 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory
system.physmem.num_writes::total 811827 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47429483 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.clcd 47429803 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 138 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 83 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 303882 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3907997 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51641582 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 303882 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 303882 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1595567 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1299164 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2894732 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1595567 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47429483 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 303884 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3908023 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51641930 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 303884 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 303884 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1595578 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1299173 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2894751 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1595578 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47429803 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 138 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 83 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 303882 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 5207161 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54536314 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 55568847 # Throughput (bytes/s)
-system.membus.data_through_bus 128994799 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.physmem.bw_total::cpu.inst 303884 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 5207196 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 54536681 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 14973631 # Transaction distribution
+system.membus.trans_dist::ReadResp 14973631 # Transaction distribution
+system.membus.trans_dist::WriteReq 763122 # Transaction distribution
+system.membus.trans_dist::WriteResp 763122 # Transaction distribution
+system.membus.trans_dist::Writeback 57873 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4517 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4517 # Transaction distribution
+system.membus.trans_dist::ReadExReq 131874 # Transaction distribution
+system.membus.trans_dist::ReadExResp 131874 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382824 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3360 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1892845 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4279041 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 27525120 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 27525120 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 31804161 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390127 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 6720 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16497448 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18894319 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 110100480 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 110100480 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 128994799 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 214751 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 214751 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 214751 # Request fanout histogram
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.iobus.throughput 48459111 # Throughput (bytes/s)
-system.iobus.data_through_bus 112490607 # Total data (bytes)
+system.iobus.trans_dist::ReadReq 14945841 # Transaction distribution
+system.iobus.trans_dist::ReadResp 14945841 # Transaction distribution
+system.iobus.trans_dist::WriteReq 8131 # Transaction distribution
+system.iobus.trans_dist::WriteResp 8131 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29952 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7900 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 476 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 984 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 732 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2382824 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 27525120 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total 27525120 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 29907944 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39247 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15800 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 952 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 1968 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 390 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 2390127 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 110100480 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::total 110100480 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 112490607 # Cumulative packet size per connected master and slave (bytes)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 13142244 # DTB read hits
+system.cpu.dtb.read_hits 13142243 # DTB read hits
system.cpu.dtb.read_misses 7297 # DTB read misses
system.cpu.dtb.write_hits 11216207 # DTB write hits
system.cpu.dtb.write_misses 2181 # DTB write misses
system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 13149541 # DTB read accesses
+system.cpu.dtb.read_accesses 13149540 # DTB read accesses
system.cpu.dtb.write_accesses 11218388 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 24358451 # DTB hits
+system.cpu.dtb.hits 24358450 # DTB hits
system.cpu.dtb.misses 9478 # DTB misses
-system.cpu.dtb.accesses 24367929 # DTB accesses
+system.cpu.dtb.accesses 24367928 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.itb.hits 61430007 # DTB hits
system.cpu.itb.misses 4471 # DTB misses
system.cpu.itb.accesses 61434478 # DTB accesses
-system.cpu.numCycles 4642702052 # number of cpu cycles simulated
+system.cpu.numCycles 4642753590 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 60406834 # Number of instructions committed
system.cpu.num_mem_refs 25221274 # number of memory refs
system.cpu.num_load_insts 13499937 # Number of load instructions
system.cpu.num_store_insts 11721337 # Number of store instructions
-system.cpu.num_idle_cycles 4568843017.980124 # Number of idle cycles
-system.cpu.num_busy_cycles 73859034.019877 # Number of busy cycles
-system.cpu.not_idle_fraction 0.015909 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.984091 # Percentage of idle cycles
+system.cpu.num_idle_cycles 4568976022.512934 # Number of idle cycles
+system.cpu.num_busy_cycles 73777567.487067 # Number of busy cycles
+system.cpu.not_idle_fraction 0.015891 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.984109 # Percentage of idle cycles
system.cpu.Branches 10298517 # Number of branches fetched
system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction
system.cpu.op_class::IntAlu 47536032 65.23% 65.27% # Class of executed instruction
system.cpu.op_class::total 72875708 # Class of executed instruction
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 82781 # number of quiesce instructions executed
-system.cpu.icache.tags.replacements 850515 # number of replacements
-system.cpu.icache.tags.tagsinuse 511.689593 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 60581740 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 851027 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 71.186625 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 5455017500 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 511.689593 # Average occupied blocks per requestor
+system.cpu.icache.tags.replacements 850504 # number of replacements
+system.cpu.icache.tags.tagsinuse 511.689630 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 60581751 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 851016 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 71.187558 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 5451547500 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 511.689630 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999394 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999394 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 62283794 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 62283794 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 60581740 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 60581740 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 60581740 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 60581740 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 60581740 # number of overall hits
-system.cpu.icache.overall_hits::total 60581740 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 851027 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 851027 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 851027 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 851027 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 851027 # number of overall misses
-system.cpu.icache.overall_misses::total 851027 # number of overall misses
+system.cpu.icache.tags.tag_accesses 62283783 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 62283783 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 60581751 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 60581751 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 60581751 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 60581751 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 60581751 # number of overall hits
+system.cpu.icache.overall_hits::total 60581751 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 851016 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 851016 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 851016 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 851016 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 851016 # number of overall misses
+system.cpu.icache.overall_misses::total 851016 # number of overall misses
system.cpu.icache.ReadReq_accesses::cpu.inst 61432767 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 61432767 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 61432767 # number of demand (read+write) accesses
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 62250 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 50006.834636 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 1669916 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse 50006.820137 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 1669876 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 127635 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 13.083527 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 2306278064000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 36897.866975 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.959775 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993971 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.476656 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 6090.537259 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.563017 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.avg_refs 13.083214 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 2306275686000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 36897.819647 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.959772 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993972 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.485209 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 6090.561537 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.563016 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107032 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.092934 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107033 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.092935 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.763044 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65380 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52125 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997620 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 17035648 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 17035648 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7541 # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses 17035355 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 17035355 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7540 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3151 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst 838793 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 366790 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1216275 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 592642 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 592642 # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst 838782 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 366774 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1216247 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 592630 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 592630 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 113706 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 113706 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 7541 # number of demand (read+write) hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 113709 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 113709 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker 7540 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 3151 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 838793 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 480496 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 1329981 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 7541 # number of overall hits
+system.cpu.l2cache.demand_hits::cpu.inst 838782 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 480483 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 1329956 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker 7540 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 3151 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 838793 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 480496 # number of overall hits
-system.cpu.l2cache.overall_hits::total 1329981 # number of overall hits
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system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 10608 # number of ReadReq misses
system.cpu.l2cache.overall_misses::cpu.inst 10608 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 143345 # number of overall misses
system.cpu.l2cache.overall_misses::total 153961 # number of overall misses
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7546 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_accesses::cpu.data 376661 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 1236762 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 592642 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 592642 # number of Writeback accesses(hits+misses)
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+system.cpu.l2cache.Writeback_accesses::writebacks 592630 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 592630 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2943 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2943 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 247180 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 247180 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7546 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::cpu.itb.walker 3154 # number of demand (read+write) accesses
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-system.cpu.l2cache.demand_accesses::cpu.data 623841 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 1483942 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7546 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses
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-system.cpu.l2cache.overall_accesses::cpu.data 623841 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 1483942 # number of overall (read+write) accesses
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+system.cpu.l2cache.overall_accesses::total 1483917 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000663 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000951 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012489 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026207 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.016565 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991165 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991165 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539987 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.539987 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539981 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.539981 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000663 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000951 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012489 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.229778 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.103751 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.229783 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.103753 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000663 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000951 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012489 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.229778 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.103751 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.229783 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.103753 # miss rate for overall accesses
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.writebacks::writebacks 57873 # number of writebacks
system.cpu.l2cache.writebacks::total 57873 # number of writebacks
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 623329 # number of replacements
+system.cpu.dcache.tags.replacements 623316 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.997018 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 21798545 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 623841 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 34.942469 # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs 21798557 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 623828 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 34.943217 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 21757000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997018 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 90313385 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 90313385 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 11240226 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 11240226 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 9961316 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 9961316 # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses 90313368 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 90313368 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 11240238 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 11240238 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 9961313 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 9961313 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 110856 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 110856 # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 236008 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 236008 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 236011 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 236011 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 247196 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 247196 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 21201542 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 21201542 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 21312398 # number of overall hits
-system.cpu.dcache.overall_hits::total 21312398 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 292030 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 292030 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 250123 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 250123 # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data 21201551 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 21201551 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 21312407 # number of overall hits
+system.cpu.dcache.overall_hits::total 21312407 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 292017 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 292017 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 250126 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 250126 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 73442 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 73442 # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 11189 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 11189 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 542153 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 542153 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 615595 # number of overall misses
-system.cpu.dcache.overall_misses::total 615595 # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data 11532256 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 11532256 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 11186 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 11186 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 542143 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 542143 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 615585 # number of overall misses
+system.cpu.dcache.overall_misses::total 615585 # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data 11532255 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 11532255 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10211439 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10211439 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 184298 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 247197 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247196 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 247196 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 21743695 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 21743695 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 21927993 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 21927993 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025323 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.025323 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024494 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.024494 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 21743694 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 21743694 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 21927992 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 21927992 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025322 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.025322 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.398496 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.398496 # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045263 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045263 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.024934 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.024934 # miss rate for demand accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045251 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045251 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.024933 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.024933 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.028073 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.028073 # miss rate for overall accesses
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 592642 # number of writebacks
-system.cpu.dcache.writebacks::total 592642 # number of writebacks
+system.cpu.dcache.writebacks::writebacks 592630 # number of writebacks
+system.cpu.dcache.writebacks::total 592630 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 59392167 # Throughput (bytes/s)
-system.cpu.toL2Bus.data_through_bus 137870067 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.trans_dist::ReadReq 2445766 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2445766 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 763122 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 763122 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 592630 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2943 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2943 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 247183 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 247183 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1715294 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5740322 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17852 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37190 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 7510658 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54491548 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83266131 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 35704 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74380 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 137867763 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 2097938 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 2097938 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 2097938 # Request fanout histogram
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
---------- Begin Simulation Statistics ----------
-sim_seconds 1.194312 # Number of seconds simulated
-sim_ticks 1194312178000 # Number of ticks simulated
-final_tick 1194312178000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.675181 # Number of seconds simulated
+sim_ticks 2675180779000 # Number of ticks simulated
+final_tick 2675180779000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 475403 # Simulator instruction rate (inst/s)
-host_op_rate 567868 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 9241250441 # Simulator tick rate (ticks/s)
-host_mem_usage 438040 # Number of bytes of host memory used
-host_seconds 129.24 # Real time elapsed on the host
-sim_insts 61439698 # Number of instructions simulated
-sim_ops 73389630 # Number of ops (including micro ops) simulated
+host_inst_rate 485184 # Simulator instruction rate (inst/s)
+host_op_rate 579312 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 20736099933 # Simulator tick rate (ticks/s)
+host_mem_usage 486856 # Number of bytes of host memory used
+host_seconds 129.01 # Real time elapsed on the host
+sim_insts 62593972 # Number of instructions simulated
+sim_ops 74737529 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 393932 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4710012 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 323460 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4796088 # Number of bytes read from this memory
-system.physmem.bytes_read::total 62128516 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 393932 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 323460 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 717392 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4097216 # Number of bytes written to this memory
+system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
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+system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
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+system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
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+system.realview.nvmem.bw_read::cpu1.inst 18 # Total read bandwidth from this memory (bytes/s)
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+system.realview.nvmem.bw_inst_read::cpu1.inst 18 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
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+system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
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system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
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-system.physmem.num_writes::total 820855 # Number of write requests responded to by this memory
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-system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_read::cpu0.data 3943703 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_read::total 52020332 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 329840 # Instruction read bandwidth from this memory (bytes/s)
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-system.physmem.bw_inst_read::total 600674 # Instruction read bandwidth from this memory (bytes/s)
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-system.physmem.bw_write::cpu0.data 14234 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 2520567 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 5965408 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3430607 # Total bandwidth to/from this memory (bytes/s)
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-system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s)
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-system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s)
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-system.physmem.bw_total::total 57985740 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 6654210 # Number of read requests accepted
-system.physmem.writeReqs 820855 # Number of write requests accepted
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-system.physmem.writeBursts 820855 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 425838464 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 30976 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7136448 # Total number of bytes written to DRAM
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-system.physmem.bytesWrittenSys 7124560 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 484 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 709321 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 12079 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 415236 # Per bank write bursts
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-system.physmem.perBankRdBursts::3 415658 # Per bank write bursts
-system.physmem.perBankRdBursts::4 422402 # Per bank write bursts
-system.physmem.perBankRdBursts::5 415506 # Per bank write bursts
-system.physmem.perBankRdBursts::6 415779 # Per bank write bursts
-system.physmem.perBankRdBursts::7 415682 # Per bank write bursts
-system.physmem.perBankRdBursts::8 416047 # Per bank write bursts
-system.physmem.perBankRdBursts::9 415577 # Per bank write bursts
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-system.physmem.perBankWrBursts::10 7000 # Per bank write bursts
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+system.physmem.mergedWrBursts 709695 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 15472 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 981539 # Per bank write bursts
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+system.physmem.perBankRdBursts::4 988300 # Per bank write bursts
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+system.physmem.perBankWrBursts::14 7034 # Per bank write bursts
+system.physmem.perBankWrBursts::15 6715 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 1194307723500 # Total gap between requests
+system.physmem.totGap 2675178052500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 6799 # Read request sizes (log2)
-system.physmem.readPktSize::3 6488089 # Read request sizes (log2)
+system.physmem.readPktSize::3 15532057 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 159322 # Read request sizes (log2)
+system.physmem.readPktSize::6 173431 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 756836 # Write request sizes (log2)
+system.physmem.writePktSize::2 757284 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 64019 # Write request sizes (log2)
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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-system.physmem.bytesPerActivate::samples 473292 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 914.815615 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 785.169464 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 288.643252 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 25022 5.29% 5.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 21566 4.56% 9.84% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::384-511 2391 0.51% 11.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2344 0.50% 12.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1629 0.34% 12.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 4093 0.86% 13.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 899 0.19% 13.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 409479 86.52% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 473292 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6481 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 1026.648974 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 26505.494009 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-65535 6473 99.88% 99.88% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.89% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6481 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6481 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.205215 # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::stdev 0.984217 # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::17 15 0.23% 40.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 3862 59.59% 99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 20 0.31% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 3 0.05% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6481 # Writes before turning the bus around for reads
-system.physmem.totQLat 170730095750 # Total ticks spent queuing
-system.physmem.totMemAccLat 295487458250 # Total ticks spent from burst creation until serviced by the DRAM
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-system.physmem.avgQLat 25659.32 # Average queueing delay per DRAM burst
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+system.physmem.rdPerTurnAround::7.60218e+06-7.86432e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44409.32 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 356.56 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 5.98 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 52.02 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 5.97 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 44770.26 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 375.85 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.75 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 50.61 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.74 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 2.83 # Data bus utilization in percentage
-system.physmem.busUtilRead 2.79 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 4.36 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.98 # Average write queue length when enqueuing
-system.physmem.readRowHits 6199598 # Number of row buffer hits during reads
-system.physmem.writeRowHits 92343 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 93.17 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 82.79 # Row buffer hit rate for writes
-system.physmem.avgGap 159772.22 # Average gap between requests
-system.physmem.pageHitRate 93.00 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 945808643750 # Time in different power states
-system.physmem.memoryStateTime::REF 39880620000 # Time in different power states
+system.physmem.busUtil 2.96 # Data bus utilization in percentage
+system.physmem.busUtilRead 2.94 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 6.50 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 26.70 # Average write queue length when enqueuing
+system.physmem.readRowHits 14689438 # Number of row buffer hits during reads
+system.physmem.writeRowHits 84116 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.29 # Row buffer hit rate for writes
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system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 208620525000 # Time in different power states
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system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
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-system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 60005732 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 7703348 # Transaction distribution
-system.membus.trans_dist::ReadResp 7703348 # Transaction distribution
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-system.membus.trans_dist::WriteResp 767581 # Transaction distribution
-system.membus.trans_dist::Writeback 64019 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 31325 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 17234 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 12079 # Transaction distribution
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-system.membus.trans_dist::ReadExResp 137066 # Transaction distribution
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+system.membus.trans_dist::UpgradeReq 56135 # Transaction distribution
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+system.membus.trans_dist::UpgradeResp 15472 # Transaction distribution
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system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
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-system.membus.pkt_count_system.l2c.mem_side::total 4364934 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes)
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-system.membus.pkt_count::total 17341062 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389989 # Cumulative packet size per connected master and slave (bytes)
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-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17348564 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total 19761065 # Cumulative packet size per connected master and slave (bytes)
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-system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 71665577 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 71665577 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1224785500 # Layer occupancy (ticks)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2098 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2043502 # Packet count per connected master and slave (bytes)
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system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
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-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27234976 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41362613 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 7152 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15780 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30036788 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39599456 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7388 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 21348 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 138285501 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 138285501 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 4606436 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 4757764712 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 1924888432 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 1752701680 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 4396499 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 8876994 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 2115350205 # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 2925844707 # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer8.occupancy 4326000 # Layer occupancy (ticks)
-system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer9.occupancy 9906999 # Layer occupancy (ticks)
-system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.throughput 45460895 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 7671423 # Transaction distribution
-system.iobus.trans_dist::ReadResp 7671423 # Transaction distribution
-system.iobus.trans_dist::WriteReq 7962 # Transaction distribution
-system.iobus.trans_dist::WriteResp 7962 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30548 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8040 # Packet count per connected master and slave (bytes)
+system.toL2Bus.trans_dist::ReadReq 1633013 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 1633009 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 769090 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 769090 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 208041 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 61292 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 23072 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 84364 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 39 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 39 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 23321 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 23321 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 2956029 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 2099720 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 5055749 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 25795270 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 15582958 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 41378228 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 171942 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 753795 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 753795 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 753795 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 2576673570 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 2390227339 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 1329617427 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 16716140 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16716140 # Transaction distribution
+system.iobus.trans_dist::WriteReq 8087 # Transaction distribution
+system.iobus.trans_dist::WriteResp 8087 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30962 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8820 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1044 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2382642 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 15358770 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40317 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16080 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 2389989 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 54294501 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 54294501 # Total data (bytes)
-system.iobus.reqLayer0.occupancy 21416000 # Layer occupancy (ticks)
+system.iobus.pkt_count_system.bridge.master::total 2384390 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 33448454 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40731 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17640 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2088 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 2392696 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 126648952 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 21726000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 4026000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 4416000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 376000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 528000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2374680000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.2 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 16364250250 # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization 1.4 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 15532032000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 2376303000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.iobus.respLayer1.occupancy 39178496115 # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 6063582 # DTB read hits
-system.cpu0.dtb.read_misses 3748 # DTB read misses
-system.cpu0.dtb.write_hits 5648980 # DTB write hits
-system.cpu0.dtb.write_misses 807 # DTB write misses
+system.cpu0.dtb.read_hits 7131006 # DTB read hits
+system.cpu0.dtb.read_misses 3644 # DTB read misses
+system.cpu0.dtb.write_hits 6127729 # DTB write hits
+system.cpu0.dtb.write_misses 663 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 1709 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 1893 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 116 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 6067330 # DTB read accesses
-system.cpu0.dtb.write_accesses 5649787 # DTB write accesses
+system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 7134650 # DTB read accesses
+system.cpu0.dtb.write_accesses 6128392 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 11712562 # DTB hits
-system.cpu0.dtb.misses 4555 # DTB misses
-system.cpu0.dtb.accesses 11717117 # DTB accesses
+system.cpu0.dtb.hits 13258735 # DTB hits
+system.cpu0.dtb.misses 4307 # DTB misses
+system.cpu0.dtb.accesses 13263042 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 29557926 # ITB inst hits
-system.cpu0.itb.inst_misses 2205 # ITB inst misses
+system.cpu0.itb.inst_hits 31182741 # ITB inst hits
+system.cpu0.itb.inst_misses 2176 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1181 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1281 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 29560131 # ITB inst accesses
-system.cpu0.itb.hits 29557926 # DTB hits
-system.cpu0.itb.misses 2205 # DTB misses
-system.cpu0.itb.accesses 29560131 # DTB accesses
-system.cpu0.numCycles 2388624356 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 31184917 # ITB inst accesses
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+system.cpu0.itb.misses 2176 # DTB misses
+system.cpu0.itb.accesses 31184917 # DTB accesses
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 28859743 # Number of instructions committed
-system.cpu0.committedOps 34624628 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 30439288 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
-system.cpu0.num_func_calls 1241573 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4174263 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 30439288 # number of integer instructions
-system.cpu0.num_fp_insts 3860 # number of float instructions
-system.cpu0.num_int_register_reads 53589242 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 19764786 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 123695766 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 15045730 # number of times the CC registers were written
-system.cpu0.num_mem_refs 12225186 # number of memory refs
-system.cpu0.num_load_insts 6245915 # Number of load instructions
-system.cpu0.num_store_insts 5979271 # Number of store instructions
-system.cpu0.num_idle_cycles 2246427873.598119 # Number of idle cycles
-system.cpu0.num_busy_cycles 142196482.401881 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.059531 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.940469 # Percentage of idle cycles
-system.cpu0.Branches 5599312 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 14563 0.04% 0.04% # Class of executed instruction
-system.cpu0.op_class::IntAlu 22957352 65.14% 65.18% # Class of executed instruction
-system.cpu0.op_class::IntMult 43755 0.12% 65.31% # Class of executed instruction
-system.cpu0.op_class::IntDiv 0 0.00% 65.31% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 65.31% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 65.31% # Class of executed instruction
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-system.cpu0.op_class::FloatMult 0 0.00% 65.31% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 65.31% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 65.31% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 65.31% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 65.31% # Class of executed instruction
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-system.cpu0.op_class::SimdCmp 0 0.00% 65.31% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 65.31% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 65.31% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 65.31% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 65.31% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 65.31% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.31% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 65.31% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.31% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.31% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.31% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.31% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.31% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 692 0.00% 65.31% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 65.31% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.31% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.31% # Class of executed instruction
-system.cpu0.op_class::MemRead 6245915 17.72% 83.03% # Class of executed instruction
-system.cpu0.op_class::MemWrite 5979271 16.97% 100.00% # Class of executed instruction
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+system.cpu0.num_conditional_control_insts 3957686 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 32859018 # number of integer instructions
+system.cpu0.num_fp_insts 5449 # number of float instructions
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+system.cpu0.num_cc_register_reads 133610661 # number of times the CC registers were read
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+system.cpu0.idle_fraction 0.915654 # Percentage of idle cycles
+system.cpu0.Branches 5660514 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 16321 0.04% 0.04% # Class of executed instruction
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system.cpu0.kern.inst.arm 0 # number of arm instructions executed
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-system.cpu0.icache.tags.avg_refs 68.436920 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 75988011000 # Cycle when the warmup percentage was hit.
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system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.dcache.tags.replacements 355829 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 496.967445 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 11721464 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 356159 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 32.910762 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 767187000 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 305747 # number of writebacks
-system.cpu0.dcache.writebacks::total 305747 # number of writebacks
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-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11115.192960 # average ReadReq mshr miss latency
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-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17597.649006 # average SoftPFReq mshr miss latency
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+system.cpu0.dcache.writebacks::total 286365 # number of writebacks
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+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030577 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.030434 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.030434 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.363553 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.363553 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064162 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064162 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.068214 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.068214 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030504 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.030504 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.034153 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.034153 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 9921.312659 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 9921.312659 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12883.059772 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12883.059772 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14870.892540 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14870.892540 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14776.624119 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14776.624119 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21331.763984 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21331.763984 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11427.704834 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11427.704834 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11829.277347 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11829.277347 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.toL2Bus.trans_dist::ReadReq 1907557 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 1767698 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 12543 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 12543 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 286363 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 331583 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 53089 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 23925 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 60027 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 17 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 39 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 171374 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 163301 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 753056 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 3449820 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 6852 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 13348 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 4223076 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 23690016 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 48159078 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10080 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 19848 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 71879022 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 631972 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 1656253 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 5.339000 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.473370 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5 1094784 66.10% 66.10% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6 561469 33.90% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 1656253 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 1405252745 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 72604500 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer0.occupancy 563408502 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer1.occupancy 1726182117 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer2.occupancy 4332000 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer3.occupancy 8386000 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 7408792 # DTB read hits
-system.cpu1.dtb.read_misses 3640 # DTB read misses
-system.cpu1.dtb.write_hits 5825509 # DTB write hits
-system.cpu1.dtb.write_misses 1435 # DTB write misses
+system.cpu1.dtb.read_hits 6599972 # DTB read hits
+system.cpu1.dtb.read_misses 3720 # DTB read misses
+system.cpu1.dtb.write_hits 5539858 # DTB write hits
+system.cpu1.dtb.write_misses 1581 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1866 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 1672 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 123 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 7412432 # DTB read accesses
-system.cpu1.dtb.write_accesses 5826944 # DTB write accesses
+system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 6603692 # DTB read accesses
+system.cpu1.dtb.write_accesses 5541439 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 13234301 # DTB hits
-system.cpu1.dtb.misses 5075 # DTB misses
-system.cpu1.dtb.accesses 13239376 # DTB accesses
+system.cpu1.dtb.hits 12139830 # DTB hits
+system.cpu1.dtb.misses 5301 # DTB misses
+system.cpu1.dtb.accesses 12145131 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 33190882 # ITB inst hits
-system.cpu1.itb.inst_misses 2171 # ITB inst misses
+system.cpu1.itb.inst_hits 32728613 # ITB inst hits
+system.cpu1.itb.inst_misses 2200 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1276 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1176 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 33193053 # ITB inst accesses
-system.cpu1.itb.hits 33190882 # DTB hits
-system.cpu1.itb.misses 2171 # DTB misses
-system.cpu1.itb.accesses 33193053 # DTB accesses
-system.cpu1.numCycles 2387219429 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 32730813 # ITB inst accesses
+system.cpu1.itb.hits 32728613 # DTB hits
+system.cpu1.itb.misses 2200 # DTB misses
+system.cpu1.itb.accesses 32730813 # DTB accesses
+system.cpu1.numCycles 5350361558 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 32579955 # Number of instructions committed
-system.cpu1.committedOps 38765002 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 35167643 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
-system.cpu1.num_func_calls 962341 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 3529676 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 35167643 # number of integer instructions
-system.cpu1.num_fp_insts 6793 # number of float instructions
-system.cpu1.num_int_register_reads 64976079 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 23977665 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 139669414 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 14465628 # number of times the CC registers were written
-system.cpu1.num_mem_refs 13620676 # number of memory refs
-system.cpu1.num_load_insts 7578910 # Number of load instructions
-system.cpu1.num_store_insts 6041766 # Number of store instructions
-system.cpu1.num_idle_cycles 1873842319.884373 # Number of idle cycles
-system.cpu1.num_busy_cycles 513377109.115627 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.215052 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.784948 # Percentage of idle cycles
-system.cpu1.Branches 4944984 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 14265 0.04% 0.04% # Class of executed instruction
-system.cpu1.op_class::IntAlu 25564023 65.13% 65.17% # Class of executed instruction
-system.cpu1.op_class::IntMult 50133 0.13% 65.29% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 65.29% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 65.29% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 65.29% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 65.29% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 65.29% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 65.29% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 65.29% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 65.29% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 65.29% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 65.29% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 65.29% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 65.29% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 65.29% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 65.29% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 65.29% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 65.29% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.29% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 65.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 1482 0.00% 65.30% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 65.30% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.30% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.30% # Class of executed instruction
-system.cpu1.op_class::MemRead 7578910 19.31% 84.61% # Class of executed instruction
-system.cpu1.op_class::MemWrite 6041766 15.39% 100.00% # Class of executed instruction
+system.cpu1.committedInsts 32086754 # Number of instructions committed
+system.cpu1.committedOps 37934299 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 33961237 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses
+system.cpu1.num_func_calls 973285 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 3888456 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 33961237 # number of integer instructions
+system.cpu1.num_fp_insts 4436 # number of float instructions
+system.cpu1.num_int_register_reads 60527961 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 22681940 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 134686779 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 15567897 # number of times the CC registers were written
+system.cpu1.num_mem_refs 12531559 # number of memory refs
+system.cpu1.num_load_insts 6744563 # Number of load instructions
+system.cpu1.num_store_insts 5786996 # Number of store instructions
+system.cpu1.num_idle_cycles 5182201093.372063 # Number of idle cycles
+system.cpu1.num_busy_cycles 168160464.627937 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.031430 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.968570 # Percentage of idle cycles
+system.cpu1.Branches 5094014 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 12501 0.03% 0.03% # Class of executed instruction
+system.cpu1.op_class::IntAlu 25826807 67.22% 67.25% # Class of executed instruction
+system.cpu1.op_class::IntMult 50699 0.13% 67.38% # Class of executed instruction
+system.cpu1.op_class::IntDiv 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 745 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.38% # Class of executed instruction
+system.cpu1.op_class::MemRead 6744563 17.55% 84.94% # Class of executed instruction
+system.cpu1.op_class::MemWrite 5786996 15.06% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 39250579 # Class of executed instruction
+system.cpu1.op_class::total 38422311 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 44258 # number of quiesce instructions executed
-system.cpu1.icache.tags.replacements 469324 # number of replacements
-system.cpu1.icache.tags.tagsinuse 478.642267 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 32721042 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 469836 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 69.643539 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 93149552500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.642267 # Average occupied blocks per requestor
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+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.069348 # mshr miss rate for ReadReq accesses
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+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.251119 # mshr miss rate for ReadReq accesses
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+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.938411 # mshr miss rate for UpgradeReq accesses
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+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.935255 # mshr miss rate for SCUpgradeReq accesses
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+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.234845 # mshr miss rate for demand accesses
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+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.069348 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.014936 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.234845 # mshr miss rate for overall accesses
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+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 24494.520499 # average ReadReq mshr miss latency
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+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 51048.255365 # average HardPFReq mshr miss latency
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+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16263.259832 # average UpgradeReq mshr miss latency
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+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 26663.835843 # average ReadExReq mshr miss latency
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+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 24494.520499 # average overall mshr miss latency
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+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12934.911243 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 24494.520499 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 20934.463207 # average overall mshr miss latency
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+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
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+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dcache.tags.replacements 313601 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 474.302028 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 10949850 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 314113 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 34.859589 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 76456711000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.302028 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.926371 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.926371 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1 287 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses 22948274 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 22948274 # Number of data accesses
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+system.cpu1.dcache.ReadReq_hits::total 6183420 # number of ReadReq hits
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+system.cpu1.dcache.SoftPFReq_hits::total 19290 # number of SoftPFReq hits
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+system.cpu1.dcache.StoreCondReq_hits::total 75753 # number of StoreCondReq hits
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+system.cpu1.dcache.overall_hits::total 10761460 # number of overall hits
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+system.cpu1.dcache.ReadReq_misses::total 187243 # number of ReadReq misses
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+system.cpu1.dcache.WriteReq_misses::total 134937 # number of WriteReq misses
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+system.cpu1.dcache.SoftPFReq_misses::total 43327 # number of SoftPFReq misses
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+system.cpu1.dcache.LoadLockedReq_misses::total 12089 # number of LoadLockedReq misses
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+system.cpu1.dcache.StoreCondReq_misses::total 13673 # number of StoreCondReq misses
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+system.cpu1.dcache.demand_misses::total 322180 # number of demand (read+write) misses
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+system.cpu1.dcache.overall_misses::total 365507 # number of overall misses
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+system.cpu1.dcache.ReadReq_miss_latency::total 2299329756 # number of ReadReq miss cycles
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+system.cpu1.dcache.StoreCondReq_miss_latency::total 317344970 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 524000 # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total 524000 # number of StoreCondFailReq miss cycles
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+system.cpu1.dcache.demand_miss_latency::total 4809305384 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 4809305384 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 4809305384 # number of overall miss cycles
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+system.cpu1.dcache.ReadReq_accesses::total 6370663 # number of ReadReq accesses(hits+misses)
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+system.cpu1.dcache.WriteReq_accesses::total 4693687 # number of WriteReq accesses(hits+misses)
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+system.cpu1.dcache.SoftPFReq_accesses::total 62617 # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89491 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 89491 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89426 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 89426 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 11064350 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 11064350 # number of demand (read+write) accesses
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+system.cpu1.dcache.overall_accesses::total 11126967 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029391 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.029391 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028749 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.028749 # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.691937 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.691937 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135086 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135086 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.152897 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.152897 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029119 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.029119 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032849 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.032849 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12279.923714 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12279.923714 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18601.092569 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 18601.092569 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18035.734966 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18035.734966 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23209.607987 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23209.607987 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14927.386504 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 14927.386504 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13157.902267 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 13157.902267 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 264973 # number of writebacks
-system.cpu1.dcache.writebacks::total 264973 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 379 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 379 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 2067 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 2067 # number of WriteReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 2446 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 2446 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 2446 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 2446 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 143674 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 143674 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150015 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 150015 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 26855 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 26855 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11222 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11222 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10062 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 10062 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 293689 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 293689 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 320544 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 320544 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1427169251 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1427169251 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6022199670 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6022199670 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 445093004 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 445093004 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73834751 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 73834751 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31881029 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31881029 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7449368921 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 7449368921 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7894461925 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 7894461925 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168604609000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168604609000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25187299088 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25187299088 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193791908088 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193791908088 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023361 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023361 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030153 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030153 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.417275 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.417275 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120462 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120462 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108461 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108461 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026398 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.026398 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.028646 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.028646 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9933.385658 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9933.385658 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40143.983402 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40143.983402 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16573.934239 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16573.934239 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6579.464534 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6579.464534 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3168.458458 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3168.458458 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25364.821022 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25364.821022 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24628.325363 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24628.325363 # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 225255 # number of writebacks
+system.cpu1.dcache.writebacks::total 225255 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 794 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 794 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 3242 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 3242 # number of WriteReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 4036 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 4036 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 4036 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 4036 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 186449 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 186449 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 131695 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 131695 # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 27821 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total 27821 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12089 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12089 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 13671 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 13671 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 318144 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 318144 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 345965 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 345965 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1916001744 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1916001744 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2027549872 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2027549872 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 596503999 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 596503999 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 193851000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 193851000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 289002030 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 289002030 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 494000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 494000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3943551616 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 3943551616 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4540055615 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 4540055615 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 12848996742 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 12848996742 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 34213847345 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34213847345 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 47062844087 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 47062844087 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029267 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029267 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028058 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028058 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.444304 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.444304 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.135086 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.135086 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.152875 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.152875 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028754 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.028754 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031092 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.031092 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10276.277931 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10276.277931 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15395.799932 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15395.799932 # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21440.782107 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21440.782107 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16035.321367 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16035.321367 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21139.787141 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21139.787141 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12395.492657 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12395.492657 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13122.875479 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13122.875479 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.toL2Bus.trans_dist::ReadReq 957719 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 715905 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 756547 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 756547 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 225255 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 189199 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 53977 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 23970 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 50977 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 39 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 119927 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 111476 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 751552 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 2675268 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6827 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16819 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 3450466 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 24038516 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 40612602 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9748 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 25768 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 64686634 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 549743 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 1492746 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 5.338347 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.473147 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5 987680 66.17% 66.17% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6 505066 33.83% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 1492746 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 1514414783 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 42402999 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer0.occupancy 563804260 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer1.occupancy 984220768 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer2.occupancy 4390000 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer3.occupancy 10377250 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 745112259250 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 745112259250 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 745112259250 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 745112259250 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1782387791115 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1782387791115 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1782387791115 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1782387791115 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 2.614581 # Number of seconds simulated
-sim_ticks 2614581252500 # Number of ticks simulated
-final_tick 2614581252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.614572 # Number of seconds simulated
+sim_ticks 2614571564500 # Number of ticks simulated
+final_tick 2614571564500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 331710 # Simulator instruction rate (inst/s)
-host_op_rate 396174 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 14409825510 # Simulator tick rate (ticks/s)
-host_mem_usage 433940 # Number of bytes of host memory used
-host_seconds 181.44 # Real time elapsed on the host
-sim_insts 60186875 # Number of instructions simulated
-sim_ops 71883476 # Number of ops (including micro ops) simulated
+host_inst_rate 536806 # Simulator instruction rate (inst/s)
+host_op_rate 641128 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 23319189669 # Simulator tick rate (ticks/s)
+host_mem_usage 459056 # Number of bytes of host memory used
+host_seconds 112.12 # Real time elapsed on the host
+sim_insts 60187274 # Number of instructions simulated
+sim_ops 71883961 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 704520 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9109080 # Number of bytes read from this memory
-system.physmem.bytes_read::total 132497440 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 704520 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 704520 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3720512 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 704648 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9109336 # Number of bytes read from this memory
+system.physmem.bytes_read::total 132497824 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 704648 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 704648 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3720832 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6736584 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6736904 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142355 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15495006 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 58133 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 17222 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142359 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15495012 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 58138 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 812151 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 46922769 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 812156 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 46922943 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 269458 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3483954 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 50676352 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 269458 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 269458 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1422986 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1153558 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2576544 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1422986 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 46922769 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 269508 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3484065 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 50676687 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 269508 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 269508 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1423113 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1153563 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2576676 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1423113 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 46922943 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 269458 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4637512 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53252896 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15495006 # Number of read requests accepted
-system.physmem.writeReqs 812151 # Number of write requests accepted
-system.physmem.readBursts 15495006 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 812151 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 991553920 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 126464 # Total number of bytes read from write queue
-system.physmem.bytesWritten 6744512 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 132497440 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 6736584 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 1976 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 706747 # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_total::cpu.inst 269508 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4637627 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53253363 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15495012 # Number of read requests accepted
+system.physmem.writeReqs 812156 # Number of write requests accepted
+system.physmem.readBursts 15495012 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 812156 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 991563904 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 116864 # Total number of bytes read from write queue
+system.physmem.bytesWritten 6748800 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 132497824 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 6736904 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 1826 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 706685 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 4511 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 968147 # Per bank write bursts
+system.physmem.perBankRdBursts::0 968097 # Per bank write bursts
system.physmem.perBankRdBursts::1 967810 # Per bank write bursts
system.physmem.perBankRdBursts::2 967673 # Per bank write bursts
system.physmem.perBankRdBursts::3 967915 # Per bank write bursts
-system.physmem.perBankRdBursts::4 974375 # Per bank write bursts
-system.physmem.perBankRdBursts::5 968054 # Per bank write bursts
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system.physmem.perBankRdBursts::6 967653 # Per bank write bursts
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-system.physmem.perBankRdBursts::8 968459 # Per bank write bursts
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system.physmem.perBankRdBursts::9 968209 # Per bank write bursts
system.physmem.perBankRdBursts::10 967967 # Per bank write bursts
system.physmem.perBankRdBursts::11 967960 # Per bank write bursts
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system.physmem.perBankRdBursts::14 967953 # Per bank write bursts
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-system.physmem.perBankWrBursts::0 6652 # Per bank write bursts
-system.physmem.perBankWrBursts::1 6388 # Per bank write bursts
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-system.physmem.perBankWrBursts::8 7007 # Per bank write bursts
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+system.physmem.perBankWrBursts::6 6659 # Per bank write bursts
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+system.physmem.perBankWrBursts::8 7028 # Per bank write bursts
system.physmem.perBankWrBursts::9 6769 # Per bank write bursts
system.physmem.perBankWrBursts::10 6571 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6647 # Per bank write bursts
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system.physmem.perBankWrBursts::12 6565 # Per bank write bursts
-system.physmem.perBankWrBursts::13 6381 # Per bank write bursts
-system.physmem.perBankWrBursts::14 6555 # Per bank write bursts
-system.physmem.perBankWrBursts::15 6466 # Per bank write bursts
+system.physmem.perBankWrBursts::13 6383 # Per bank write bursts
+system.physmem.perBankWrBursts::14 6560 # Per bank write bursts
+system.physmem.perBankWrBursts::15 6462 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2614576987500 # Total gap between requests
+system.physmem.totGap 2614567301000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 6644 # Read request sizes (log2)
system.physmem.readPktSize::3 15335434 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 152928 # Read request sizes (log2)
+system.physmem.readPktSize::6 152934 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 754018 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 58133 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1126497 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 970808 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1027240 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 971.825895 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 905.842120 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 203.903622 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 22776 2.22% 2.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 22448 2.19% 4.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 8450 0.82% 5.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2555 0.25% 5.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2575 0.25% 5.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1819 0.18% 5.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 8664 0.84% 6.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 942 0.09% 6.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 957011 93.16% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1027240 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6120 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 2531.539869 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 116318.280129 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-524287 6115 99.92% 99.92% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 1027284 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 971.798163 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 905.747967 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 203.998959 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 22800 2.22% 2.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 22532 2.19% 4.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 8422 0.82% 5.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2556 0.25% 5.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2545 0.25% 5.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1785 0.17% 5.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 8607 0.84% 6.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 981 0.10% 6.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 957056 93.16% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1027284 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6124 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 2529.911822 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 116281.505657 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287 6119 99.92% 99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::524288-1.04858e+06 3 0.05% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6120 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6120 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.219444 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.191199 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.977796 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 2386 38.99% 38.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 19 0.31% 39.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 3702 60.49% 99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 12 0.20% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6120 # Writes before turning the bus around for reads
-system.physmem.totQLat 400457727500 # Total ticks spent queuing
-system.physmem.totMemAccLat 690952040000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 77465150000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 25847.61 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 6124 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6124 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.219138 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.190607 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 0.983110 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 2397 39.14% 39.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 24 0.39% 39.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 3669 59.91% 99.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 32 0.52% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 2 0.03% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6124 # Writes before turning the bus around for reads
+system.physmem.totQLat 400730693500 # Total ticks spent queuing
+system.physmem.totMemAccLat 691227931000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 77465930000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 25864.96 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44597.61 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 379.24 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 44614.96 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 379.25 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.58 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 50.68 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.58 # Average system write bandwidth in MiByte/s
system.physmem.busUtil 2.98 # Data bus utilization in percentage
system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 6.67 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 26.38 # Average write queue length when enqueuing
-system.physmem.readRowHits 14482583 # Number of row buffer hits during reads
-system.physmem.writeRowHits 88590 # Number of row buffer hits during writes
+system.physmem.avgRdQLen 6.80 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 28.13 # Average write queue length when enqueuing
+system.physmem.readRowHits 14482679 # Number of row buffer hits during reads
+system.physmem.writeRowHits 88673 # Number of row buffer hits during writes
system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 84.05 # Row buffer hit rate for writes
-system.physmem.avgGap 160333.10 # Average gap between requests
+system.physmem.writeRowHitRate 84.07 # Row buffer hit rate for writes
+system.physmem.avgGap 160332.39 # Average gap between requests
system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2239817846000 # Time in different power states
-system.physmem.memoryStateTime::REF 87306440000 # Time in different power states
+system.physmem.memoryStateTime::IDLE 2239359524750 # Time in different power states
+system.physmem.memoryStateTime::REF 87306180000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 287452006500 # Time in different power states
+system.physmem.memoryStateTime::ACT 287902801500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 54170150 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 16546653 # Transaction distribution
-system.membus.trans_dist::ReadResp 16546653 # Transaction distribution
+system.membus.trans_dist::ReadReq 16546657 # Transaction distribution
+system.membus.trans_dist::ReadResp 16546657 # Transaction distribution
system.membus.trans_dist::WriteReq 763381 # Transaction distribution
system.membus.trans_dist::WriteResp 763381 # Transaction distribution
-system.membus.trans_dist::Writeback 58133 # Transaction distribution
+system.membus.trans_dist::Writeback 58138 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4511 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution
-system.membus.trans_dist::ReadExReq 132457 # Transaction distribution
-system.membus.trans_dist::ReadExResp 132457 # Transaction distribution
+system.membus.trans_dist::ReadExReq 132459 # Transaction distribution
+system.membus.trans_dist::ReadExResp 132459 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383082 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3840 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1894355 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4281289 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1894372 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4281306 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 34952137 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390530 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7680 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16550632 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18948866 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 141632258 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 141632258 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1207280500 # Layer occupancy (ticks)
+system.membus.pkt_count::total 34952154 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390530 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7680 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16551336 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18949570 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 141632962 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 215583 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 215583 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 215583 # Request fanout histogram
+system.membus.reqLayer0.occupancy 1204828500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3534000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 3334000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer6.occupancy 17916889500 # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy 17917176000 # Layer occupancy (ticks)
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4952195664 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 4952454428 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 37921268500 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 37912905250 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.iobus.throughput 47837076 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 16518783 # Transaction distribution
system.iobus.trans_dist::ReadResp 16518783 # Transaction distribution
system.iobus.trans_dist::WriteReq 8182 # Transaction distribution
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 33053930 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1064 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2080 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 2390530 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 125073922 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 125073922 # Total data (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1064 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2080 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 2390530 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 125073922 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 15335424000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
system.iobus.respLayer0.occupancy 2374900000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 38692913500 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 38695381750 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 13160128 # DTB read hits
+system.cpu.dtb.read_hits 13160242 # DTB read hits
system.cpu.dtb.read_misses 7329 # DTB read misses
-system.cpu.dtb.write_hits 11227968 # DTB write hits
+system.cpu.dtb.write_hits 11228050 # DTB write hits
system.cpu.dtb.write_misses 2212 # DTB write misses
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system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch
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system.cpu.dtb.misses 9541 # DTB misses
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system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
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system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024979 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.024979 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.542995 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.542995 # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045251 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045251 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.025268 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.025268 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.029617 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.029617 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13711.884421 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13711.884421 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45175.314481 # average WriteReq miss latency
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-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13846.881413 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13846.881413 # average LoadLockedReq miss latency
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-system.cpu.dcache.demand_avg_miss_latency::total 28317.527202 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 23956.809401 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23956.809401 # average overall miss latency
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+system.cpu.dcache.SoftPFReq_miss_rate::total 0.543003 # miss rate for SoftPFReq accesses
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+system.cpu.dcache.ReadReq_avg_miss_latency::total 13705.573310 # average ReadReq miss latency
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+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13827.913098 # average LoadLockedReq miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 594981 # number of writebacks
-system.cpu.dcache.writebacks::total 594981 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 534 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 534 # number of ReadReq MSHR hits
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-system.cpu.dcache.WriteReq_mshr_misses::total 250461 # number of WriteReq MSHR misses
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-system.cpu.dcache.LoadLockedReq_mshr_misses::total 11207 # number of LoadLockedReq MSHR misses
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-system.cpu.dcache.ReadReq_mshr_miss_latency::total 3445567250 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10763005489 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 10763005489 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1228271500 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1228271500 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 132710000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 132710000 # number of LoadLockedReq MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_latency::total 15436844239 # number of overall MSHR miss cycles
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-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058544250 # number of ReadReq MSHR uncacheable cycles
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-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242551425 # number of WriteReq MSHR uncacheable cycles
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-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045251 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045251 # mshr miss rate for LoadLockedReq accesses
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-system.cpu.dcache.demand_mshr_miss_rate::total 0.025022 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028159 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.028159 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11714.476471 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11714.476471 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42972.780149 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42972.780149 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16715.952857 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16715.952857 # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11841.706077 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11841.706077 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26090.403311 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26090.403311 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24975.923787 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24975.923787 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 595027 # number of writebacks
+system.cpu.dcache.writebacks::total 595027 # number of writebacks
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+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11208 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 11208 # number of LoadLockedReq MSHR misses
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+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1224587250 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 132510750 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 132510750 # number of LoadLockedReq MSHR miss cycles
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+system.cpu.dcache.overall_mshr_miss_latency::total 15453754489 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182056011250 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182056011250 # number of ReadReq MSHR uncacheable cycles
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+system.cpu.dcache.overall_mshr_uncacheable_latency::total 208298450189 # number of overall MSHR uncacheable cycles
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+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025482 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024506 # mshr miss rate for WriteReq accesses
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+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.398573 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045254 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045254 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025024 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025024 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028161 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.028161 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11708.909255 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11708.909255 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43057.923596 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43057.923596 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16665.359072 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16665.359072 # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11822.872056 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11822.872056 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26125.917103 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26125.917103 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25001.261066 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25001.261066 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 52981595 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 2453579 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2453579 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 2453657 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2453657 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 763381 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 763381 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 594981 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2922 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2922 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 247539 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 247539 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1724389 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5748549 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12041 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::Writeback 595027 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2921 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2921 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 247551 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 247551 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1724466 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5748697 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12042 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 26252 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 7511231 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54730908 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83579878 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12460 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 30172 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 138353418 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 138353418 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 171268 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 3007873000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.pkt_count::total 7511457 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54733404 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83586150 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12464 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 30172 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 138362190 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 18590 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 2108398 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 2108398 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 2108398 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 3007986500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1294746250 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1294797750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2533153086 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 2533255572 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1760059764500 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1760059764500 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1760059764500 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1760059764500 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1760318460750 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1760318460750 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1760318460750 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1760318460750 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 2.321351 # Number of seconds simulated
-sim_ticks 2321351025500 # Number of ticks simulated
-final_tick 2321351025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.321335 # Number of seconds simulated
+sim_ticks 2321335404000 # Number of ticks simulated
+final_tick 2321335404000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 709541 # Simulator instruction rate (inst/s)
-host_op_rate 854435 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 27266672116 # Simulator tick rate (ticks/s)
-host_mem_usage 431868 # Number of bytes of host memory used
-host_seconds 85.14 # Real time elapsed on the host
+host_inst_rate 1185543 # Simulator instruction rate (inst/s)
+host_op_rate 1427641 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 45558461303 # Simulator tick rate (ticks/s)
+host_mem_usage 457752 # Number of bytes of host memory used
+host_seconds 50.95 # Real time elapsed on the host
sim_insts 60406834 # Number of instructions simulated
sim_ops 72742429 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bytes_read::realview.clcd 110100480 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 508168 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 5844952 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 197248 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 3227072 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 508104 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 5777624 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 197312 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 3294400 # Number of bytes read from this memory
system.physmem.bytes_read::total 119878240 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 508168 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 197248 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 508104 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 197312 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 705416 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3703808 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1462736 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 1553080 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 1461532 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 1554284 # Number of bytes written to this memory
system.physmem.bytes_written::total 6719624 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 13762560 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 14152 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 91353 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 3082 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 50423 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 14151 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 90301 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 3083 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 51475 # Number of read requests responded to by this memory
system.physmem.num_reads::total 13921575 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57872 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 365684 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 388270 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 365383 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 388571 # Number of write requests responded to by this memory
system.physmem.num_writes::total 811826 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47429483 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.clcd 47429803 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 83 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 218910 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 2517910 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 84971 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1390170 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51641582 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 218910 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 84971 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 303882 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1595540 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 630123 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 669041 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2894704 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1595540 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47429483 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 218884 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 2488923 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 84999 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 1419183 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51641930 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 218884 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 84999 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 303884 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1595551 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 629608 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 669565 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2894723 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1595551 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47429803 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 83 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 218910 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3148032 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 84971 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 2059211 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54536286 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 218884 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 3118531 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 84999 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 2088748 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 54536653 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 55568819 # Throughput (bytes/s)
-system.membus.data_through_bus 128994735 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 14973628 # Transaction distribution
+system.membus.trans_dist::ReadResp 14973628 # Transaction distribution
+system.membus.trans_dist::WriteReq 763122 # Transaction distribution
+system.membus.trans_dist::WriteResp 763122 # Transaction distribution
+system.membus.trans_dist::Writeback 57872 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4519 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4519 # Transaction distribution
+system.membus.trans_dist::ReadExReq 131877 # Transaction distribution
+system.membus.trans_dist::ReadExResp 131877 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382824 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3360 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892848 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 4279044 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 27525120 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 27525120 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 31804164 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2390127 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 6720 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16497384 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 18894255 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 110100480 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 110100480 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 128994735 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 214752 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 214752 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 214752 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.l2c.tags.replacements 62250 # number of replacements
-system.l2c.tags.tagsinuse 50005.872632 # Cycle average of tags in use
-system.l2c.tags.total_refs 1678480 # Total number of references to valid blocks.
+system.l2c.tags.tagsinuse 50005.858036 # Cycle average of tags in use
+system.l2c.tags.total_refs 1678527 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 127635 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 13.150625 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 2306278064000 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 36900.828862 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993863 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993971 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 4874.093087 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 3539.587837 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 2140.383073 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 2548.991939 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.563062 # Average percentage of cache occupancy
+system.l2c.tags.avg_refs 13.150993 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 2306275686000 # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks 36902.743708 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993864 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993972 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 4873.119904 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 3553.057866 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 2141.364810 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 2533.583912 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.563091 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.074373 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.054010 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.032660 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.038895 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst 0.074358 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data 0.054215 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst 0.032675 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data 0.038659 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.763029 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 2 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 65383 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 3672 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 9281 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 52128 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3 9282 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4 52127 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.000031 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.997665 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 17104797 # Number of tag accesses
-system.l2c.tags.data_accesses 17104797 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker 8775 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 3263 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 451755 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 188951 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 5151 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 2105 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 387038 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 177833 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1224871 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 592686 # number of Writeback hits
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system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
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-system.toL2Bus.data_through_bus 137910275 # Total data (bytes)
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-system.iobus.throughput 48459111 # Throughput (bytes/s)
-system.iobus.data_through_bus 112490607 # Total data (bytes)
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+system.toL2Bus.snoops 0 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 2107457 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 2107457 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 2107457 # Request fanout histogram
+system.iobus.trans_dist::ReadReq 14945841 # Transaction distribution
+system.iobus.trans_dist::ReadResp 14945841 # Transaction distribution
+system.iobus.trans_dist::WriteReq 8131 # Transaction distribution
+system.iobus.trans_dist::WriteResp 8131 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29952 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7900 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 476 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 984 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 732 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2382824 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 27525120 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total 27525120 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 29907944 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39247 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15800 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 952 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 1968 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 390 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 2390127 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 110100480 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.clcd.dma::total 110100480 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 112490607 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 6811742 # DTB read hits
-system.cpu0.dtb.read_misses 6183 # DTB read misses
-system.cpu0.dtb.write_hits 6269363 # DTB write hits
-system.cpu0.dtb.write_misses 2047 # DTB write misses
+system.cpu0.dtb.read_hits 6816435 # DTB read hits
+system.cpu0.dtb.read_misses 6211 # DTB read misses
+system.cpu0.dtb.write_hits 6254825 # DTB write hits
+system.cpu0.dtb.write_misses 2049 # DTB write misses
system.cpu0.dtb.flush_tlb 2324 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 763 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_mva_asid 758 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 5527 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 5541 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 117 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 120 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 235 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 6817925 # DTB read accesses
-system.cpu0.dtb.write_accesses 6271410 # DTB write accesses
+system.cpu0.dtb.perms_faults 232 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 6822646 # DTB read accesses
+system.cpu0.dtb.write_accesses 6256874 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 13081105 # DTB hits
-system.cpu0.dtb.misses 8230 # DTB misses
-system.cpu0.dtb.accesses 13089335 # DTB accesses
+system.cpu0.dtb.hits 13071260 # DTB hits
+system.cpu0.dtb.misses 8260 # DTB misses
+system.cpu0.dtb.accesses 13079520 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 32133466 # ITB inst hits
-system.cpu0.itb.inst_misses 3581 # ITB inst misses
+system.cpu0.itb.inst_hits 32152502 # ITB inst hits
+system.cpu0.itb.inst_misses 3598 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 2324 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 763 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_mva_asid 758 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2662 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 2674 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 32137047 # ITB inst accesses
-system.cpu0.itb.hits 32133466 # DTB hits
-system.cpu0.itb.misses 3581 # DTB misses
-system.cpu0.itb.accesses 32137047 # DTB accesses
-system.cpu0.numCycles 4608021079 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 32156100 # ITB inst accesses
+system.cpu0.itb.hits 32152502 # DTB hits
+system.cpu0.itb.misses 3598 # DTB misses
+system.cpu0.itb.accesses 32156100 # DTB accesses
+system.cpu0.numCycles 4610022066 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 31639227 # Number of instructions committed
-system.cpu0.committedOps 38587883 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 34004805 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 5482 # Number of float alu accesses
-system.cpu0.num_func_calls 1192523 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4010781 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 34004805 # number of integer instructions
-system.cpu0.num_fp_insts 5482 # number of float instructions
-system.cpu0.num_int_register_reads 62290177 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 22551825 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 3925 # number of times the floating registers were read
+system.cpu0.committedInsts 31655881 # Number of instructions committed
+system.cpu0.committedOps 38589756 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 34002307 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 5498 # Number of float alu accesses
+system.cpu0.num_func_calls 1192858 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 4013764 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 34002307 # number of integer instructions
+system.cpu0.num_fp_insts 5498 # number of float instructions
+system.cpu0.num_int_register_reads 62271464 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 22558612 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 3941 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1558 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 115496065 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 15262729 # number of times the CC registers were written
-system.cpu0.num_mem_refs 13528824 # number of memory refs
-system.cpu0.num_load_insts 6988108 # Number of load instructions
-system.cpu0.num_store_insts 6540716 # Number of store instructions
-system.cpu0.num_idle_cycles 4534732444.570566 # Number of idle cycles
-system.cpu0.num_busy_cycles 73288634.429434 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.015905 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.984095 # Percentage of idle cycles
-system.cpu0.Branches 5541899 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 16090 0.04% 0.04% # Class of executed instruction
-system.cpu0.op_class::IntAlu 25070156 64.84% 64.89% # Class of executed instruction
-system.cpu0.op_class::IntMult 45827 0.12% 65.00% # Class of executed instruction
-system.cpu0.op_class::IntDiv 0 0.00% 65.00% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 65.00% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 65.00% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 65.00% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 65.00% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 65.00% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 65.00% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 65.00% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 65.00% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 65.00% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 65.00% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 65.00% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 65.00% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 65.00% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 65.00% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 65.00% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.00% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 65.00% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.00% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.00% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.00% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.00% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.00% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 1368 0.00% 65.01% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 65.01% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.01% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.01% # Class of executed instruction
-system.cpu0.op_class::MemRead 6988108 18.07% 83.08% # Class of executed instruction
-system.cpu0.op_class::MemWrite 6540716 16.92% 100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads 115497170 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 15275707 # number of times the CC registers were written
+system.cpu0.num_mem_refs 13519126 # number of memory refs
+system.cpu0.num_load_insts 6992673 # Number of load instructions
+system.cpu0.num_store_insts 6526453 # Number of store instructions
+system.cpu0.num_idle_cycles 4538759726.926458 # Number of idle cycles
+system.cpu0.num_busy_cycles 71262339.073542 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.015458 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.984542 # Percentage of idle cycles
+system.cpu0.Branches 5545179 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 16079 0.04% 0.04% # Class of executed instruction
+system.cpu0.op_class::IntAlu 25081623 64.87% 64.91% # Class of executed instruction
+system.cpu0.op_class::IntMult 45922 0.12% 65.03% # Class of executed instruction
+system.cpu0.op_class::IntDiv 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 1365 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.03% # Class of executed instruction
+system.cpu0.op_class::MemRead 6992673 18.09% 83.12% # Class of executed instruction
+system.cpu0.op_class::MemWrite 6526453 16.88% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 38662265 # Class of executed instruction
+system.cpu0.op_class::total 38664115 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 82781 # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements 850515 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.689593 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 60581740 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 851027 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 71.186625 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 5455017500 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 446.344221 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 65.345372 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.871766 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.127628 # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements 850504 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.689630 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 60581751 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 851016 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 71.187558 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 5451547500 # Cycle when the warmup percentage was hit.
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+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045534 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044874 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.045255 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025926 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023771 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.024934 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028526 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data 0.027542 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.028073 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 592686 # number of writebacks
-system.cpu0.dcache.writebacks::total 592686 # number of writebacks
+system.cpu0.dcache.writebacks::writebacks 592674 # number of writebacks
+system.cpu0.dcache.writebacks::total 592674 # number of writebacks
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 6327054 # DTB read hits
-system.cpu1.dtb.read_misses 4532 # DTB read misses
-system.cpu1.dtb.write_hits 4945852 # DTB write hits
-system.cpu1.dtb.write_misses 1126 # DTB write misses
+system.cpu1.dtb.read_hits 6322311 # DTB read hits
+system.cpu1.dtb.read_misses 4545 # DTB read misses
+system.cpu1.dtb.write_hits 4960387 # DTB write hits
+system.cpu1.dtb.write_misses 1127 # DTB write misses
system.cpu1.dtb.flush_tlb 2320 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_mva_asid 681 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 3028 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 3056 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 87 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 92 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 6331586 # DTB read accesses
-system.cpu1.dtb.write_accesses 4946978 # DTB write accesses
+system.cpu1.dtb.perms_faults 220 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 6326856 # DTB read accesses
+system.cpu1.dtb.write_accesses 4961514 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 11272906 # DTB hits
-system.cpu1.dtb.misses 5658 # DTB misses
-system.cpu1.dtb.accesses 11278564 # DTB accesses
+system.cpu1.dtb.hits 11282698 # DTB hits
+system.cpu1.dtb.misses 5672 # DTB misses
+system.cpu1.dtb.accesses 11288370 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 29294834 # ITB inst hits
-system.cpu1.itb.inst_misses 2597 # ITB inst misses
+system.cpu1.itb.inst_hits 29275767 # ITB inst hits
+system.cpu1.itb.inst_misses 2611 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 2320 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_mva_asid 681 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1660 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1680 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 29297431 # ITB inst accesses
-system.cpu1.itb.hits 29294834 # DTB hits
-system.cpu1.itb.misses 2597 # DTB misses
-system.cpu1.itb.accesses 29297431 # DTB accesses
-system.cpu1.numCycles 141054432 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 29278378 # ITB inst accesses
+system.cpu1.itb.hits 29275767 # DTB hits
+system.cpu1.itb.misses 2611 # DTB misses
+system.cpu1.itb.accesses 29278378 # DTB accesses
+system.cpu1.numCycles 143033518 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 28767607 # Number of instructions committed
-system.cpu1.committedOps 34154546 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 30186625 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 4787 # Number of float alu accesses
-system.cpu1.num_func_calls 943239 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 3534203 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 30186625 # number of integer instructions
-system.cpu1.num_fp_insts 4787 # number of float instructions
-system.cpu1.num_int_register_reads 54137170 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 20266282 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 3568 # number of times the floating registers were read
+system.cpu1.committedInsts 28750953 # Number of instructions committed
+system.cpu1.committedOps 34152673 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 30189123 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 4771 # Number of float alu accesses
+system.cpu1.num_func_calls 942904 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 3531220 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 30189123 # number of integer instructions
+system.cpu1.num_fp_insts 4771 # number of float instructions
+system.cpu1.num_int_register_reads 54155883 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 20259495 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 3552 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 1222 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 102073939 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 13715012 # number of times the CC registers were written
-system.cpu1.num_mem_refs 11692450 # number of memory refs
-system.cpu1.num_load_insts 6511829 # Number of load instructions
-system.cpu1.num_store_insts 5180621 # Number of store instructions
-system.cpu1.num_idle_cycles 138966556.858503 # Number of idle cycles
-system.cpu1.num_busy_cycles 2087875.141497 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.014802 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.985198 # Percentage of idle cycles
-system.cpu1.Branches 4756618 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 12428 0.04% 0.04% # Class of executed instruction
-system.cpu1.op_class::IntAlu 22465876 65.66% 65.70% # Class of executed instruction
-system.cpu1.op_class::IntMult 41944 0.12% 65.82% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 745 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.82% # Class of executed instruction
-system.cpu1.op_class::MemRead 6511829 19.03% 84.86% # Class of executed instruction
-system.cpu1.op_class::MemWrite 5180621 15.14% 100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads 102072834 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 13702034 # number of times the CC registers were written
+system.cpu1.num_mem_refs 11702148 # number of memory refs
+system.cpu1.num_load_insts 6507264 # Number of load instructions
+system.cpu1.num_store_insts 5194884 # Number of store instructions
+system.cpu1.num_idle_cycles 140979209.208319 # Number of idle cycles
+system.cpu1.num_busy_cycles 2054308.791681 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.014362 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.985638 # Percentage of idle cycles
+system.cpu1.Branches 4753338 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 12439 0.04% 0.04% # Class of executed instruction
+system.cpu1.op_class::IntAlu 22454409 65.63% 65.67% # Class of executed instruction
+system.cpu1.op_class::IntMult 41849 0.12% 65.79% # Class of executed instruction
+system.cpu1.op_class::IntDiv 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 748 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.79% # Class of executed instruction
+system.cpu1.op_class::MemRead 6507264 19.02% 84.82% # Class of executed instruction
+system.cpu1.op_class::MemWrite 5194884 15.18% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 34213443 # Class of executed instruction
+system.cpu1.op_class::total 34211593 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.iocache.tags.replacements 0 # number of replacements
---------- Begin Simulation Statistics ----------
-sim_seconds 5.112126 # Number of seconds simulated
-sim_ticks 5112125984500 # Number of ticks simulated
-final_tick 5112125984500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.112127 # Number of seconds simulated
+sim_ticks 5112126720000 # Number of ticks simulated
+final_tick 5112126720000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1274105 # Simulator instruction rate (inst/s)
-host_op_rate 2608650 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 32578287771 # Simulator tick rate (ticks/s)
-host_mem_usage 593532 # Number of bytes of host memory used
-host_seconds 156.92 # Real time elapsed on the host
-sim_insts 199930130 # Number of instructions simulated
-sim_ops 409344539 # Number of ops (including micro ops) simulated
+host_inst_rate 1627732 # Simulator instruction rate (inst/s)
+host_op_rate 3332615 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 41616843658 # Simulator tick rate (ticks/s)
+host_mem_usage 647148 # Number of bytes of host memory used
+host_seconds 122.84 # Real time elapsed on the host
+sim_insts 199947158 # Number of instructions simulated
+sim_ops 409371517 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 852800 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10650880 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11532416 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 852800 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 852800 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6281856 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 852352 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10669504 # Number of bytes read from this memory
+system.physmem.bytes_read::total 11550592 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 852352 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 852352 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6285632 # Number of bytes written to this memory
system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9271936 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9275712 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 13325 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 166420 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 180194 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 98154 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 13318 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 166711 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 180478 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 98213 # Number of write requests responded to by this memory
system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 144874 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 144933 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 166819 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2083454 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2255894 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 166819 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 166819 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1228815 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide 584900 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1813714 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1228815 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 590446 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 166731 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2087097 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2259449 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 166731 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 166731 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1229553 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide 584899 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1814453 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1229553 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 590445 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 166819 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2083454 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4069609 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 9050072 # Throughput (bytes/s)
-system.membus.data_through_bus 46265107 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.iocache.tags.replacements 47569 # number of replacements
-system.iocache.tags.tagsinuse 0.042447 # Cycle average of tags in use
+system.physmem.bw_total::cpu.inst 166731 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2087097 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4073902 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 13903648 # Transaction distribution
+system.membus.trans_dist::ReadResp 13903648 # Transaction distribution
+system.membus.trans_dist::WriteReq 13796 # Transaction distribution
+system.membus.trans_dist::WriteResp 13796 # Transaction distribution
+system.membus.trans_dist::Writeback 98213 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 2521 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 2092 # Transaction distribution
+system.membus.trans_dist::ReadExReq 134490 # Transaction distribution
+system.membus.trans_dist::ReadExResp 134485 # Transaction distribution
+system.membus.trans_dist::MessageReq 1696 # Transaction distribution
+system.membus.trans_dist::MessageResp 1696 # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20043728 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462901 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28204873 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95256 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 95256 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 28303521 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10027982 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17807872 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43232339 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3048192 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 3048192 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 46287315 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 328402 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 328402 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 328402 # Request fanout histogram
+system.iocache.tags.replacements 47573 # number of replacements
+system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 4994846763009 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042447 # Average occupied blocks per requestor
+system.iocache.tags.warmup_cycle 4994846765009 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 428616 # Number of tag accesses
-system.iocache.tags.data_accesses 428616 # Number of data accesses
+system.iocache.tags.tag_accesses 428652 # Number of tag accesses
+system.iocache.tags.data_accesses 428652 # Number of data accesses
system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
-system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 904 # number of ReadReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses
-system.iocache.demand_misses::total 904 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses
-system.iocache.overall_misses::total 904 # number of overall misses
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 908 # number of ReadReq misses
+system.iocache.demand_misses::pc.south_bridge.ide 908 # number of demand (read+write) misses
+system.iocache.demand_misses::total 908 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 908 # number of overall misses
+system.iocache.overall_misses::total 908 # number of overall misses
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 908 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 908 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 908 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 908 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.iobus.throughput 2555207 # Throughput (bytes/s)
-system.iobus.data_through_bus 13062542 # Total data (bytes)
+system.iobus.trans_dist::ReadReq 10011915 # Transaction distribution
+system.iobus.trans_dist::ReadResp 10011915 # Transaction distribution
+system.iobus.trans_dist::WriteReq 57577 # Transaction distribution
+system.iobus.trans_dist::WriteResp 10857 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1696 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1696 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 19999988 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1098 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27352 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 20043728 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95256 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95256 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3392 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3392 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 20142376 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 9999994 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2196 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13676 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 10027982 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027808 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027808 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6784 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 13062574 # Cumulative packet size per connected master and slave (bytes)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.numCycles 10224253344 # number of cpu cycles simulated
+system.cpu.numCycles 10224257410 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 199930130 # Number of instructions committed
-system.cpu.committedOps 409344539 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 374365317 # Number of integer alu accesses
+system.cpu.committedInsts 199947158 # Number of instructions committed
+system.cpu.committedOps 409371517 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 374392167 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_func_calls 2307745 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 39976374 # number of instructions that are conditional controls
-system.cpu.num_int_insts 374365317 # number of integer instructions
+system.cpu.num_func_calls 2307997 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 39978602 # number of instructions that are conditional controls
+system.cpu.num_int_insts 374392167 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 682286798 # number of times the integer registers were read
-system.cpu.num_int_register_writes 323369753 # number of times the integer registers were written
+system.cpu.num_int_register_reads 682348609 # number of times the integer registers were read
+system.cpu.num_int_register_writes 323388730 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 233715334 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 157233726 # number of times the CC registers were written
-system.cpu.num_mem_refs 35661072 # number of memory refs
-system.cpu.num_load_insts 27238907 # Number of load instructions
-system.cpu.num_store_insts 8422165 # Number of store instructions
-system.cpu.num_idle_cycles 9770516870.697727 # Number of idle cycles
-system.cpu.num_busy_cycles 453736473.302274 # Number of busy cycles
-system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.955622 # Percentage of idle cycles
-system.cpu.Branches 43125613 # Number of branches fetched
-system.cpu.op_class::No_OpClass 175318 0.04% 0.04% # Class of executed instruction
-system.cpu.op_class::IntAlu 373241846 91.18% 91.22% # Class of executed instruction
-system.cpu.op_class::IntMult 144365 0.04% 91.26% # Class of executed instruction
-system.cpu.op_class::IntDiv 122968 0.03% 91.29% # Class of executed instruction
+system.cpu.num_cc_register_reads 233729759 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 157242019 # number of times the CC registers were written
+system.cpu.num_mem_refs 35671209 # number of memory refs
+system.cpu.num_load_insts 27243676 # Number of load instructions
+system.cpu.num_store_insts 8427533 # Number of store instructions
+system.cpu.num_idle_cycles 9770491320.524229 # Number of idle cycles
+system.cpu.num_busy_cycles 453766089.475771 # Number of busy cycles
+system.cpu.not_idle_fraction 0.044381 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.955619 # Percentage of idle cycles
+system.cpu.Branches 43128209 # Number of branches fetched
+system.cpu.op_class::No_OpClass 175380 0.04% 0.04% # Class of executed instruction
+system.cpu.op_class::IntAlu 373258577 91.18% 91.22% # Class of executed instruction
+system.cpu.op_class::IntMult 144442 0.04% 91.26% # Class of executed instruction
+system.cpu.op_class::IntDiv 122944 0.03% 91.29% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::MemRead 27238907 6.65% 97.94% # Class of executed instruction
-system.cpu.op_class::MemWrite 8422165 2.06% 100.00% # Class of executed instruction
+system.cpu.op_class::MemRead 27243676 6.65% 97.94% # Class of executed instruction
+system.cpu.op_class::MemWrite 8427533 2.06% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 409345569 # Class of executed instruction
+system.cpu.op_class::total 409372552 # Class of executed instruction
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu.icache.tags.replacements 790679 # number of replacements
+system.cpu.icache.tags.replacements 791918 # number of replacements
system.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 243526070 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 791191 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 307.796815 # Average number of references to valid blocks.
+system.cpu.icache.tags.total_refs 243546972 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 792430 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 307.341938 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 245108466 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 245108466 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 243526070 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 243526070 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 243526070 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 243526070 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 243526070 # number of overall hits
-system.cpu.icache.overall_hits::total 243526070 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 791198 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 791198 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 791198 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 791198 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 791198 # number of overall misses
-system.cpu.icache.overall_misses::total 791198 # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst 244317268 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 244317268 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 244317268 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 244317268 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 244317268 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 244317268 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses
+system.cpu.icache.tags.tag_accesses 245131846 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 245131846 # Number of data accesses
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-system.cpu.dcache.WriteReq_accesses::total 8411913 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.toL2Bus.data_through_bus 279231827 # Total data (bytes)
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system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016842 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.102778 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.074319 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016842 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.102778 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.074319 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses::cpu.inst 13318 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 166994 # number of overall misses
+system.cpu.l2cache.overall_misses::total 180318 # number of overall misses
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7335 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3342 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 792424 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1308415 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 2111516 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 1540333 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 1540333 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1831 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 1831 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 314780 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 314780 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7335 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker 3342 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 792424 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1623195 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 2426296 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7335 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker 3342 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 792424 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1623195 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 2426296 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000136 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001496 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016807 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024630 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.021572 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987985 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987985 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428134 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.428134 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000136 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001496 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016807 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.102880 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.074318 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000136 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001496 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016807 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.102880 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.074318 # miss rate for overall accesses
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 98154 # number of writebacks
-system.cpu.l2cache.writebacks::total 98154 # number of writebacks
+system.cpu.l2cache.writebacks::writebacks 98213 # number of writebacks
+system.cpu.l2cache.writebacks::total 98213 # number of writebacks
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 5.192526 # Number of seconds simulated
-sim_ticks 5192526233000 # Number of ticks simulated
-final_tick 5192526233000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.192511 # Number of seconds simulated
+sim_ticks 5192511044000 # Number of ticks simulated
+final_tick 5192511044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1492668 # Simulator instruction rate (inst/s)
-host_op_rate 2877328 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 60393582039 # Simulator tick rate (ticks/s)
-host_mem_usage 592376 # Number of bytes of host memory used
-host_seconds 85.98 # Real time elapsed on the host
-sim_insts 128336778 # Number of instructions simulated
-sim_ops 247387190 # Number of ops (including micro ops) simulated
+host_inst_rate 1018343 # Simulator instruction rate (inst/s)
+host_op_rate 1963050 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 41210458750 # Simulator tick rate (ticks/s)
+host_mem_usage 646888 # Number of bytes of host memory used
+host_seconds 126.00 # Real time elapsed on the host
+sim_insts 128310974 # Number of instructions simulated
+sim_ops 247343919 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 829632 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9090688 # Number of bytes read from this memory
-system.physmem.bytes_read::total 9949056 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 829632 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 829632 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 5138240 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 827456 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9076288 # Number of bytes read from this memory
+system.physmem.bytes_read::total 9932544 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 827456 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 827456 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 5141952 # Number of bytes written to this memory
system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8128320 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8132032 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12963 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142042 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 155454 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 80285 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12929 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 141817 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 155196 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 80343 # Number of write requests responded to by this memory
system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 127005 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 127063 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 5460 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 159774 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1750725 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1916034 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 159774 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 159774 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 989545 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide 575843 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1565388 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 989545 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 581303 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 159356 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1747957 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1912859 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 159356 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 159356 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 990263 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide 575845 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1566108 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 990263 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 581305 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 159774 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1750725 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3481422 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 155454 # Number of read requests accepted
-system.physmem.writeReqs 127005 # Number of write requests accepted
-system.physmem.readBursts 155454 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 127005 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 9932928 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 16128 # Total number of bytes read from write queue
-system.physmem.bytesWritten 8126720 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 9949056 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 8128320 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 252 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu.inst 159356 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1747957 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3478967 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 155196 # Number of read requests accepted
+system.physmem.writeReqs 127063 # Number of write requests accepted
+system.physmem.readBursts 155196 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 127063 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 9914944 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 17600 # Total number of bytes read from write queue
+system.physmem.bytesWritten 8130496 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 9932544 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 8132032 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 275 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 1602 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 10234 # Per bank write bursts
-system.physmem.perBankRdBursts::1 9830 # Per bank write bursts
-system.physmem.perBankRdBursts::2 10412 # Per bank write bursts
-system.physmem.perBankRdBursts::3 9937 # Per bank write bursts
-system.physmem.perBankRdBursts::4 9788 # Per bank write bursts
-system.physmem.perBankRdBursts::5 9348 # Per bank write bursts
-system.physmem.perBankRdBursts::6 9238 # Per bank write bursts
-system.physmem.perBankRdBursts::7 9473 # Per bank write bursts
-system.physmem.perBankRdBursts::8 9270 # Per bank write bursts
-system.physmem.perBankRdBursts::9 9085 # Per bank write bursts
-system.physmem.perBankRdBursts::10 9528 # Per bank write bursts
-system.physmem.perBankRdBursts::11 9619 # Per bank write bursts
-system.physmem.perBankRdBursts::12 9707 # Per bank write bursts
-system.physmem.perBankRdBursts::13 10058 # Per bank write bursts
-system.physmem.perBankRdBursts::14 9877 # Per bank write bursts
-system.physmem.perBankRdBursts::15 9798 # Per bank write bursts
-system.physmem.perBankWrBursts::0 8316 # Per bank write bursts
-system.physmem.perBankWrBursts::1 7729 # Per bank write bursts
-system.physmem.perBankWrBursts::2 8212 # Per bank write bursts
-system.physmem.perBankWrBursts::3 7860 # Per bank write bursts
-system.physmem.perBankWrBursts::4 8063 # Per bank write bursts
-system.physmem.perBankWrBursts::5 7657 # Per bank write bursts
-system.physmem.perBankWrBursts::6 7184 # Per bank write bursts
-system.physmem.perBankWrBursts::7 7824 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7616 # Per bank write bursts
-system.physmem.perBankWrBursts::9 7570 # Per bank write bursts
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-system.physmem.perBankWrBursts::12 8040 # Per bank write bursts
-system.physmem.perBankWrBursts::13 8642 # Per bank write bursts
-system.physmem.perBankWrBursts::14 8420 # Per bank write bursts
-system.physmem.perBankWrBursts::15 8095 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 1594 # Number of requests that are neither read nor write
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+system.physmem.perBankRdBursts::4 9555 # Per bank write bursts
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+system.physmem.perBankRdBursts::6 9351 # Per bank write bursts
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+system.physmem.perBankRdBursts::8 9073 # Per bank write bursts
+system.physmem.perBankRdBursts::9 8991 # Per bank write bursts
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+system.physmem.perBankRdBursts::12 9550 # Per bank write bursts
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+system.physmem.perBankWrBursts::4 7990 # Per bank write bursts
+system.physmem.perBankWrBursts::5 7535 # Per bank write bursts
+system.physmem.perBankWrBursts::6 7392 # Per bank write bursts
+system.physmem.perBankWrBursts::7 7734 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7444 # Per bank write bursts
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+system.physmem.perBankWrBursts::10 7970 # Per bank write bursts
+system.physmem.perBankWrBursts::11 7896 # Per bank write bursts
+system.physmem.perBankWrBursts::12 8102 # Per bank write bursts
+system.physmem.perBankWrBursts::13 8416 # Per bank write bursts
+system.physmem.perBankWrBursts::14 8297 # Per bank write bursts
+system.physmem.perBankWrBursts::15 7835 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 5192526169500 # Total gap between requests
+system.physmem.numWrRetry 1 # Number of times write queue was full causing retry
+system.physmem.totGap 5192510980500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 155454 # Read request sizes (log2)
+system.physmem.readPktSize::6 155196 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 127005 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 151750 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 3023 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 127063 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 151525 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::16 3242 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::22 8169 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 8822 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 9909 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::26 8509 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 7675 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 7337 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 6397 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 6159 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 6188 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 6092 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 206 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 180 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 188 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 164 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 176 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 203 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 191 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 183 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 179 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 171 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 181 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 170 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 148 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 146 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 140 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 88 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 55 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 43 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 30 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 28 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 21 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 56259 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 321.007910 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 189.347718 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 335.337897 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 20082 35.70% 35.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 13652 24.27% 59.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 5681 10.10% 70.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3443 6.12% 76.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2317 4.12% 80.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1632 2.90% 83.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1101 1.96% 85.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1008 1.79% 86.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 7343 13.05% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 56259 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5896 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 26.315638 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 622.349689 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 5895 99.98% 99.98% # Reads before turning the bus around for writes
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+system.physmem.wrQLenPdf::52 64 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 57292 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 314.972003 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 184.928814 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 333.427002 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 21127 36.88% 36.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 13732 23.97% 60.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 5729 10.00% 70.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3461 6.04% 76.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2250 3.93% 80.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1575 2.75% 83.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1105 1.93% 85.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1008 1.76% 87.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 7305 12.75% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 57292 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 5905 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 26.232854 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 621.882480 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 5904 99.98% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5896 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5896 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 21.536635 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 19.431893 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 14.049302 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 4860 82.43% 82.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 44 0.75% 83.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 38 0.64% 83.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 287 4.87% 88.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 272 4.61% 93.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 20 0.34% 93.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 25 0.42% 94.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 11 0.19% 94.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 27 0.46% 94.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 4 0.07% 94.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 3 0.05% 94.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 1 0.02% 94.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 223 3.78% 98.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 4 0.07% 98.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 6 0.10% 98.80% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 5905 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 5905 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 21.513802 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 19.393687 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 14.130484 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 4886 82.74% 82.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 42 0.71% 83.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 41 0.69% 84.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 275 4.66% 88.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 267 4.52% 93.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 20 0.34% 93.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 10 0.17% 93.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 19 0.32% 94.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 22 0.37% 94.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 8 0.14% 94.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 6 0.10% 94.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 2 0.03% 94.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 226 3.83% 98.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 6 0.10% 98.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 4 0.07% 98.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 3 0.05% 98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 20 0.34% 99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 1 0.02% 99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 1 0.02% 99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 10 0.17% 99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 2 0.03% 99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 2 0.03% 99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 2 0.03% 99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 8 0.14% 99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 2 0.03% 99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 4 0.07% 99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 13 0.22% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 15 0.25% 99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 1 0.02% 99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 1 0.02% 99.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 13 0.22% 99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 1 0.02% 99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 6 0.10% 99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 3 0.05% 99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 8 0.14% 99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 2 0.03% 99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 3 0.05% 99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 12 0.20% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.02% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5896 # Writes before turning the bus around for reads
-system.physmem.totQLat 1473683250 # Total ticks spent queuing
-system.physmem.totMemAccLat 4383720750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 776010000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 9495.26 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total 5905 # Writes before turning the bus around for reads
+system.physmem.totQLat 1558594500 # Total ticks spent queuing
+system.physmem.totMemAccLat 4463363250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 774605000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 10060.58 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 28245.26 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 28810.58 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.92 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 22.52 # Average write queue length when enqueuing
-system.physmem.readRowHits 127189 # Number of row buffer hits during reads
-system.physmem.writeRowHits 98733 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.95 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 77.74 # Row buffer hit rate for writes
-system.physmem.avgGap 18383291.63 # Average gap between requests
-system.physmem.pageHitRate 80.06 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 4971157882750 # Time in different power states
-system.physmem.memoryStateTime::REF 173389840000 # Time in different power states
+system.physmem.avgWrQLen 22.05 # Average write queue length when enqueuing
+system.physmem.readRowHits 125976 # Number of row buffer hits during reads
+system.physmem.writeRowHits 98691 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 81.32 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 77.67 # Row buffer hit rate for writes
+system.physmem.avgGap 18396263.65 # Average gap between requests
+system.physmem.pageHitRate 79.67 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 4970934831000 # Time in different power states
+system.physmem.memoryStateTime::REF 173389320000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 47978395250 # Time in different power states
+system.physmem.memoryStateTime::ACT 48186778000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 3808612 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 623901 # Transaction distribution
-system.membus.trans_dist::ReadResp 623901 # Transaction distribution
+system.membus.trans_dist::ReadReq 623858 # Transaction distribution
+system.membus.trans_dist::ReadResp 623858 # Transaction distribution
system.membus.trans_dist::WriteReq 13773 # Transaction distribution
system.membus.trans_dist::WriteResp 13773 # Transaction distribution
-system.membus.trans_dist::Writeback 80285 # Transaction distribution
+system.membus.trans_dist::Writeback 80343 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
system.membus.trans_dist::UpgradeReq 2146 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 1602 # Transaction distribution
-system.membus.trans_dist::ReadExReq 113400 # Transaction distribution
-system.membus.trans_dist::ReadExResp 113400 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 1594 # Transaction distribution
+system.membus.trans_dist::ReadExReq 113180 # Transaction distribution
+system.membus.trans_dist::ReadExResp 113180 # Transaction distribution
system.membus.trans_dist::MessageReq 1654 # Transaction distribution
system.membus.trans_dist::MessageResp 1654 # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480328 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710110 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394055 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584493 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94727 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 94727 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1682528 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246444 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420217 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15058944 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16725605 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 19750653 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 19750653 # Total data (bytes)
-system.membus.snoop_data_through_bus 25664 # Total snoop data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393589 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584027 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94722 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 94722 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1682057 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246444 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420217 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15046144 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16712805 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 19737853 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 948 # Total snoops (count)
+system.membus.snoop_fanout::samples 284802 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 284802 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 284802 # Request fanout histogram
system.membus.reqLayer0.occupancy 256795500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 359321500 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 358101500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 1309717000 # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy 1310597750 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 2621518398 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 2618526656 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer4.occupancy 54330498 # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy 54286498 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 47509 # number of replacements
-system.iocache.tags.tagsinuse 0.112613 # Cycle average of tags in use
+system.iocache.tags.replacements 47504 # number of replacements
+system.iocache.tags.tagsinuse 0.112573 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 47525 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 47520 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 5045777659000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.112613 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007038 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.007038 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 5045778761000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.112573 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007036 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.007036 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 428076 # Number of tag accesses
-system.iocache.tags.data_accesses 428076 # Number of data accesses
+system.iocache.tags.tag_accesses 428031 # Number of tag accesses
+system.iocache.tags.data_accesses 428031 # Number of data accesses
system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
-system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 844 # number of ReadReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 844 # number of demand (read+write) misses
-system.iocache.demand_misses::total 844 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 844 # number of overall misses
-system.iocache.overall_misses::total 844 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141199186 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 141199186 # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 141199186 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 141199186 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 141199186 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 141199186 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_misses::pc.south_bridge.ide 839 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 839 # number of ReadReq misses
+system.iocache.demand_misses::pc.south_bridge.ide 839 # number of demand (read+write) misses
+system.iocache.demand_misses::total 839 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 839 # number of overall misses
+system.iocache.overall_misses::total 839 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 140842436 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 140842436 # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 140842436 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 140842436 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 140842436 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 140842436 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 839 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 839 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 844 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 844 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 844 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 844 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 839 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 839 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 839 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 839 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167297.613744 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 167297.613744 # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167297.613744 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 167297.613744 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167297.613744 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 167297.613744 # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 167869.411204 # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 167869.411204 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 167869.411204 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 46720 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 839 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 839 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 844 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 844 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 844 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 844 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97286186 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 97286186 # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2834928162 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2834928162 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97286186 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 97286186 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97286186 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 97286186 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 839 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 839 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 839 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 839 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97188936 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 97188936 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2836981412 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2836981412 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97188936 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 97188936 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97188936 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 97188936 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115267.992891 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 115267.992891 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60679.113057 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60679.113057 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115267.992891 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 115267.992891 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115267.992891 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 115267.992891 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 115839.017878 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60723.061045 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60723.061045 # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 115839.017878 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 115839.017878 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.iobus.throughput 631746 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 230149 # Transaction distribution
-system.iobus.trans_dist::ReadResp 230149 # Transaction distribution
+system.iobus.trans_dist::ReadReq 230144 # Transaction distribution
+system.iobus.trans_dist::ReadResp 230144 # Transaction distribution
system.iobus.trans_dist::WriteReq 57579 # Transaction distribution
system.iobus.trans_dist::WriteResp 57579 # Transaction distribution
system.iobus.trans_dist::MessageReq 1654 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 480328 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95128 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95128 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95118 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95118 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 578764 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 246444 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027296 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027296 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 3280356 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 3280356 # Total data (bytes)
+system.iobus.pkt_count::total 578754 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 246444 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 3280316 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 3944816 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
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system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
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system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks)
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+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7868 # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total 7868 # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7847 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total 7847 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7847 # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total 7847 # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4381 # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total 4381 # number of ReadReq misses
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-system.cpu.itb_walker_cache.demand_misses::total 4381 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4381 # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total 4381 # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43773750 # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43773750 # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43773750 # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total 43773750 # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43773750 # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total 43773750 # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12226 # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total 12226 # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7870 # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total 7870 # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7870 # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total 7870 # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4357 # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total 4357 # number of ReadReq misses
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+system.cpu.itb_walker_cache.demand_misses::total 4357 # number of demand (read+write) misses
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+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43584500 # number of demand (read+write) miss cycles
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+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43584500 # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total 43584500 # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12228 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total 12228 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12228 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total 12228 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.358335 # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.358335 # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.358276 # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total 0.358276 # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.358276 # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total 0.358276 # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9991.725633 # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9991.725633 # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9991.725633 # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9991.725633 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9991.725633 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9991.725633 # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses
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+system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses
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+system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.356401 # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.356343 # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total 0.356343 # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.356343 # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total 0.356343 # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10003.327978 # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10003.327978 # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10003.327978 # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10003.327978 # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10003.327978 # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10003.327978 # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks 771 # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total 771 # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4381 # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4381 # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4381 # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total 4381 # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4381 # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total 4381 # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 35010250 # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 35010250 # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 35010250 # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 35010250 # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 35010250 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 35010250 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.358335 # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.358335 # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.358276 # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.358276 # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.358276 # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.358276 # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7991.383246 # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7991.383246 # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7991.383246 # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7991.383246 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7991.383246 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7991.383246 # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks 747 # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total 747 # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4357 # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4357 # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4357 # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total 4357 # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4357 # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total 4357 # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34868500 # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34868500 # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34868500 # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34868500 # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34868500 # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34868500 # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.356401 # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.356401 # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.356343 # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.356343 # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.356343 # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.356343 # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8002.868947 # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8002.868947 # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8002.868947 # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8002.868947 # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8002.868947 # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8002.868947 # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements 7447 # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse 5.051866 # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs 13273 # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs 7461 # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs 1.778984 # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 5163481853000 # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.051866 # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.replacements 7826 # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse 5.051872 # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs 12792 # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs 7842 # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs 1.631217 # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 5165211267000 # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.051872 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315742 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315742 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses 52546 # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses 52546 # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13289 # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total 13289 # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13289 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total 13289 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13289 # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total 13289 # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8656 # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total 8656 # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8656 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total 8656 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8656 # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total 8656 # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 91979000 # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 91979000 # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 91979000 # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total 91979000 # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 91979000 # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total 91979000 # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21945 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total 21945 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21945 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total 21945 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21945 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total 21945 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.394441 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.394441 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.394441 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total 0.394441 # miss rate for demand accesses
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-system.cpu.dtb_walker_cache.overall_miss_rate::total 0.394441 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10626.039741 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10626.039741 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10626.039741 # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10626.039741 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10626.039741 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10626.039741 # average overall miss latency
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.dtb_walker_cache.tags.tag_accesses 52641 # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses 52641 # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12792 # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total 12792 # number of ReadReq hits
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+system.cpu.dtb_walker_cache.demand_hits::total 12792 # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12792 # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total 12792 # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9019 # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total 9019 # number of ReadReq misses
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+system.cpu.dtb_walker_cache.demand_misses::total 9019 # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9019 # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total 9019 # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 95783000 # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 95783000 # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 95783000 # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total 95783000 # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 95783000 # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total 95783000 # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21811 # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total 21811 # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21811 # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total 21811 # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21811 # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total 21811 # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.413507 # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.413507 # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.413507 # miss rate for demand accesses
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+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10620.135270 # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10620.135270 # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10620.135270 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10620.135270 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10620.135270 # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
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-system.cpu.dtb_walker_cache.writebacks::total 2980 # number of writebacks
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-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8656 # number of ReadReq MSHR misses
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-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74666500 # number of demand (read+write) MSHR miss cycles
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-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74666500 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74666500 # number of overall MSHR miss cycles
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-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.394441 # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.394441 # mshr miss rate for overall accesses
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-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8625.981978 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8625.981978 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8625.981978 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8625.981978 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8625.981978 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8625.981978 # average overall mshr miss latency
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+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8620.079831 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8620.079831 # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 1620883 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.997130 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 20027756 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1621395 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 12.352176 # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements 1621218 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.996934 # Cycle average of tags in use
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system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 102 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id
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system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu.dcache.SoftPFReq_hits::total 59261 # number of SoftPFReq hits
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-system.cpu.dcache.SoftPFReq_misses::total 402313 # number of SoftPFReq misses
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 14027.410255 # average ReadReq miss latency
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-system.cpu.dcache.blocked_cycles::no_mshrs 7655 # number of cycles access was blocked
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+system.cpu.dcache.ReadReq_hits::total 11933720 # number of ReadReq hits
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.dcache.writebacks::total 1537682 # number of writebacks
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-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5351981750 # number of SoftPFReq MSHR miss cycles
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-system.cpu.dcache.demand_mshr_miss_latency::total 21103367124 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26455348874 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 26455348874 # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9293 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 9293 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 9580 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 9580 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 9580 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 9580 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906280 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 906280 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315243 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 315243 # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402425 # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total 402425 # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1221523 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1221523 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1623948 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1623948 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10906302000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 10906302000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10245705379 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245705379 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5368514000 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5368514000 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21152007379 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 21152007379 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26520521379 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 26520521379 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214672000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214672000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537257000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537257000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96751929000 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 96751929000 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070552 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070552 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037738 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037738 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871535 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871535 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057617 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.057617 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074963 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.074963 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12023.714497 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12023.714497 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32379.162831 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32379.162831 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13304.187030 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13304.187030 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17279.047400 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 17279.047400 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16294.202638 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 16294.202638 # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2536037000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2536037000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96750709000 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 96750709000 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070581 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070581 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037737 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037737 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871459 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871459 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057635 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.057635 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074989 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.074989 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12034.141766 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12034.141766 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32500.976640 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32500.976640 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13340.408772 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13340.408772 # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17316.094236 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 17316.094236 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16330.893218 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16330.893218 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 49844829 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 2698695 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2698173 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 2694994 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2694474 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 13773 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 13773 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 1541433 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 1541461 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46721 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2183 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2183 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 313150 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 313150 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1590153 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5974271 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8035 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18003 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 7590462 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50884480 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203815525 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 233856 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 598208 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 255532069 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 255511461 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 3309120 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 3832514500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::ReadExReq 313073 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 313073 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1581243 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5975195 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7975 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18479 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 7582892 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50599360 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203853221 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 231552 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 605440 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 255289573 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 53135 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 4016986 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3.011840 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.108164 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 3969426 98.82% 98.82% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 47560 1.18% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 4016986 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 3830670000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 483000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy 478500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1195084369 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1188381870 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3051993102 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 3052447844 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 6572250 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 6536500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 12984250 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 13528750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu.l2cache.tags.replacements 87211 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 64746.136544 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 3491181 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 151954 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 22.975249 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements 87289 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 64708.241819 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 3488268 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 151942 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 22.957892 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50332.685507 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006414 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141265 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 3220.709839 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11192.593518 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.768016 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 50201.970335 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.012829 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141259 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 3236.502324 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 11269.615072 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.766021 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049144 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.170785 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.987948 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 64743 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2897 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4651 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 57056 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987900 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 32212608 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 32212608 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6366 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2878 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst 782107 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 1278785 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 2070136 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 1541433 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 1541433 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 314 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 314 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 199468 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 199468 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 6366 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker 2878 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 782107 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 1478253 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2269604 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 6366 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker 2878 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 782107 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1478253 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2269604 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049385 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.171961 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.987369 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 64653 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2860 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4737 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56942 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986526 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 32181921 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 32181921 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6616 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2866 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst 777686 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 1279269 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 2066437 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 1541461 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 1541461 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 312 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 312 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 199613 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 199613 # number of ReadExReq hits
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1789530750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2574457250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 13262825 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 13262825 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6444689027 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6444689027 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 48750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 287750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 784590000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8234219777 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 9019146277 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 48750 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 287750 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 784590000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8234219777 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 9019146277 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 12929 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 142092 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 155028 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 138750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 301500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 792612500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1813424750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2606477500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 13194319 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 13194319 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6481465525 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6481465525 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 138750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 301500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 792612500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8294890275 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 9087943025 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 138750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 301500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 792612500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8294890275 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 9087943025 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86655868500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86655868500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370634000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370634000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89026502500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89026502500 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001734 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016304 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021907 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019705 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808420 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808420 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.363017 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.363017 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001734 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016304 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087820 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.064039 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001734 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016304 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087820 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.064039 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48750 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 57550 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60525.341356 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62479.252496 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61869.631828 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10009.679245 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10009.679245 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56692.990024 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56692.990024 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48750 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60525.341356 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57857.487595 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58080.123880 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48750 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60525.341356 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57857.487595 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58080.123880 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000302 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001742 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016353 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021895 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019721 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808706 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808706 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362397 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362397 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000302 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001742 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016353 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087658 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.064033 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000302 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001742 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016353 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087658 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.064033 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69375 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 60300 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61305.011989 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63324.536439 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62696.401511 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10003.274450 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10003.274450 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57128.073025 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57128.073025 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69375 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61305.011989 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58376.898594 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58621.300830 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69375 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61305.011989 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58376.898594 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58621.300830 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
---------- Begin Simulation Statistics ----------
sim_seconds 0.200409 # Number of seconds simulated
-sim_ticks 200409284500 # Number of ticks simulated
-final_tick 4321214250500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 200409271000 # Number of ticks simulated
+final_tick 4321213476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 23274047 # Simulator instruction rate (inst/s)
-host_op_rate 23274036 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 8904961694 # Simulator tick rate (ticks/s)
-host_mem_usage 483300 # Number of bytes of host memory used
-host_seconds 22.51 # Real time elapsed on the host
-sim_insts 523790075 # Number of instructions simulated
-sim_ops 523790075 # Number of ops (including micro ops) simulated
+host_inst_rate 15445218 # Simulator instruction rate (inst/s)
+host_op_rate 15445213 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5909651303 # Simulator tick rate (ticks/s)
+host_mem_usage 534848 # Number of bytes of host memory used
+host_seconds 33.91 # Real time elapsed on the host
+sim_insts 523780905 # Number of instructions simulated
+sim_ops 523780905 # Number of ops (including micro ops) simulated
testsys.voltage_domain.voltage 1 # Voltage in Volts
testsys.clk_domain.clock 1000 # Clock period in ticks
-testsys.physmem.bytes_read::cpu.inst 81046720 # Number of bytes read from this memory
-testsys.physmem.bytes_read::cpu.data 27826276 # Number of bytes read from this memory
+testsys.physmem.bytes_read::cpu.inst 81044080 # Number of bytes read from this memory
+testsys.physmem.bytes_read::cpu.data 27825116 # Number of bytes read from this memory
testsys.physmem.bytes_read::tsunami.ethernet 57260496 # Number of bytes read from this memory
-testsys.physmem.bytes_read::total 166133492 # Number of bytes read from this memory
-testsys.physmem.bytes_inst_read::cpu.inst 81046720 # Number of instructions bytes read from this memory
-testsys.physmem.bytes_inst_read::total 81046720 # Number of instructions bytes read from this memory
-testsys.physmem.bytes_written::cpu.data 16606680 # Number of bytes written to this memory
+testsys.physmem.bytes_read::total 166129692 # Number of bytes read from this memory
+testsys.physmem.bytes_inst_read::cpu.inst 81044080 # Number of instructions bytes read from this memory
+testsys.physmem.bytes_inst_read::total 81044080 # Number of instructions bytes read from this memory
+testsys.physmem.bytes_written::cpu.data 16605404 # Number of bytes written to this memory
testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory
-testsys.physmem.bytes_written::total 16607582 # Number of bytes written to this memory
-testsys.physmem.num_reads::cpu.inst 20261680 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::cpu.data 3842559 # Number of read requests responded to by this memory
+testsys.physmem.bytes_written::total 16606306 # Number of bytes written to this memory
+testsys.physmem.num_reads::cpu.inst 20261020 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::cpu.data 3842409 # Number of read requests responded to by this memory
testsys.physmem.num_reads::tsunami.ethernet 2385836 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::total 26490075 # Number of read requests responded to by this memory
-testsys.physmem.num_writes::cpu.data 2258392 # Number of write requests responded to by this memory
+testsys.physmem.num_reads::total 26489265 # Number of read requests responded to by this memory
+testsys.physmem.num_writes::cpu.data 2258228 # Number of write requests responded to by this memory
testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory
-testsys.physmem.num_writes::total 2258423 # Number of write requests responded to by this memory
-testsys.physmem.bw_read::cpu.inst 404406014 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::cpu.data 138847240 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::tsunami.ethernet 285717781 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::total 828971035 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::cpu.inst 404406014 # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::total 404406014 # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::cpu.data 82863826 # Write bandwidth from this memory (bytes/s)
+testsys.physmem.num_writes::total 2258259 # Number of write requests responded to by this memory
+testsys.physmem.bw_read::cpu.inst 404392869 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::cpu.data 138841461 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::tsunami.ethernet 285717800 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::total 828952130 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_inst_read::cpu.inst 404392869 # Instruction read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_inst_read::total 404392869 # Instruction read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_write::cpu.data 82857464 # Write bandwidth from this memory (bytes/s)
testsys.physmem.bw_write::tsunami.ethernet 4501 # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::total 82868326 # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.inst 404406014 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.data 221711065 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::tsunami.ethernet 285722281 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::total 911839361 # Total bandwidth to/from this memory (bytes/s)
-testsys.membus.throughput 916540501 # Throughput (bytes/s)
-testsys.membus.data_through_bus 183683226 # Total data (bytes)
-testsys.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+testsys.physmem.bw_write::total 82861965 # Write bandwidth from this memory (bytes/s)
+testsys.physmem.bw_total::cpu.inst 404392869 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::cpu.data 221698925 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::tsunami.ethernet 285722301 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::total 911814095 # Total bandwidth to/from this memory (bytes/s)
+testsys.membus.trans_dist::ReadReq 26478762 # Transaction distribution
+testsys.membus.trans_dist::ReadResp 26587372 # Transaction distribution
+testsys.membus.trans_dist::WriteReq 2189273 # Transaction distribution
+testsys.membus.trans_dist::WriteResp 2189273 # Transaction distribution
+testsys.membus.trans_dist::LoadLockedReq 108610 # Transaction distribution
+testsys.membus.trans_dist::StoreCondReq 108528 # Transaction distribution
+testsys.membus.trans_dist::StoreCondResp 108528 # Transaction distribution
+testsys.membus.pkt_count_testsys.cpu.icache_port::testsys.physmem.port 40522040 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.icache_port::total 40522040 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.bridge.slave 275298 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.physmem.port 12201274 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.dcache_port::total 12476572 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.iobridge.master::testsys.physmem.port 4771734 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.iobridge.master::total 4771734 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count::total 57770346 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.icache_port::testsys.physmem.port 81044080 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.icache_port::total 81044080 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.bridge.slave 942152 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.physmem.port 44430520 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.dcache_port::total 45372672 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port 57261398 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.iobridge.master::total 57261398 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size::total 183678150 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.snoops 0 # Total snoops (count)
+testsys.membus.snoop_fanout::samples 28747524 # Request fanout histogram
+testsys.membus.snoop_fanout::mean 0.787786 # Request fanout histogram
+testsys.membus.snoop_fanout::stdev 0.408876 # Request fanout histogram
+testsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+testsys.membus.snoop_fanout::0 6100637 21.22% 21.22% # Request fanout histogram
+testsys.membus.snoop_fanout::1 22646887 78.78% 100.00% # Request fanout histogram
+testsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram
+testsys.membus.snoop_fanout::max_value 1 # Request fanout histogram
+testsys.membus.snoop_fanout::total 28747524 # Request fanout histogram
testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
testsys.cpu.dtb.fetch_misses 0 # ITB misses
testsys.cpu.dtb.fetch_acv 0 # ITB acv
testsys.cpu.dtb.fetch_accesses 0 # ITB accesses
-testsys.cpu.dtb.read_hits 3916918 # DTB read hits
+testsys.cpu.dtb.read_hits 3916768 # DTB read hits
testsys.cpu.dtb.read_misses 3287 # DTB read misses
testsys.cpu.dtb.read_acv 80 # DTB read access violations
testsys.cpu.dtb.read_accesses 225414 # DTB read accesses
-testsys.cpu.dtb.write_hits 2316885 # DTB write hits
+testsys.cpu.dtb.write_hits 2316721 # DTB write hits
testsys.cpu.dtb.write_misses 528 # DTB write misses
testsys.cpu.dtb.write_acv 81 # DTB write access violations
testsys.cpu.dtb.write_accesses 109988 # DTB write accesses
-testsys.cpu.dtb.data_hits 6233803 # DTB hits
+testsys.cpu.dtb.data_hits 6233489 # DTB hits
testsys.cpu.dtb.data_misses 3815 # DTB misses
testsys.cpu.dtb.data_acv 161 # DTB access violations
testsys.cpu.dtb.data_accesses 335402 # DTB accesses
-testsys.cpu.itb.fetch_hits 4052211 # ITB hits
+testsys.cpu.itb.fetch_hits 4052237 # ITB hits
testsys.cpu.itb.fetch_misses 1497 # ITB misses
testsys.cpu.itb.fetch_acv 69 # ITB acv
-testsys.cpu.itb.fetch_accesses 4053708 # ITB accesses
+testsys.cpu.itb.fetch_accesses 4053734 # ITB accesses
testsys.cpu.itb.read_hits 0 # DTB read hits
testsys.cpu.itb.read_misses 0 # DTB read misses
testsys.cpu.itb.read_acv 0 # DTB read access violations
testsys.cpu.itb.data_misses 0 # DTB misses
testsys.cpu.itb.data_acv 0 # DTB access violations
testsys.cpu.itb.data_accesses 0 # DTB accesses
-testsys.cpu.numCycles 400804755 # number of cpu cycles simulated
+testsys.cpu.numCycles 400825859 # number of cpu cycles simulated
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-testsys.cpu.committedInsts 20257704 # Number of instructions committed
-testsys.cpu.committedOps 20257704 # Number of ops (including micro ops) committed
-testsys.cpu.num_int_alu_accesses 18837017 # Number of integer alu accesses
+testsys.cpu.committedInsts 20257044 # Number of instructions committed
+testsys.cpu.committedOps 20257044 # Number of ops (including micro ops) committed
+testsys.cpu.num_int_alu_accesses 18836392 # Number of integer alu accesses
testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses
-testsys.cpu.num_func_calls 1221180 # number of times a function call or return occured
-testsys.cpu.num_conditional_control_insts 1442148 # number of instructions that are conditional controls
-testsys.cpu.num_int_insts 18837017 # number of integer instructions
+testsys.cpu.num_func_calls 1221158 # number of times a function call or return occured
+testsys.cpu.num_conditional_control_insts 1442105 # number of instructions that are conditional controls
+testsys.cpu.num_int_insts 18836392 # number of integer instructions
testsys.cpu.num_fp_insts 17380 # number of float instructions
-testsys.cpu.num_int_register_reads 24787248 # number of times the integer registers were read
-testsys.cpu.num_int_register_writes 14693875 # number of times the integer registers were written
+testsys.cpu.num_int_register_reads 24786330 # number of times the integer registers were read
+testsys.cpu.num_int_register_writes 14693469 # number of times the integer registers were written
testsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read
testsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written
-testsys.cpu.num_mem_refs 6263046 # number of memory refs
-testsys.cpu.num_load_insts 3944033 # Number of load instructions
-testsys.cpu.num_store_insts 2319013 # Number of store instructions
-testsys.cpu.num_idle_cycles 380542207.362158 # Number of idle cycles
-testsys.cpu.num_busy_cycles 20262547.637842 # Number of busy cycles
-testsys.cpu.not_idle_fraction 0.050555 # Percentage of non-idle cycles
-testsys.cpu.idle_fraction 0.949445 # Percentage of idle cycles
-testsys.cpu.Branches 2929848 # Number of branches fetched
-testsys.cpu.op_class::No_OpClass 712819 3.52% 3.52% # Class of executed instruction
-testsys.cpu.op_class::IntAlu 12147338 59.95% 63.47% # Class of executed instruction
+testsys.cpu.num_mem_refs 6262732 # number of memory refs
+testsys.cpu.num_load_insts 3943883 # Number of load instructions
+testsys.cpu.num_store_insts 2318849 # Number of store instructions
+testsys.cpu.num_idle_cycles 380582482.461103 # Number of idle cycles
+testsys.cpu.num_busy_cycles 20243376.538897 # Number of busy cycles
+testsys.cpu.not_idle_fraction 0.050504 # Percentage of non-idle cycles
+testsys.cpu.idle_fraction 0.949496 # Percentage of idle cycles
+testsys.cpu.Branches 2929782 # Number of branches fetched
+testsys.cpu.op_class::No_OpClass 712785 3.52% 3.52% # Class of executed instruction
+testsys.cpu.op_class::IntAlu 12147004 59.95% 63.47% # Class of executed instruction
testsys.cpu.op_class::IntMult 21654 0.11% 63.58% # Class of executed instruction
testsys.cpu.op_class::IntDiv 0 0.00% 63.58% # Class of executed instruction
testsys.cpu.op_class::FloatAdd 4655 0.02% 63.60% # Class of executed instruction
testsys.cpu.op_class::SimdFloatMult 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.60% # Class of executed instruction
testsys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::MemRead 4230637 20.88% 84.48% # Class of executed instruction
-testsys.cpu.op_class::MemWrite 2319552 11.45% 95.93% # Class of executed instruction
-testsys.cpu.op_class::IprAccess 824102 4.07% 100.00% # Class of executed instruction
+testsys.cpu.op_class::MemRead 4230485 20.88% 84.48% # Class of executed instruction
+testsys.cpu.op_class::MemWrite 2319388 11.45% 95.93% # Class of executed instruction
+testsys.cpu.op_class::IprAccess 824126 4.07% 100.00% # Class of executed instruction
testsys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-testsys.cpu.op_class::total 20261680 # Class of executed instruction
+testsys.cpu.op_class::total 20261020 # Class of executed instruction
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
testsys.cpu.kern.inst.quiesce 19580 # number of quiesce instructions executed
-testsys.cpu.kern.inst.hwrei 153667 # number of hwrei instructions executed
+testsys.cpu.kern.inst.hwrei 153669 # number of hwrei instructions executed
testsys.cpu.kern.ipl_count::0 62779 42.67% 42.67% # number of times we switched to this ipl
testsys.cpu.kern.ipl_count::21 19625 13.34% 56.01% # number of times we switched to this ipl
testsys.cpu.kern.ipl_count::22 205 0.14% 56.15% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::31 64509 43.85% 100.00% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::total 147118 # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::31 64511 43.85% 100.00% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::total 147120 # number of times we switched to this ipl
testsys.cpu.kern.ipl_good::0 62773 43.18% 43.18% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::21 19625 13.50% 56.67% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::22 205 0.14% 56.82% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::31 62785 43.18% 100.00% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::total 145388 # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_ticks::0 194346512500 96.98% 96.98% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::0 194347611000 96.98% 96.98% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks::21 1588986000 0.79% 97.77% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks::22 8815000 0.00% 97.78% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::31 4458282500 2.22% 100.00% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::total 200402596000 # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::31 4457946500 2.22% 100.00% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::total 200403358500 # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_used::0 0.999904 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::31 0.973275 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::total 0.988241 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::31 0.973245 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::total 0.988227 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed
testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed
testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed
testsys.cpu.kern.syscall::total 83 # number of syscalls executed
testsys.cpu.kern.callpal::swpctx 438 0.34% 0.34% # number of callpals executed
testsys.cpu.kern.callpal::tbi 20 0.02% 0.36% # number of callpals executed
-testsys.cpu.kern.callpal::swpipl 106830 83.26% 83.62% # number of callpals executed
+testsys.cpu.kern.callpal::swpipl 106832 83.26% 83.62% # number of callpals executed
testsys.cpu.kern.callpal::rdps 359 0.28% 83.90% # number of callpals executed
testsys.cpu.kern.callpal::wrusp 3 0.00% 83.90% # number of callpals executed
testsys.cpu.kern.callpal::rdusp 3 0.00% 83.90% # number of callpals executed
testsys.cpu.kern.callpal::rti 20470 15.95% 99.86% # number of callpals executed
testsys.cpu.kern.callpal::callsys 140 0.11% 99.97% # number of callpals executed
testsys.cpu.kern.callpal::imb 44 0.03% 100.00% # number of callpals executed
-testsys.cpu.kern.callpal::total 128307 # number of callpals executed
+testsys.cpu.kern.callpal::total 128309 # number of callpals executed
testsys.cpu.kern.mode_switch::kernel 1280 # number of protection mode switches
-testsys.cpu.kern.mode_switch::user 702 # number of protection mode switches
+testsys.cpu.kern.mode_switch::user 706 # number of protection mode switches
testsys.cpu.kern.mode_switch::idle 19629 # number of protection mode switches
-testsys.cpu.kern.mode_good::kernel 707
-testsys.cpu.kern.mode_good::user 702
+testsys.cpu.kern.mode_good::kernel 711
+testsys.cpu.kern.mode_good::user 706
testsys.cpu.kern.mode_good::idle 5
-testsys.cpu.kern.mode_switch_good::kernel 0.552344 # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::kernel 0.555469 # fraction of useful protection mode switches
testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
testsys.cpu.kern.mode_switch_good::idle 0.000255 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::total 0.065430 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_ticks::kernel 994603000 60.01% 60.01% # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::user 533068000 32.16% 92.17% # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::idle 129740500 7.83% 100.00% # number of ticks spent at the given mode
+testsys.cpu.kern.mode_switch_good::total 0.065788 # fraction of useful protection mode switches
+testsys.cpu.kern.mode_ticks::kernel 994253000 59.96% 59.96% # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks::user 533088000 32.15% 92.11% # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks::idle 130749000 7.89% 100.00% # number of ticks spent at the given mode
testsys.cpu.kern.swap_context 438 # number of times the context was actually changed
testsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted
testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
testsys.tsunami.ethernet.postedInterrupts 2385819 # number of posts to CPU
testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-testsys.iobus.throughput 290423421 # Throughput (bytes/s)
-testsys.iobus.data_through_bus 58203550 # Total data (bytes)
+testsys.iobus.trans_dist::ReadReq 2483943 # Transaction distribution
+testsys.iobus.trans_dist::ReadResp 2483943 # Transaction distribution
+testsys.iobus.trans_dist::WriteReq 39573 # Transaction distribution
+testsys.iobus.trans_dist::WriteResp 39573 # Transaction distribution
+testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.cchip.pio 196204 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.io.pio 336 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.uart.pio 428 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.ethernet.pio 78330 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.bridge.master::total 275298 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 4771734 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::total 4771734 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count::total 5047032 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.cchip.pio 784816 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.io.pio 462 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.uart.pio 214 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.ethernet.pio 156660 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::total 942152 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 57261398 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total 57261398 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size::total 58203550 # Cumulative packet size per connected master and slave (bytes)
drivesys.voltage_domain.voltage 1 # Voltage in Volts
drivesys.clk_domain.clock 1000 # Clock period in ticks
drivesys.physmem.bytes_read::cpu.inst 76205572 # Number of bytes read from this memory
drivesys.physmem.bytes_read::cpu.data 26284292 # Number of bytes read from this memory
-drivesys.physmem.bytes_read::tsunami.ethernet 57260526 # Number of bytes read from this memory
-drivesys.physmem.bytes_read::total 159750390 # Number of bytes read from this memory
+drivesys.physmem.bytes_read::tsunami.ethernet 57260550 # Number of bytes read from this memory
+drivesys.physmem.bytes_read::total 159750414 # Number of bytes read from this memory
drivesys.physmem.bytes_inst_read::cpu.inst 76205572 # Number of instructions bytes read from this memory
drivesys.physmem.bytes_inst_read::total 76205572 # Number of instructions bytes read from this memory
drivesys.physmem.bytes_written::cpu.data 14619632 # Number of bytes written to this memory
drivesys.physmem.bytes_written::total 14620696 # Number of bytes written to this memory
drivesys.physmem.num_reads::cpu.inst 19051393 # Number of read requests responded to by this memory
drivesys.physmem.num_reads::cpu.data 3647049 # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::tsunami.ethernet 2385838 # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::total 25084280 # Number of read requests responded to by this memory
+drivesys.physmem.num_reads::tsunami.ethernet 2385839 # Number of read requests responded to by this memory
+drivesys.physmem.num_reads::total 25084281 # Number of read requests responded to by this memory
drivesys.physmem.num_writes::cpu.data 2024776 # Number of write requests responded to by this memory
drivesys.physmem.num_writes::tsunami.ethernet 37 # Number of write requests responded to by this memory
drivesys.physmem.num_writes::total 2024813 # Number of write requests responded to by this memory
-drivesys.physmem.bw_read::cpu.inst 380249708 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::cpu.data 131153065 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::tsunami.ethernet 285717930 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::total 797120704 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::cpu.inst 380249708 # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::total 380249708 # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::cpu.data 72948876 # Write bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::cpu.inst 380249734 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::cpu.data 131153074 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::tsunami.ethernet 285718069 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::total 797120878 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_inst_read::cpu.inst 380249734 # Instruction read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_inst_read::total 380249734 # Instruction read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_write::cpu.data 72948881 # Write bandwidth from this memory (bytes/s)
drivesys.physmem.bw_write::tsunami.ethernet 5309 # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::total 72954185 # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.inst 380249708 # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.data 204101941 # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::tsunami.ethernet 285723240 # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::total 870074889 # Total bandwidth to/from this memory (bytes/s)
-drivesys.membus.throughput 874808223 # Throughput (bytes/s)
-drivesys.membus.data_through_bus 175319690 # Total data (bytes)
-drivesys.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+drivesys.physmem.bw_write::total 72954190 # Write bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_total::cpu.inst 380249734 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::cpu.data 204101955 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::tsunami.ethernet 285723379 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::total 870075068 # Total bandwidth to/from this memory (bytes/s)
+drivesys.membus.trans_dist::ReadReq 25081955 # Transaction distribution
+drivesys.membus.trans_dist::ReadResp 25182911 # Transaction distribution
+drivesys.membus.trans_dist::WriteReq 1963575 # Transaction distribution
+drivesys.membus.trans_dist::WriteResp 1963575 # Transaction distribution
+drivesys.membus.trans_dist::LoadLockedReq 100956 # Transaction distribution
+drivesys.membus.trans_dist::StoreCondReq 100924 # Transaction distribution
+drivesys.membus.trans_dist::StoreCondResp 100924 # Transaction distribution
+drivesys.membus.pkt_count_drivesys.cpu.icache_port::drivesys.physmem.port 38102786 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.icache_port::total 38102786 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.bridge.slave 276632 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.physmem.port 11343650 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.dcache_port::total 11620282 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.iobridge.master::drivesys.physmem.port 4771752 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.iobridge.master::total 4771752 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count::total 54494820 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.icache_port::drivesys.physmem.port 76205572 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.icache_port::total 76205572 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.bridge.slave 948604 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.physmem.port 40903924 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.dcache_port::total 41852528 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port 57261614 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.iobridge.master::total 57261614 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size::total 175319714 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.snoops 0 # Total snoops (count)
+drivesys.membus.snoop_fanout::samples 27109094 # Request fanout histogram
+drivesys.membus.snoop_fanout::mean 0.790778 # Request fanout histogram
+drivesys.membus.snoop_fanout::stdev 0.406753 # Request fanout histogram
+drivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+drivesys.membus.snoop_fanout::0 5671825 20.92% 20.92% # Request fanout histogram
+drivesys.membus.snoop_fanout::1 21437269 79.08% 100.00% # Request fanout histogram
+drivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram
+drivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram
+drivesys.membus.snoop_fanout::total 27109094 # Request fanout histogram
drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
drivesys.cpu.itb.data_misses 0 # DTB misses
drivesys.cpu.itb.data_acv 0 # DTB access violations
drivesys.cpu.itb.data_accesses 0 # DTB accesses
-drivesys.cpu.numCycles 801631448 # number of cpu cycles simulated
+drivesys.cpu.numCycles 801651324 # number of cpu cycles simulated
drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
drivesys.cpu.committedInsts 19050784 # Number of instructions committed
drivesys.cpu.num_mem_refs 5830788 # number of memory refs
drivesys.cpu.num_load_insts 3746196 # Number of load instructions
drivesys.cpu.num_store_insts 2084592 # Number of store instructions
-drivesys.cpu.num_idle_cycles 782579974.227931 # Number of idle cycles
-drivesys.cpu.num_busy_cycles 19051473.772069 # Number of busy cycles
-drivesys.cpu.not_idle_fraction 0.023766 # Percentage of non-idle cycles
-drivesys.cpu.idle_fraction 0.976234 # Percentage of idle cycles
+drivesys.cpu.num_idle_cycles 782619252.927065 # Number of idle cycles
+drivesys.cpu.num_busy_cycles 19032071.072935 # Number of busy cycles
+drivesys.cpu.not_idle_fraction 0.023741 # Percentage of non-idle cycles
+drivesys.cpu.idle_fraction 0.976259 # Percentage of idle cycles
drivesys.cpu.Branches 2793313 # Number of branches fetched
drivesys.cpu.op_class::No_OpClass 623554 3.27% 3.27% # Class of executed instruction
drivesys.cpu.op_class::IntAlu 11538627 60.57% 63.84% # Class of executed instruction
drivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device
drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
drivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
-drivesys.tsunami.ethernet.descDMAReads 2385809 # Number of descriptors the device read w/ DMA
+drivesys.tsunami.ethernet.descDMAReads 2385810 # Number of descriptors the device read w/ DMA
drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
-drivesys.tsunami.ethernet.descDmaReadBytes 57259416 # number of descriptor bytes read w/ DMA
+drivesys.tsunami.ethernet.descDmaReadBytes 57259440 # number of descriptor bytes read w/ DMA
drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
drivesys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s)
drivesys.tsunami.ethernet.totPackets 13 # Total Packets
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
drivesys.tsunami.ethernet.postedTxIdle 19726 # number of TxIdle interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
-drivesys.tsunami.ethernet.totalTxIdle 2385809 # total number of TxIdle written to ISR
+drivesys.tsunami.ethernet.totalTxIdle 2385810 # total number of TxIdle written to ISR
drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
-drivesys.tsunami.ethernet.postedInterrupts 2385830 # number of posts to CPU
+drivesys.tsunami.ethernet.postedInterrupts 2385831 # number of posts to CPU
drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-drivesys.iobus.throughput 290456573 # Throughput (bytes/s)
-drivesys.iobus.data_through_bus 58210194 # Total data (bytes)
+drivesys.iobus.trans_dist::ReadReq 2484469 # Transaction distribution
+drivesys.iobus.trans_dist::ReadResp 2484469 # Transaction distribution
+drivesys.iobus.trans_dist::WriteReq 39723 # Transaction distribution
+drivesys.iobus.trans_dist::WriteResp 39723 # Transaction distribution
+drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.cchip.pio 197670 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 78962 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.bridge.master::total 276632 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 4771752 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::total 4771752 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count::total 5048384 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.cchip.pio 790680 # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 157924 # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.bridge.master::total 948604 # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 57261614 # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total 57261614 # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size::total 58210218 # Cumulative packet size per connected master and slave (bytes)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
sim_seconds 0.000407 # Number of seconds simulated
sim_ticks 407341500 # Number of ticks simulated
-final_tick 4321621592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+final_tick 4321620817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 11799945954 # Simulator instruction rate (inst/s)
-host_op_rate 11797124974 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 9171074905 # Simulator tick rate (ticks/s)
-host_mem_usage 483300 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
-sim_insts 523862353 # Number of instructions simulated
-sim_ops 523862353 # Number of ops (including micro ops) simulated
+host_inst_rate 7893991697 # Simulator instruction rate (inst/s)
+host_op_rate 7892445581 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6135954870 # Simulator tick rate (ticks/s)
+host_mem_usage 534848 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
+sim_insts 523853183 # Number of instructions simulated
+sim_ops 523853183 # Number of ops (including micro ops) simulated
testsys.voltage_domain.voltage 1 # Voltage in Volts
testsys.clk_domain.clock 1000 # Clock period in ticks
testsys.physmem.bytes_read::cpu.inst 144504 # Number of bytes read from this memory
testsys.physmem.bw_total::cpu.data 190601743 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::tsunami.ethernet 285696400 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::total 831047168 # Total bandwidth to/from this memory (bytes/s)
-testsys.membus.throughput 835780297 # Throughput (bytes/s)
-testsys.membus.data_through_bus 340448 # Total data (bytes)
-testsys.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+testsys.membus.trans_dist::ReadReq 47876 # Transaction distribution
+testsys.membus.trans_dist::ReadResp 48080 # Transaction distribution
+testsys.membus.trans_dist::WriteReq 3691 # Transaction distribution
+testsys.membus.trans_dist::WriteResp 3691 # Transaction distribution
+testsys.membus.trans_dist::LoadLockedReq 204 # Transaction distribution
+testsys.membus.trans_dist::StoreCondReq 204 # Transaction distribution
+testsys.membus.trans_dist::StoreCondResp 204 # Transaction distribution
+testsys.membus.pkt_count_testsys.cpu.icache_port::testsys.physmem.port 72252 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.icache_port::total 72252 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.bridge.slave 562 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.physmem.port 21438 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.dcache_port::total 22000 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.iobridge.master::testsys.physmem.port 9698 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.iobridge.master::total 9698 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count::total 103950 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.icache_port::testsys.physmem.port 144504 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.icache_port::total 144504 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.bridge.slave 1928 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.physmem.port 77640 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.dcache_port::total 79568 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port 116376 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.iobridge.master::total 116376 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size::total 340448 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.snoops 0 # Total snoops (count)
+testsys.membus.snoop_fanout::samples 51694 # Request fanout histogram
+testsys.membus.snoop_fanout::mean 0.792645 # Request fanout histogram
+testsys.membus.snoop_fanout::stdev 0.405416 # Request fanout histogram
+testsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+testsys.membus.snoop_fanout::0 10719 20.74% 20.74% # Request fanout histogram
+testsys.membus.snoop_fanout::1 40975 79.26% 100.00% # Request fanout histogram
+testsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram
+testsys.membus.snoop_fanout::max_value 1 # Request fanout histogram
+testsys.membus.snoop_fanout::total 51694 # Request fanout histogram
testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
testsys.cpu.itb.data_misses 0 # DTB misses
testsys.cpu.itb.data_acv 0 # DTB access violations
testsys.cpu.itb.data_accesses 0 # DTB accesses
-testsys.cpu.numCycles 821016 # number of cpu cycles simulated
+testsys.cpu.numCycles 821056 # number of cpu cycles simulated
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
testsys.cpu.committedInsts 36126 # Number of instructions committed
testsys.cpu.num_mem_refs 11041 # number of memory refs
testsys.cpu.num_load_insts 7105 # Number of load instructions
testsys.cpu.num_store_insts 3936 # Number of store instructions
-testsys.cpu.num_idle_cycles 784609.171892 # Number of idle cycles
-testsys.cpu.num_busy_cycles 36406.828108 # Number of busy cycles
-testsys.cpu.not_idle_fraction 0.044344 # Percentage of non-idle cycles
-testsys.cpu.idle_fraction 0.955656 # Percentage of idle cycles
+testsys.cpu.num_idle_cycles 784687.711054 # Number of idle cycles
+testsys.cpu.num_busy_cycles 36368.288946 # Number of busy cycles
+testsys.cpu.not_idle_fraction 0.044295 # Percentage of non-idle cycles
+testsys.cpu.idle_fraction 0.955705 # Percentage of idle cycles
testsys.cpu.Branches 5238 # Number of branches fetched
testsys.cpu.op_class::No_OpClass 1261 3.49% 3.49% # Class of executed instruction
testsys.cpu.op_class::IntAlu 21664 59.97% 63.46% # Class of executed instruction
testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
testsys.tsunami.ethernet.postedInterrupts 4849 # number of posts to CPU
testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-testsys.iobus.throughput 290429529 # Throughput (bytes/s)
-testsys.iobus.data_through_bus 118304 # Total data (bytes)
+testsys.iobus.trans_dist::ReadReq 5049 # Transaction distribution
+testsys.iobus.trans_dist::ReadResp 5049 # Transaction distribution
+testsys.iobus.trans_dist::WriteReq 81 # Transaction distribution
+testsys.iobus.trans_dist::WriteResp 81 # Transaction distribution
+testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.cchip.pio 402 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.ethernet.pio 160 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.bridge.master::total 562 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 9698 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::total 9698 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count::total 10260 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.cchip.pio 1608 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.ethernet.pio 320 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::total 1928 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 116376 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total 116376 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size::total 118304 # Cumulative packet size per connected master and slave (bytes)
drivesys.voltage_domain.voltage 1 # Voltage in Volts
drivesys.clk_domain.clock 1000 # Clock period in ticks
drivesys.physmem.bytes_read::cpu.inst 144608 # Number of bytes read from this memory
drivesys.physmem.bw_total::cpu.data 190601743 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::tsunami.ethernet 285755318 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::total 831361401 # Total bandwidth to/from this memory (bytes/s)
-drivesys.membus.throughput 836094530 # Throughput (bytes/s)
-drivesys.membus.data_through_bus 340576 # Total data (bytes)
-drivesys.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+drivesys.membus.trans_dist::ReadReq 47907 # Transaction distribution
+drivesys.membus.trans_dist::ReadResp 48111 # Transaction distribution
+drivesys.membus.trans_dist::WriteReq 3689 # Transaction distribution
+drivesys.membus.trans_dist::WriteResp 3689 # Transaction distribution
+drivesys.membus.trans_dist::LoadLockedReq 204 # Transaction distribution
+drivesys.membus.trans_dist::StoreCondReq 204 # Transaction distribution
+drivesys.membus.trans_dist::StoreCondResp 204 # Transaction distribution
+drivesys.membus.pkt_count_drivesys.cpu.icache_port::drivesys.physmem.port 72304 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.icache_port::total 72304 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.bridge.slave 562 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.physmem.port 21442 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.dcache_port::total 22004 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.iobridge.master::drivesys.physmem.port 9700 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.iobridge.master::total 9700 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count::total 104008 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.icache_port::drivesys.physmem.port 144608 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.icache_port::total 144608 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.bridge.slave 1928 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.physmem.port 77640 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.dcache_port::total 79568 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port 116400 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.iobridge.master::total 116400 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size::total 340576 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.snoops 0 # Total snoops (count)
+drivesys.membus.snoop_fanout::samples 51723 # Request fanout histogram
+drivesys.membus.snoop_fanout::mean 0.792723 # Request fanout histogram
+drivesys.membus.snoop_fanout::stdev 0.405360 # Request fanout histogram
+drivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+drivesys.membus.snoop_fanout::0 10721 20.73% 20.73% # Request fanout histogram
+drivesys.membus.snoop_fanout::1 41002 79.27% 100.00% # Request fanout histogram
+drivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram
+drivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram
+drivesys.membus.snoop_fanout::total 51723 # Request fanout histogram
drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
drivesys.cpu.itb.data_misses 0 # DTB misses
drivesys.cpu.itb.data_acv 0 # DTB access violations
drivesys.cpu.itb.data_accesses 0 # DTB accesses
-drivesys.cpu.numCycles 1626240 # number of cpu cycles simulated
+drivesys.cpu.numCycles 1626281 # number of cpu cycles simulated
drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
drivesys.cpu.committedInsts 36152 # Number of instructions committed
drivesys.cpu.num_mem_refs 11043 # number of memory refs
drivesys.cpu.num_load_insts 7109 # Number of load instructions
drivesys.cpu.num_store_insts 3934 # Number of store instructions
-drivesys.cpu.num_idle_cycles 1590157.359061 # Number of idle cycles
-drivesys.cpu.num_busy_cycles 36082.640939 # Number of busy cycles
-drivesys.cpu.not_idle_fraction 0.022188 # Percentage of non-idle cycles
-drivesys.cpu.idle_fraction 0.977812 # Percentage of idle cycles
+drivesys.cpu.num_idle_cycles 1590238.371734 # Number of idle cycles
+drivesys.cpu.num_busy_cycles 36042.628266 # Number of busy cycles
+drivesys.cpu.not_idle_fraction 0.022163 # Percentage of non-idle cycles
+drivesys.cpu.idle_fraction 0.977837 # Percentage of idle cycles
drivesys.cpu.Branches 5243 # Number of branches fetched
drivesys.cpu.op_class::No_OpClass 1262 3.49% 3.49% # Class of executed instruction
drivesys.cpu.op_class::IntAlu 21687 59.99% 63.48% # Class of executed instruction
drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
drivesys.tsunami.ethernet.postedInterrupts 4850 # number of posts to CPU
drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-drivesys.iobus.throughput 290488448 # Throughput (bytes/s)
-drivesys.iobus.data_through_bus 118328 # Total data (bytes)
+drivesys.iobus.trans_dist::ReadReq 5050 # Transaction distribution
+drivesys.iobus.trans_dist::ReadResp 5050 # Transaction distribution
+drivesys.iobus.trans_dist::WriteReq 81 # Transaction distribution
+drivesys.iobus.trans_dist::WriteResp 81 # Transaction distribution
+drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.cchip.pio 402 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 160 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.bridge.master::total 562 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 9700 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::total 9700 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count::total 10262 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.cchip.pio 1608 # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 320 # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.bridge.master::total 1928 # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 116400 # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total 116400 # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size::total 118328 # Cumulative packet size per connected master and slave (bytes)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
sim_seconds 0.000035 # Number of seconds simulated
-sim_ticks 35015500 # Number of ticks simulated
-final_tick 35015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 35024500 # Number of ticks simulated
+final_tick 35024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 57020 # Simulator instruction rate (inst/s)
-host_op_rate 57008 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 311836228 # Simulator tick rate (ticks/s)
-host_mem_usage 240292 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
+host_inst_rate 173753 # Simulator instruction rate (inst/s)
+host_op_rate 173686 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 950177695 # Simulator tick rate (ticks/s)
+host_mem_usage 289108 # Number of bytes of host memory used
+host_seconds 0.04 # Real time elapsed on the host
sim_insts 6400 # Number of instructions simulated
sim_ops 6400 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 533 # Number of read requests responded to by this memory
system.physmem.num_reads::total 533 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 974197141 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 974197141 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 665305365 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 665305365 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 974197141 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 974197141 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 973946809 # Total read bandwidth from this memory (bytes/s)
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system.physmem.readReqs 533 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 34917000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.bytesPerActivate::896-1023 4 4.44% 88.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 10 11.11% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 90 # Bytes accessed per row activation
-system.physmem.totQLat 3823500 # Total ticks spent queuing
-system.physmem.totMemAccLat 13817250 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 7173.55 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 25923.55 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 974.20 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 974.20 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 7.61 # Data bus utilization in percentage
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 65510.32 # Average gap between requests
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system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 15500 # Time in different power states
system.physmem.memoryStateTime::REF 1040000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 974197141 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 460 # Transaction distribution
system.membus.trans_dist::ReadResp 460 # Transaction distribution
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
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system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes)
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-system.membus.data_through_bus 34112 # Total data (bytes)
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system.membus.reqLayer0.occupancy 618000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.8 # Layer utilization (%)
system.membus.respLayer1.occupancy 4976250 # Layer occupancy (ticks)
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6400 # Number of instructions committed
system.cpu.committedOps 6400 # Number of ops (including micro ops) committed
system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 10.942344 # CPI: cycles per instruction
-system.cpu.ipc 0.091388 # IPC: instructions per cycle
-system.cpu.tickCycles 12510 # Number of cycles that the object actually ticked
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system.cpu.icache.tags.replacements 0 # number of replacements
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system.cpu.icache.tags.total_refs 2265 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 6.205479 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id
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system.cpu.icache.ReadReq_accesses::cpu.inst 2630 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2630 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for ReadReq accesses
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution
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-system.cpu.toL2Bus.data_through_bus 34176 # Total data (bytes)
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25964750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4147500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4147500 # number of ReadExReq MSHR miss cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::total 30112250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30112250 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 30112250 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997831 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56446.195652 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56446.195652 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56684.931507 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56684.931507 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56478.893058 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56478.893058 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56478.893058 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56478.893058 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56445.108696 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56445.108696 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56815.068493 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56815.068493 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 104.053835 # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse 104.075920 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1968 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11.644970 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst 104.053835 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst 0.025404 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.025404 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.inst 104.075920 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst 0.025409 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.025409 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses
system.cpu.dcache.overall_misses::total 227 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7727250 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 7727250 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8696750 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 8696750 # number of WriteReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7718250 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 7718250 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8705750 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 8705750 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.inst 16424000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 16424000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.inst 16424000 # number of overall miss cycles
system.cpu.dcache.demand_miss_rate::total 0.103417 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.inst 0.103417 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.103417 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75757.352941 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 75757.352941 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69574 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69574 # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75669.117647 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 75669.117647 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69646 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 69646 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 72352.422907 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency
system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7154500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 7154500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5130500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 5130500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7145500 # number of ReadReq MSHR miss cycles
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+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5139500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12285000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 12285000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12285000 # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate::total 0.076993 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.076993 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74526.041667 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74526.041667 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70280.821918 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70280.821918 # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74432.291667 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74432.291667 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70404.109589 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70404.109589 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency
sim_ticks 20537500 # Number of ticks simulated
final_tick 20537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 46749 # Simulator instruction rate (inst/s)
-host_op_rate 46745 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 150649735 # Simulator tick rate (ticks/s)
-host_mem_usage 236424 # Number of bytes of host memory used
-host_seconds 0.14 # Real time elapsed on the host
+host_inst_rate 100086 # Simulator instruction rate (inst/s)
+host_op_rate 100066 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 322455292 # Simulator tick rate (ticks/s)
+host_mem_usage 290128 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 6372 # Number of instructions simulated
sim_ops 6372 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bytesPerActivate::896-1023 3 3.66% 86.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 11 13.41% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 82 # Bytes accessed per row activation
-system.physmem.totQLat 4551750 # Total ticks spent queuing
-system.physmem.totMemAccLat 13683000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 4742750 # Total ticks spent queuing
+system.physmem.totMemAccLat 13874000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2435000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 9346.51 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 9738.71 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 28096.51 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 28488.71 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1517.61 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1517.61 # Average system read bandwidth in MiByte/s
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 15339250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 1517614121 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 415 # Transaction distribution
system.membus.trans_dist::ReadResp 415 # Transaction distribution
system.membus.trans_dist::ReadExReq 72 # Transaction distribution
system.membus.trans_dist::ReadExResp 72 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 974 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 974 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 31168 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 487 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 487 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 487 # Request fanout histogram
system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 3.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 4554500 # Layer occupancy (ticks)
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 1520730371 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 976 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 31232 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 488 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 488 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 488 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 244000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 528500 # Layer occupancy (ticks)
sim_ticks 3208000 # Number of ticks simulated
final_tick 3208000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 172950 # Simulator instruction rate (inst/s)
-host_op_rate 172880 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 86758979 # Simulator tick rate (ticks/s)
-host_mem_usage 253924 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
+host_inst_rate 1057772 # Simulator instruction rate (inst/s)
+host_op_rate 1055326 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 528762156 # Simulator tick rate (ticks/s)
+host_mem_usage 277832 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7980049875 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4826683292 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12806733167 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 12806733167 # Throughput (bytes/s)
-system.membus.data_through_bus 41084 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 7583 # Transaction distribution
+system.membus.trans_dist::ReadResp 7583 # Transaction distribution
+system.membus.trans_dist::WriteReq 865 # Transaction distribution
+system.membus.trans_dist::WriteResp 865 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 12800 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4096 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 16896 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 25600 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 15484 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 41084 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 8448 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.757576 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.428575 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 2048 24.24% 24.24% # Request fanout histogram
+system.membus.snoop_fanout::1 6400 75.76% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 8448 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
sim_ticks 32544000 # Number of ticks simulated
final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 550056 # Simulator instruction rate (inst/s)
-host_op_rate 549394 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2794675827 # Simulator tick rate (ticks/s)
-host_mem_usage 262632 # Number of bytes of host memory used
+host_inst_rate 485157 # Simulator instruction rate (inst/s)
+host_op_rate 484642 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2465828156 # Simulator tick rate (ticks/s)
+host_mem_usage 286540 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 877089479 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 373 # Transaction distribution
system.membus.trans_dist::ReadResp 373 # Transaction distribution
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 28544 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 446 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 446 # Request fanout histogram
system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 4014000 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 879056047 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 28608 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 447 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 447 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks)
sim_ticks 18662000 # Number of ticks simulated
final_tick 18662000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 32674 # Simulator instruction rate (inst/s)
-host_op_rate 32664 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 235769003 # Simulator tick rate (ticks/s)
-host_mem_usage 238980 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 154264 # Simulator instruction rate (inst/s)
+host_op_rate 154144 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1111892278 # Simulator tick rate (ticks/s)
+host_mem_usage 287792 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
sim_insts 2585 # Number of instructions simulated
sim_ops 2585 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bytesPerActivate::896-1023 1 2.27% 90.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 4 9.09% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 44 # Bytes accessed per row activation
-system.physmem.totQLat 1654250 # Total ticks spent queuing
-system.physmem.totMemAccLat 7429250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 1719250 # Total ticks spent queuing
+system.physmem.totMemAccLat 7494250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 5370.94 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 5581.98 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 24120.94 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 24331.98 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1056.26 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1056.26 # Average system read bandwidth in MiByte/s
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 15310750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 1056264066 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 281 # Transaction distribution
system.membus.trans_dist::ReadResp 281 # Transaction distribution
system.membus.trans_dist::ReadExReq 27 # Transaction distribution
system.membus.trans_dist::ReadExResp 27 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 616 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 616 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19712 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 19712 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19712 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 308 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 308 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 308 # Request fanout histogram
system.membus.reqLayer0.occupancy 362000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.9 # Layer utilization (%)
system.membus.respLayer1.occupancy 2870500 # Layer occupancy (ticks)
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66880.044843 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 66880.044843 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 1056264066 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 446 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 616 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14272 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 19712 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14272 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 308 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 308 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 381750 # Layer occupancy (ticks)
sim_ticks 11765500 # Number of ticks simulated
final_tick 11765500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 45706 # Simulator instruction rate (inst/s)
-host_op_rate 45696 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 225189511 # Simulator tick rate (ticks/s)
-host_mem_usage 236100 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 81487 # Simulator instruction rate (inst/s)
+host_op_rate 81445 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 401265305 # Simulator tick rate (ticks/s)
+host_mem_usage 288836 # Number of bytes of host memory used
+host_seconds 0.03 # Real time elapsed on the host
sim_insts 2387 # Number of instructions simulated
sim_ops 2387 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bytesPerActivate::896-1023 1 2.56% 84.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 6 15.38% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 39 # Bytes accessed per row activation
-system.physmem.totQLat 1710500 # Total ticks spent queuing
-system.physmem.totMemAccLat 6810500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 1802000 # Total ticks spent queuing
+system.physmem.totMemAccLat 6902000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 6288.60 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 6625.00 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 25038.60 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 25375.00 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1479.58 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1479.58 # Average system read bandwidth in MiByte/s
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 7778000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 1479580128 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 248 # Transaction distribution
system.membus.trans_dist::ReadResp 248 # Transaction distribution
system.membus.trans_dist::ReadExReq 24 # Transaction distribution
system.membus.trans_dist::ReadExResp 24 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 544 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 544 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 17408 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 272 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 272 # Request fanout histogram
system.membus.reqLayer0.occupancy 339500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
system.membus.respLayer1.occupancy 2545000 # Layer occupancy (ticks)
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 1479580128 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 544 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11968 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 17408 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11968 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 272 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 272 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 314250 # Layer occupancy (ticks)
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12706250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4451500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 17157750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1692250 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 1692250 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1694250 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 1694250 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 12706250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 6143750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 18850000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 6145750 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 18852000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 12706250 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 6143750 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 18850000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 6145750 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 18852000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 187 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 248 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67947.860963 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72975.409836 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69184.475806 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70510.416667 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70510.416667 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70593.750000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70593.750000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67947.860963 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72279.411765 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69301.470588 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72302.941176 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 69308.823529 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67947.860963 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72279.411765 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69301.470588 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72302.941176 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69308.823529 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10348750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3702000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14050750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1398750 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1398750 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1400750 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1400750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10348750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5100750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 15449500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5102750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 15451500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10348750 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5100750 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 15449500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5102750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 15451500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55340.909091 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60688.524590 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56656.250000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58281.250000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58281.250000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58364.583333 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58364.583333 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55340.909091 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60008.823529 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56799.632353 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60032.352941 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56806.985294 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55340.909091 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60008.823529 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56799.632353 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60032.352941 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56806.985294 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 46.118379 # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse 46.118209 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 729 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 8.576471 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 46.118379 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data 46.118209 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.011259 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.011259 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id
system.cpu.dcache.demand_misses::total 198 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 198 # number of overall misses
system.cpu.dcache.overall_misses::total 198 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 7443000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 7443000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 5304000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 5304000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 12747000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 12747000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 12747000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 12747000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 7447000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 7447000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 5312000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 5312000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 12759000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 12759000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 12759000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 12759000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 633 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 633 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_miss_rate::total 0.213592 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.213592 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.213592 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63615.384615 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 63615.384615 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65481.481481 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 65481.481481 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 64378.787879 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 64378.787879 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 64378.787879 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 64378.787879 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63649.572650 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 63649.572650 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65580.246914 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 65580.246914 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 64439.393939 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 64439.393939 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 131 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4512500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4512500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1717750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1717750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6230250 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6230250 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6230250 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6230250 # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1719750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 1719750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6232250 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6232250 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6232250 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6232250 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096367 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096367 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.091694 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73975.409836 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73975.409836 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71572.916667 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71572.916667 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73297.058824 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 73297.058824 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73297.058824 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 73297.058824 # average overall mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71656.250000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71656.250000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 1297500 # Number of ticks simulated
final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 741583 # Simulator instruction rate (inst/s)
-host_op_rate 738395 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 370291096 # Simulator tick rate (ticks/s)
-host_mem_usage 253628 # Number of bytes of host memory used
+host_inst_rate 828617 # Simulator instruction rate (inst/s)
+host_op_rate 824640 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 413479924 # Simulator tick rate (ticks/s)
+host_mem_usage 276508 # Number of bytes of host memory used
host_seconds 0.00 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bw_total::cpu.inst 7969171484 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3910597303 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11879768786 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 11879768786 # Throughput (bytes/s)
-system.membus.data_through_bus 15414 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 3000 # Transaction distribution
+system.membus.trans_dist::ReadResp 3000 # Transaction distribution
+system.membus.trans_dist::WriteReq 294 # Transaction distribution
+system.membus.trans_dist::WriteResp 294 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 5170 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1418 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 6588 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 10340 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 5074 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 15414 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 3294 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.784760 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.411051 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 709 21.52% 21.52% # Request fanout histogram
+system.membus.snoop_fanout::1 2585 78.48% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 3294 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
sim_ticks 16524000 # Number of ticks simulated
final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 366311 # Simulator instruction rate (inst/s)
-host_op_rate 365532 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2339184598 # Simulator tick rate (ticks/s)
-host_mem_usage 262348 # Number of bytes of host memory used
+host_inst_rate 428144 # Simulator instruction rate (inst/s)
+host_op_rate 427151 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2733498759 # Simulator tick rate (ticks/s)
+host_mem_usage 286260 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bw_total::cpu.inst 631324135 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 317598644 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 948922779 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 948922779 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 218 # Transaction distribution
system.membus.trans_dist::ReadResp 218 # Transaction distribution
system.membus.trans_dist::ReadExReq 27 # Transaction distribution
system.membus.trans_dist::ReadExResp 27 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 15680 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 245 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 245 # Request fanout histogram
system.membus.reqLayer0.occupancy 245000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.5 # Layer utilization (%)
system.membus.respLayer1.occupancy 2205000 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 948922779 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 218 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 326 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 164 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 490 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10432 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5248 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 15680 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10432 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5248 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 245 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 245 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 245 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 244500 # Layer occupancy (ticks)
sim_ticks 27911000 # Number of ticks simulated
final_tick 27911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 66829 # Simulator instruction rate (inst/s)
-host_op_rate 78212 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 404876453 # Simulator tick rate (ticks/s)
-host_mem_usage 278412 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
+host_inst_rate 116522 # Simulator instruction rate (inst/s)
+host_op_rate 136369 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 705946329 # Simulator tick rate (ticks/s)
+host_mem_usage 304192 # Number of bytes of host memory used
+host_seconds 0.04 # Real time elapsed on the host
sim_insts 4604 # Number of instructions simulated
sim_ops 5390 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bytesPerActivate::768-895 3 4.69% 84.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 10 15.62% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 64 # Bytes accessed per row activation
-system.physmem.totQLat 2525000 # Total ticks spent queuing
-system.physmem.totMemAccLat 10400000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 2575500 # Total ticks spent queuing
+system.physmem.totMemAccLat 10450500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 6011.90 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 6132.14 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 24761.90 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 24882.14 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 963.06 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 963.06 # Average system read bandwidth in MiByte/s
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 22840500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 963061159 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 377 # Transaction distribution
system.membus.trans_dist::ReadResp 377 # Transaction distribution
system.membus.trans_dist::ReadExReq 43 # Transaction distribution
system.membus.trans_dist::ReadExResp 43 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 26880 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 420 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 420 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 420 # Request fanout histogram
system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.7 # Layer utilization (%)
system.membus.respLayer1.occupancy 3924000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 14.1 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 1905 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1139 # Number of conditional branches predicted
+system.cpu.branchPred.lookups 1903 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1138 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 1574 # Number of BTB lookups
+system.cpu.branchPred.BTBLookups 1573 # Number of BTB lookups
system.cpu.branchPred.BTBHits 325 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 20.648030 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 223 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 20.661157 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 12.124674 # CPI: cycles per instruction
system.cpu.ipc 0.082476 # IPC: instructions per cycle
-system.cpu.tickCycles 10535 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 45287 # Total number of cycles that the object has spent stopped
+system.cpu.tickCycles 10521 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 45301 # Total number of cycles that the object has spent stopped
system.cpu.icache.tags.replacements 3 # number of replacements
-system.cpu.icache.tags.tagsinuse 162.198888 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 1923 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 162.201432 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 5.990654 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 5.978193 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 162.198888 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.079199 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.079199 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 162.201432 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.079200 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.079200 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 4809 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 4809 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 1923 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1923 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1923 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1923 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1923 # number of overall hits
-system.cpu.icache.overall_hits::total 1923 # number of overall hits
+system.cpu.icache.tags.tag_accesses 4801 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 4801 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits
+system.cpu.icache.overall_hits::total 1919 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses
system.cpu.icache.overall_misses::total 321 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 21494250 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 21494250 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 21494250 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 21494250 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 21494250 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 21494250 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 2244 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 2244 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 2244 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 2244 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 2244 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 2244 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143048 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.143048 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.143048 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.143048 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.143048 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.143048 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66960.280374 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 66960.280374 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 66960.280374 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 66960.280374 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 66960.280374 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 66960.280374 # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 21503250 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 21503250 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 21503250 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 21503250 # number of demand (read+write) miss cycles
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+system.cpu.icache.overall_miss_latency::total 21503250 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 2240 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 2240 # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total 2240 # number of demand (read+write) accesses
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+system.cpu.icache.overall_accesses::total 2240 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143304 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.143304 # miss rate for ReadReq accesses
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+system.cpu.icache.demand_miss_rate::total 0.143304 # miss rate for demand accesses
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+system.cpu.icache.overall_miss_rate::total 0.143304 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66988.317757 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 66988.317757 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 66988.317757 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 66988.317757 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 321 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20721750 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 20721750 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20721750 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 20721750 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20721750 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 20721750 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143048 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143048 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143048 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.143048 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143048 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.143048 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64553.738318 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64553.738318 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64553.738318 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 64553.738318 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64553.738318 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 64553.738318 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20730750 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 20730750 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20730750 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 20730750 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20730750 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 20730750 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143304 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.143304 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.143304 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64581.775701 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64581.775701 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 1070832288 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 934 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20544 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 29888 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 29888 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20544 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 29888 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 467 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 467 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 467 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 233500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 546750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 195.954343 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 195.957604 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 377 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.103448 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.954343 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.957604 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005980 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.005980 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 377 # Occupied blocks per task id
system.cpu.l2cache.demand_misses::total 428 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 428 # number of overall misses
system.cpu.l2cache.overall_misses::total 428 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26168000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 26168000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26169000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 26169000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2824000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2824000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 28992000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 28992000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 28992000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 28992000 # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 28993000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 28993000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 28993000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 28993000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 424 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 424 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 43 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_miss_rate::total 0.916488 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.916488 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.916488 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67968.831169 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 67968.831169 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67971.428571 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 67971.428571 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65674.418605 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65674.418605 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67738.317757 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 67738.317757 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67738.317757 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 67738.317757 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 67740.654206 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 67740.654206 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 420 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20973000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20973000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20974000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20974000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 2284000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2284000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23257000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 23257000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23257000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 23257000 # number of overall MSHR miss cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::total 23258000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23258000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 23258000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.889151 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889151 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899358 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55631.299735 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55631.299735 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55633.952255 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55633.952255 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53116.279070 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53116.279070 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55373.809524 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55373.809524 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55373.809524 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55373.809524 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 86.663656 # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse 86.665340 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1919 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 13.143836 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst 86.663656 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst 0.021158 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.021158 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.inst 86.665340 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst 0.021159 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.021159 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.inst 182 # number of overall misses
system.cpu.dcache.overall_misses::total 182 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6958741 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 6958741 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6950741 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 6950741 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 4586500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4586500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst 11545241 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 11545241 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst 11545241 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 11545241 # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst 11537241 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 11537241 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst 11537241 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 11537241 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.inst 1166 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1166 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.inst 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_miss_rate::total 0.087542 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.inst 0.087542 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.087542 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60510.791304 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 60510.791304 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60441.226087 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 60441.226087 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68455.223881 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 68455.223881 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63435.390110 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63435.390110 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63435.390110 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63435.390110 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 63391.434066 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 63391.434066 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.inst 146 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6265258 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 6265258 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6257258 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 6257258 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2867000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2867000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9132258 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 9132258 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9132258 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 9132258 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9124258 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 9124258 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9124258 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 9124258 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.088336 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088336 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.047097 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.070226 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.070226 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60827.747573 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.747573 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60750.077670 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60750.077670 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66674.418605 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66674.418605 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62549.712329 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 62549.712329 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62549.712329 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 62549.712329 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 16223000 # Number of ticks simulated
final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 32617 # Simulator instruction rate (inst/s)
-host_op_rate 38195 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 115221437 # Simulator tick rate (ticks/s)
-host_mem_usage 253076 # Number of bytes of host memory used
-host_seconds 0.14 # Real time elapsed on the host
+host_inst_rate 55920 # Simulator instruction rate (inst/s)
+host_op_rate 65484 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 197542740 # Simulator tick rate (ticks/s)
+host_mem_usage 304472 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5377 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 209 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
-system.physmem.totQLat 2970000 # Total ticks spent queuing
-system.physmem.totMemAccLat 10413750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 3126000 # Total ticks spent queuing
+system.physmem.totMemAccLat 10569750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 7481.11 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 7874.06 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 26231.11 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 26624.06 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1566.17 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1566.17 # Average system read bandwidth in MiByte/s
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 15315250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 1566171485 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 355 # Transaction distribution
system.membus.trans_dist::ReadResp 355 # Transaction distribution
system.membus.trans_dist::ReadExReq 42 # Transaction distribution
system.membus.trans_dist::ReadExResp 42 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 25408 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 397 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 397 # Request fanout histogram
system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 3.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks)
system.cpu.cc_regfile_writes 3302 # number of cc regfile writes
system.cpu.misc_regfile_reads 3189 # number of misc regfile reads
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 1735807187 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 28160 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::9 441 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
system.cpu.icache.tags.replacements 1 # number of replacements
-system.cpu.icache.tags.tagsinuse 150.758993 # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse 150.722255 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 5.666667 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 150.758993 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.073613 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.073613 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 150.722255 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.073595 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.073595 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 293 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id
system.cpu.icache.demand_misses::total 402 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 402 # number of overall misses
system.cpu.icache.overall_misses::total 402 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 25574000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 25574000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 25574000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 25574000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 25574000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 25574000 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 25584000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 25584000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 25584000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 25584000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 25584000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 25584000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses
system.cpu.icache.demand_miss_rate::total 0.194391 # miss rate for demand accesses
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-system.cpu.dcache.demand_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000016 # Number of seconds simulated
-sim_ticks 16223000 # Number of ticks simulated
-final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000012 # Number of seconds simulated
+sim_ticks 11859500 # Number of ticks simulated
+final_tick 11859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 35590 # Simulator instruction rate (inst/s)
-host_op_rate 41676 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 125719954 # Simulator tick rate (ticks/s)
-host_mem_usage 252016 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
+host_inst_rate 50616 # Simulator instruction rate (inst/s)
+host_op_rate 59274 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 130716325 # Simulator tick rate (ticks/s)
+host_mem_usage 300356 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5377 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory
-system.physmem.bytes_read::total 25408 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 397 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1084879492 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 481291993 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1566171485 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1084879492 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1084879492 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1084879492 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 481291993 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1566171485 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 397 # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst 3776 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 5888 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher 37184 # Number of bytes read from this memory
+system.physmem.bytes_read::total 46848 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 3776 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 3776 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 59 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 92 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher 581 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 732 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 318394536 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 496479615 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher 3135376702 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3950250854 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 318394536 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 318394536 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 318394536 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 496479615 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher 3135376702 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3950250854 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 733 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 733 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 46912 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 46912 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 90 # Per bank write bursts
-system.physmem.perBankRdBursts::1 46 # Per bank write bursts
-system.physmem.perBankRdBursts::2 20 # Per bank write bursts
-system.physmem.perBankRdBursts::3 43 # Per bank write bursts
-system.physmem.perBankRdBursts::4 18 # Per bank write bursts
-system.physmem.perBankRdBursts::5 32 # Per bank write bursts
-system.physmem.perBankRdBursts::6 35 # Per bank write bursts
-system.physmem.perBankRdBursts::7 10 # Per bank write bursts
-system.physmem.perBankRdBursts::8 4 # Per bank write bursts
-system.physmem.perBankRdBursts::9 8 # Per bank write bursts
-system.physmem.perBankRdBursts::10 28 # Per bank write bursts
-system.physmem.perBankRdBursts::11 42 # Per bank write bursts
-system.physmem.perBankRdBursts::12 9 # Per bank write bursts
-system.physmem.perBankRdBursts::13 6 # Per bank write bursts
+system.physmem.perBankRdBursts::0 143 # Per bank write bursts
+system.physmem.perBankRdBursts::1 90 # Per bank write bursts
+system.physmem.perBankRdBursts::2 40 # Per bank write bursts
+system.physmem.perBankRdBursts::3 73 # Per bank write bursts
+system.physmem.perBankRdBursts::4 58 # Per bank write bursts
+system.physmem.perBankRdBursts::5 88 # Per bank write bursts
+system.physmem.perBankRdBursts::6 52 # Per bank write bursts
+system.physmem.perBankRdBursts::7 18 # Per bank write bursts
+system.physmem.perBankRdBursts::8 12 # Per bank write bursts
+system.physmem.perBankRdBursts::9 28 # Per bank write bursts
+system.physmem.perBankRdBursts::10 34 # Per bank write bursts
+system.physmem.perBankRdBursts::11 47 # Per bank write bursts
+system.physmem.perBankRdBursts::12 17 # Per bank write bursts
+system.physmem.perBankRdBursts::13 19 # Per bank write bursts
system.physmem.perBankRdBursts::14 0 # Per bank write bursts
-system.physmem.perBankRdBursts::15 6 # Per bank write bursts
+system.physmem.perBankRdBursts::15 14 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 16156000 # Total gap between requests
+system.physmem.totGap 11846500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 397 # Read request sizes (log2)
+system.physmem.readPktSize::6 733 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 96 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 60 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 51 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 53 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 48 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 17 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 18 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 396.190476 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 265.364013 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 334.900990 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 12 19.05% 19.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 16 25.40% 44.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 9 14.29% 71.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
-system.physmem.totQLat 2970000 # Total ticks spent queuing
-system.physmem.totMemAccLat 10413750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 7481.11 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 712.533333 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 570.872295 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 336.283550 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 4 6.67% 6.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 5 8.33% 15.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 4 6.67% 21.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 1 1.67% 23.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 4 6.67% 30.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 10 16.67% 46.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 4 6.67% 53.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 5 8.33% 61.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 23 38.33% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation
+system.physmem.totQLat 17284989 # Total ticks spent queuing
+system.physmem.totMemAccLat 31028739 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 3665000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 23581.16 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 26231.11 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1566.17 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 42331.16 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 3955.65 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1566.17 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 3955.65 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 12.24 # Data bus utilization in percentage
-system.physmem.busUtilRead 12.24 # Data bus utilization in percentage for reads
+system.physmem.busUtil 30.90 # Data bus utilization in percentage
+system.physmem.busUtilRead 30.90 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 5.25 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 331 # Number of row buffer hits during reads
+system.physmem.readRowHits 662 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 90.31 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 40695.21 # Average gap between requests
-system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
-system.physmem.memoryStateTime::REF 520000 # Time in different power states
+system.physmem.avgGap 16161.66 # Average gap between requests
+system.physmem.pageHitRate 90.31 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 6500 # Time in different power states
+system.physmem.memoryStateTime::REF 260000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 15315250 # Time in different power states
+system.physmem.memoryStateTime::ACT 7800750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 1566171485 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 355 # Transaction distribution
-system.membus.trans_dist::ReadResp 355 # Transaction distribution
-system.membus.trans_dist::ReadExReq 42 # Transaction distribution
-system.membus.trans_dist::ReadExResp 42 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 25408 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 3.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 22.8 # Layer utilization (%)
+system.membus.trans_dist::ReadReq 704 # Transaction distribution
+system.membus.trans_dist::ReadResp 702 # Transaction distribution
+system.membus.trans_dist::ReadExReq 29 # Transaction distribution
+system.membus.trans_dist::ReadExResp 29 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1464 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1464 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46784 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 46784 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 733 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 733 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 733 # Request fanout histogram
+system.membus.reqLayer0.occupancy 803724 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 6.8 # Layer utilization (%)
+system.membus.respLayer1.occupancy 6629985 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 55.9 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 2638 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 2101 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 783 # Number of BTB hits
+system.cpu.branchPred.lookups 2560 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1531 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 510 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 939 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 497 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 37.267968 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 354 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 52.928647 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 297 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
-system.cpu.numCycles 32447 # number of cpu cycles simulated
+system.cpu.numCycles 23720 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 7786 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 12484 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2638 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1137 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 4850 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1010 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 2068 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 320 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 13433 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.098935 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.478489 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 4394 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 12370 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2560 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 794 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 11397 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1062 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 322 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 84 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 4117 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 139 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 16747 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.858243 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.204203 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 10743 79.97% 79.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 265 1.97% 81.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 241 1.79% 83.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 235 1.75% 85.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 238 1.77% 87.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 291 2.17% 89.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 141 1.05% 90.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 175 1.30% 91.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1104 8.22% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 9977 59.57% 59.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2687 16.04% 75.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 563 3.36% 78.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 3520 21.02% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 13433 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.081302 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.384751 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 6529 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 4272 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2145 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 138 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 349 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 390 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 12118 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 349 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 6736 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 846 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 2304 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2064 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 1134 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 11483 # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents 163 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 117 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 963 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 11820 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 52846 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 12757 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups
+system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 16747 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.107926 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.521501 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 4535 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 6577 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 5106 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 160 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 369 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 338 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 165 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 10143 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 1684 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 369 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 5681 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 3207 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 2422 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 4105 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 963 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 9048 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 426 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 101 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 748 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 9432 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 41033 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 9977 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 18 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6326 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 43 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 443 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2313 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 10354 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8358 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 4760 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 12835 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 13433 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.622199 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.376807 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 3938 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 31 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 472 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 1824 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1295 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 8517 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 7242 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 203 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 2981 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 8241 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 16747 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.432436 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 0.833231 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 10179 75.78% 75.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1183 8.81% 84.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 748 5.57% 90.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 453 3.37% 93.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 362 2.69% 96.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 286 2.13% 98.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 135 1.00% 99.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 64 0.48% 99.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 23 0.17% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 12501 74.65% 74.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1960 11.70% 86.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 1628 9.72% 96.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 606 3.62% 99.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 52 0.31% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::total 13433 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 16747 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 9 5.33% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 80 47.34% 52.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 80 47.34% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 437 29.61% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 482 32.66% 62.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 557 37.74% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5041 60.31% 60.31% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.42% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2009 24.04% 84.46% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1299 15.54% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 4533 62.59% 62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 6 0.08% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.72% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 1613 22.27% 84.99% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1087 15.01% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8358 # Type of FU issued
-system.cpu.iq.rate 0.257589 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 169 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.020220 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 30275 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 15052 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 7570 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 31 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 8484 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 25 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 7242 # Type of FU issued
+system.cpu.iq.rate 0.305312 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1476 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.203811 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 32865 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 11527 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 6638 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 45 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 18 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 8689 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 29 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 15 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1286 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 701 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 797 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 357 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 39 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 349 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 800 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 10411 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2313 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 252 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 364 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8063 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 1908 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 295 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 369 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 705 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 159 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 8571 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 1824 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1295 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 151 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 362 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 6828 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 1428 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 11 # number of nop insts executed
-system.cpu.iew.exec_refs 3148 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1457 # Number of branches executed
-system.cpu.iew.exec_stores 1240 # Number of stores executed
-system.cpu.iew.exec_rate 0.248498 # Inst execution rate
-system.cpu.iew.wb_sent 7735 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 7601 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 3572 # num instructions producing a value
-system.cpu.iew.wb_consumers 6998 # num instructions consuming a value
+system.cpu.iew.exec_nop 14 # number of nop insts executed
+system.cpu.iew.exec_refs 2449 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1283 # Number of branches executed
+system.cpu.iew.exec_stores 1021 # Number of stores executed
+system.cpu.iew.exec_rate 0.287858 # Inst execution rate
+system.cpu.iew.wb_sent 6699 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 6654 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 3045 # num instructions producing a value
+system.cpu.iew.wb_consumers 5519 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.234259 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.510432 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.280523 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.551730 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 5037 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 2714 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 324 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 12552 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.428378 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.273949 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 348 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 16184 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.332242 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 0.986798 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 10495 83.61% 83.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 893 7.11% 90.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 426 3.39% 94.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 211 1.68% 95.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 111 0.88% 96.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 212 1.69% 98.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 50 0.40% 98.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 37 0.29% 99.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 117 0.93% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 13581 83.92% 83.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1345 8.31% 92.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 599 3.70% 95.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 281 1.74% 97.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 168 1.04% 98.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 78 0.48% 99.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 47 0.29% 99.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 33 0.20% 99.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 52 0.32% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 12552 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 16184 # Number of insts commited each cycle
system.cpu.commit.committedInsts 4591 # Number of instructions committed
system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 5377 # Class of committed instruction
-system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 52 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 22692 # The number of ROB reads
-system.cpu.rob.rob_writes 21719 # The number of ROB writes
-system.cpu.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 19014 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 24066 # The number of ROB reads
+system.cpu.rob.rob_writes 16749 # The number of ROB writes
+system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 6973 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4591 # Number of Instructions Simulated
system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 7.067523 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.067523 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.141492 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.141492 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 7944 # number of integer regfile reads
-system.cpu.int_regfile_writes 4420 # number of integer regfile writes
-system.cpu.fp_regfile_reads 31 # number of floating regfile reads
-system.cpu.cc_regfile_reads 28734 # number of cc regfile reads
-system.cpu.cc_regfile_writes 3302 # number of cc regfile writes
-system.cpu.misc_regfile_reads 3189 # number of misc regfile reads
+system.cpu.cpi 5.166630 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 5.166630 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.193550 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.193550 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 6786 # number of integer regfile reads
+system.cpu.int_regfile_writes 3839 # number of integer regfile writes
+system.cpu.fp_regfile_reads 16 # number of floating regfile reads
+system.cpu.cc_regfile_reads 24301 # number of cc regfile reads
+system.cpu.cc_regfile_writes 2919 # number of cc regfile writes
+system.cpu.misc_regfile_reads 2642 # number of misc regfile reads
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 1735807187 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 28160 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
-system.cpu.icache.tags.replacements 1 # number of replacements
-system.cpu.icache.tags.tagsinuse 150.758993 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 5.666667 # Average number of references to valid blocks.
+system.cpu.toL2Bus.trans_dist::ReadReq 408 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 407 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq 1026 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 40 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 40 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 608 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 895 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19456 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 1026 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 1474 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5.696065 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.460111 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 448 30.39% 30.39% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 1026 69.61% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 1474 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 224000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 461250 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 3.9 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 223747 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%)
+system.cpu.icache.tags.replacements 47 # number of replacements
+system.cpu.icache.tags.tagsinuse 138.950029 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 3784 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 304 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 12.447368 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 150.758993 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.073613 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.073613 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 293 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.143066 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 4430 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 4430 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 1666 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1666 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1666 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1666 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1666 # number of overall hits
-system.cpu.icache.overall_hits::total 1666 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 402 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 402 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 402 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 402 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 402 # number of overall misses
-system.cpu.icache.overall_misses::total 402 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 25574000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 25574000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 25574000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 25574000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 25574000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 25574000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 2068 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 2068 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 2068 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194391 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.194391 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.194391 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.194391 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.194391 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.194391 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63616.915423 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 63616.915423 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 63616.915423 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 63616.915423 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked
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+system.cpu.dcache.demand_miss_latency::cpu.data 19667245 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 19667245 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 19667245 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 19667245 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1352 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1352 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55918.684729 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55918.684729 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 61606.512476 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 61606.512476 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 2265 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2265 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2265 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2265 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.143491 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.143491 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.216867 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.216867 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.173068 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.173068 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.173068 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.173068 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55698.427835 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55698.427835 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44756.313131 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 44756.313131 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 76250 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 76250 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 50171.543367 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 50171.543367 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 617 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 10 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 34.277778 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 90 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 158 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6245255 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 6245255 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9390005 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 9390005 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9390005 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 9390005 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59478.619048 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59478.619048 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_hits::cpu.data 248 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 248 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 248 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 40 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5492753 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 5492753 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2689000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2689000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8181753 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 8181753 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8181753 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 8181753 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076923 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076923 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.043812 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.043812 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.063576 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.063576 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52814.932692 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52814.932692 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67225 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67225 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 2694500 # Number of ticks simulated
final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 109620 # Simulator instruction rate (inst/s)
-host_op_rate 128318 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 64270947 # Simulator tick rate (ticks/s)
-host_mem_usage 268656 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
+host_inst_rate 582910 # Simulator instruction rate (inst/s)
+host_op_rate 681582 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 341032781 # Simulator tick rate (ticks/s)
+host_mem_usage 293692 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5377 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 9855260716 # Throughput (bytes/s)
-system.membus.data_through_bus 26555 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 5596 # Transaction distribution
+system.membus.trans_dist::ReadResp 5607 # Transaction distribution
+system.membus.trans_dist::WriteReq 913 # Transaction distribution
+system.membus.trans_dist::WriteResp 913 # Transaction distribution
+system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution
+system.membus.trans_dist::StoreCondReq 11 # Transaction distribution
+system.membus.trans_dist::StoreCondResp 11 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 6531 # Request fanout histogram
+system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram
+system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 4 # Request fanout histogram
+system.membus.snoop_fanout::max_value 5 # Request fanout histogram
+system.membus.snoop_fanout::total 6531 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
sim_ticks 2694500 # Number of ticks simulated
final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 133655 # Simulator instruction rate (inst/s)
-host_op_rate 156442 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 78348823 # Simulator tick rate (ticks/s)
-host_mem_usage 267596 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
+host_inst_rate 685428 # Simulator instruction rate (inst/s)
+host_op_rate 801222 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 400788339 # Simulator tick rate (ticks/s)
+host_mem_usage 292412 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5377 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 9855260716 # Throughput (bytes/s)
-system.membus.data_through_bus 26555 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 5596 # Transaction distribution
+system.membus.trans_dist::ReadResp 5607 # Transaction distribution
+system.membus.trans_dist::WriteReq 913 # Transaction distribution
+system.membus.trans_dist::WriteResp 913 # Transaction distribution
+system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution
+system.membus.trans_dist::StoreCondReq 11 # Transaction distribution
+system.membus.trans_dist::StoreCondResp 11 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 6531 # Request fanout histogram
+system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram
+system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 4 # Request fanout histogram
+system.membus.snoop_fanout::max_value 5 # Request fanout histogram
+system.membus.snoop_fanout::total 6531 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
sim_ticks 25815000 # Number of ticks simulated
final_tick 25815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 85918 # Simulator instruction rate (inst/s)
-host_op_rate 100276 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 485659481 # Simulator tick rate (ticks/s)
-host_mem_usage 277384 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 367819 # Simulator instruction rate (inst/s)
+host_op_rate 428893 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2075494452 # Simulator tick rate (ticks/s)
+host_mem_usage 302164 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 4565 # Number of instructions simulated
sim_ops 5329 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 557815224 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 309897347 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 867712570 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 867712570 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 307 # Transaction distribution
system.membus.trans_dist::ReadResp 307 # Transaction distribution
system.membus.trans_dist::ReadExReq 43 # Transaction distribution
system.membus.trans_dist::ReadExResp 43 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 22400 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 350 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 350 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 350 # Request fanout histogram
system.membus.reqLayer0.occupancy 355000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 3155000 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 947046291 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 482 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 764 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 24448 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 382 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks)
sim_ticks 24907000 # Number of ticks simulated
final_tick 24907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 84163 # Simulator instruction rate (inst/s)
-host_op_rate 84145 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 360406899 # Simulator tick rate (ticks/s)
-host_mem_usage 264444 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
+host_inst_rate 110455 # Simulator instruction rate (inst/s)
+host_op_rate 110427 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 472950648 # Simulator tick rate (ticks/s)
+host_mem_usage 286112 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bytesPerActivate::768-895 3 2.83% 95.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 5 4.72% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 106 # Bytes accessed per row activation
-system.physmem.totQLat 4873000 # Total ticks spent queuing
-system.physmem.totMemAccLat 13404250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 4936500 # Total ticks spent queuing
+system.physmem.totMemAccLat 13467750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2275000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10709.89 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 10849.45 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29459.89 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 29599.45 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1169.15 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1169.15 # Average system read bandwidth in MiByte/s
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 22841500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 1169149235 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 404 # Transaction distribution
system.membus.trans_dist::ReadResp 404 # Transaction distribution
system.membus.trans_dist::ReadExReq 51 # Transaction distribution
system.membus.trans_dist::ReadExResp 51 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 910 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 910 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 29120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 29120 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 29120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 455 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 455 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 455 # Request fanout histogram
system.membus.reqLayer0.occupancy 552000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 4259500 # Layer occupancy (ticks)
system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 9486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 9484 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 462 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 44432 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 5383 # Number of cycles cpu stages are processed.
-system.cpu.activity 10.805982 # Percentage of cycles cpu is active
+system.cpu.idleCycles 44434 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 5381 # Number of cycles cpu stages are processed.
+system.cpu.activity 10.801967 # Percentage of cycles cpu is active
system.cpu.comLoads 1163 # Number of Load instructions committed
system.cpu.comStores 925 # Number of Store instructions committed
system.cpu.comBranches 915 # Number of Branches instructions committed
system.cpu.ipc 0.116712 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.116712 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 46167 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 3648 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 7.323095 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 47002 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 2813 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 5.646894 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage0.idleCycles 46168 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 3647 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 7.321088 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 47003 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 2812 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 5.644886 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 47048 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 2767 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 5.554552 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 48577 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 1238 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 2.485195 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 46927 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 2888 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 5.797451 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 46929 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 2886 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 5.793436 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.tags.replacements 13 # number of replacements
-system.cpu.icache.tags.tagsinuse 150.585033 # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse 150.581339 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 150.585033 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.073528 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.073528 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 150.581339 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.073526 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.073526 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 306 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id
system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses
system.cpu.icache.overall_misses::total 350 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 25291750 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 25291750 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 25291750 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 25291750 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 25291750 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 25291750 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 25285250 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 25285250 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 25285250 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 25285250 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 25285250 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 25285250 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 778 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses
system.cpu.icache.demand_miss_rate::total 0.449871 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.449871 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.449871 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72262.142857 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 72262.142857 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 72262.142857 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 72262.142857 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 72262.142857 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 72262.142857 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72243.571429 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 72243.571429 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 72243.571429 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 72243.571429 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 72243.571429 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 72243.571429 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22956750 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 22956750 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22956750 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 22956750 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22956750 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 22956750 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22950250 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 22950250 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22950250 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 22950250 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22950250 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 22950250 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.410026 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.410026 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.410026 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71964.733542 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71964.733542 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71964.733542 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 71964.733542 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71964.733542 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 71964.733542 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71944.357367 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71944.357367 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71944.357367 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 71944.357367 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71944.357367 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 71944.357367 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 1174288353 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 638 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 914 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 29248 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 29248 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 29248 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 457 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
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+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
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system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 21611500 # Number of ticks simulated
final_tick 21611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 39362 # Simulator instruction rate (inst/s)
-host_op_rate 39354 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 164927772 # Simulator tick rate (ticks/s)
-host_mem_usage 235848 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
+host_inst_rate 87050 # Simulator instruction rate (inst/s)
+host_op_rate 87030 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 364707967 # Simulator tick rate (ticks/s)
+host_mem_usage 288672 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 5156 # Number of instructions simulated
sim_ops 5156 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bytesPerActivate::896-1023 2 1.83% 95.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 5 4.59% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 109 # Bytes accessed per row activation
-system.physmem.totQLat 5548500 # Total ticks spent queuing
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system.physmem.avgRdBW 1418.50 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1418.50 # Average system read bandwidth in MiByte/s
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991176 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993039 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991176 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.993776 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59344.213650 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67782.967033 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61138.434579 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67127.450980 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67127.450980 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59344.213650 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67547.535211 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61776.096033 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59344.213650 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67547.535211 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61776.096033 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59339.762611 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67760.989011 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61130.257009 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67088.235294 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67088.235294 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59339.762611 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67519.366197 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61764.613779 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59339.762611 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67519.366197 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61764.613779 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 92.430317 # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse 92.429669 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 2508 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 17.661972 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 92.430317 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data 92.429669 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.022566 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.022566 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id
system.cpu.dcache.demand_misses::total 531 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 531 # number of overall misses
system.cpu.dcache.overall_misses::total 531 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11709000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11709000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 23266249 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 23266249 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 34975249 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 34975249 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 34975249 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 34975249 # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 11707000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 11707000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 23264249 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 23264249 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 34971249 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 34971249 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 34971249 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 34971249 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 2114 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 2114 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_miss_rate::total 0.174729 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.174729 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.174729 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69284.023669 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 69284.023669 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64271.406077 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64271.406077 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 65866.758945 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 65866.758945 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 65866.758945 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 65866.758945 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69272.189349 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 69272.189349 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64265.881215 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64265.881215 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 65859.225989 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 65859.225989 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 65859.225989 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 65859.225989 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7382750 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 7382750 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4109999 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4109999 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11492749 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 11492749 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11492749 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 11492749 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7380750 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 7380750 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4107999 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4107999 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11488749 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 11488749 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11488749 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 11488749 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.043046 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.043046 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.046726 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046726 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.046726 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81129.120879 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81129.120879 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80588.215686 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80588.215686 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80934.852113 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 80934.852113 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80934.852113 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 80934.852113 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81107.142857 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81107.142857 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80549 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80549 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80906.683099 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 80906.683099 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80906.683099 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 80906.683099 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 2907000 # Number of ticks simulated
final_tick 2907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1298058 # Simulator instruction rate (inst/s)
-host_op_rate 1293725 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 644853594 # Simulator tick rate (ticks/s)
-host_mem_usage 255756 # Number of bytes of host memory used
-host_seconds 0.00 # Real time elapsed on the host
+host_inst_rate 972729 # Simulator instruction rate (inst/s)
+host_op_rate 970456 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 484177215 # Simulator tick rate (ticks/s)
+host_mem_usage 275596 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 8001375989 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2762985896 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10764361885 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 10764361885 # Throughput (bytes/s)
-system.membus.data_through_bus 31292 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 6978 # Transaction distribution
+system.membus.trans_dist::ReadResp 6978 # Transaction distribution
+system.membus.trans_dist::WriteReq 925 # Transaction distribution
+system.membus.trans_dist::WriteResp 925 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11630 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4176 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 15806 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 23260 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8032 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 31292 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 7903 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.735797 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.440936 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 2088 26.42% 26.42% # Request fanout histogram
+system.membus.snoop_fanout::1 5815 73.58% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 7903 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
sim_ticks 31633000 # Number of ticks simulated
final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 474922 # Simulator instruction rate (inst/s)
-host_op_rate 474341 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2577866515 # Simulator tick rate (ticks/s)
-host_mem_usage 263440 # Number of bytes of host memory used
+host_inst_rate 442331 # Simulator instruction rate (inst/s)
+host_op_rate 441894 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2401898254 # Simulator tick rate (ticks/s)
+host_mem_usage 285092 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bw_total::cpu.inst 608984289 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 279202099 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 888186388 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 888186388 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 388 # Transaction distribution
system.membus.trans_dist::ReadResp 388 # Transaction distribution
system.membus.trans_dist::ReadExReq 51 # Transaction distribution
system.membus.trans_dist::ReadExResp 51 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 878 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28096 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 28096 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 28096 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28096 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 28096 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 439 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 439 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 439 # Request fanout histogram
system.membus.reqLayer0.occupancy 439000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 3951000 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 892232795 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 390 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 390 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 606 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 882 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19392 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 28224 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 28224 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19392 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 28224 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 441 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 454500 # Layer occupancy (ticks)
sim_ticks 18857500 # Number of ticks simulated
final_tick 18857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 41326 # Simulator instruction rate (inst/s)
-host_op_rate 41320 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 134509153 # Simulator tick rate (ticks/s)
-host_mem_usage 232584 # Number of bytes of host memory used
-host_seconds 0.14 # Real time elapsed on the host
+host_inst_rate 98075 # Simulator instruction rate (inst/s)
+host_op_rate 98051 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 319158839 # Simulator tick rate (ticks/s)
+host_mem_usage 285824 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bytesPerActivate::896-1023 3 3.80% 86.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 11 13.92% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation
-system.physmem.totQLat 3609000 # Total ticks spent queuing
-system.physmem.totMemAccLat 11934000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 3635500 # Total ticks spent queuing
+system.physmem.totMemAccLat 11960500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 8128.38 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 8188.06 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 26878.38 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 26938.06 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1506.88 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1506.88 # Average system read bandwidth in MiByte/s
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 15315250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 1506880552 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 397 # Transaction distribution
system.membus.trans_dist::ReadResp 397 # Transaction distribution
system.membus.trans_dist::ReadExReq 47 # Transaction distribution
system.membus.trans_dist::ReadExResp 47 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 28416 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 444 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 444 # Request fanout histogram
system.membus.reqLayer0.occupancy 555500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
system.membus.respLayer1.occupancy 4160750 # Layer occupancy (ticks)
system.cpu.int_regfile_writes 7176 # number of integer regfile writes
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
-system.cpu.toL2Bus.throughput 1530637677 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 903 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 28864 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 584250 # Layer occupancy (ticks)
sim_ticks 2896000 # Number of ticks simulated
final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1148266 # Simulator instruction rate (inst/s)
-host_op_rate 1144862 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 570752858 # Simulator tick rate (ticks/s)
-host_mem_usage 250716 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
+host_inst_rate 1326844 # Simulator instruction rate (inst/s)
+host_op_rate 1322603 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 659230594 # Simulator tick rate (ticks/s)
+host_mem_usage 274036 # Number of bytes of host memory used
+host_seconds 0.00 # Real time elapsed on the host
sim_insts 5793 # Number of instructions simulated
sim_ops 5793 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 8001381215 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2737914365 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10739295580 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 10739295580 # Throughput (bytes/s)
-system.membus.data_through_bus 31101 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 6754 # Transaction distribution
+system.membus.trans_dist::ReadResp 6754 # Transaction distribution
+system.membus.trans_dist::WriteReq 1046 # Transaction distribution
+system.membus.trans_dist::WriteResp 1046 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11586 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4014 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 15600 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 23172 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 7929 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 31101 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 7800 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.742692 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.437178 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 2007 25.73% 25.73% # Request fanout histogram
+system.membus.snoop_fanout::1 5793 74.27% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 7800 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
---------- Begin Simulation Statistics ----------
sim_seconds 0.000021 # Number of seconds simulated
-sim_ticks 20918500 # Number of ticks simulated
-final_tick 20918500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 20927500 # Number of ticks simulated
+final_tick 20927500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 69876 # Simulator instruction rate (inst/s)
-host_op_rate 69862 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 274294219 # Simulator tick rate (ticks/s)
-host_mem_usage 270808 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 84066 # Simulator instruction rate (inst/s)
+host_op_rate 84047 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 330123200 # Simulator tick rate (ticks/s)
+host_mem_usage 286520 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
system.physmem.num_reads::total 423 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 884193417 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 409972034 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1294165452 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 884193417 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 884193417 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 884193417 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 409972034 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1294165452 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 883813164 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 409795723 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1293608888 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 883813164 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 883813164 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 883813164 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 409795723 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1293608888 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 423 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 423 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 20849000 # Total gap between requests
+system.physmem.totGap 20858000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.bytesPerActivate::640-767 4 5.41% 93.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 5 6.76% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 74 # Bytes accessed per row activation
-system.physmem.totQLat 3773250 # Total ticks spent queuing
-system.physmem.totMemAccLat 11704500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 3885750 # Total ticks spent queuing
+system.physmem.totMemAccLat 11817000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2115000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 8920.21 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 9186.17 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 27670.21 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1294.17 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 27936.17 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1293.61 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1294.17 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1293.61 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 10.11 # Data bus utilization in percentage
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.14 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 49288.42 # Average gap between requests
+system.physmem.avgGap 49309.69 # Average gap between requests
system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 13500 # Time in different power states
system.physmem.memoryStateTime::REF 520000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 15312750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 1294165452 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 342 # Transaction distribution
system.membus.trans_dist::ReadResp 342 # Transaction distribution
system.membus.trans_dist::ReadExReq 81 # Transaction distribution
system.membus.trans_dist::ReadExResp 81 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 846 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 846 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27072 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 27072 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27072 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 423 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 423 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 423 # Request fanout histogram
system.membus.reqLayer0.occupancy 501500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 3931250 # Layer occupancy (ticks)
system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 41838 # number of cpu cycles simulated
+system.cpu.numCycles 41856 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True).
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 9657 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 9651 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 422 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 35590 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 6248 # Number of cycles cpu stages are processed.
-system.cpu.activity 14.933792 # Percentage of cycles cpu is active
+system.cpu.timesIdled 424 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 35611 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 6245 # Number of cycles cpu stages are processed.
+system.cpu.activity 14.920203 # Percentage of cycles cpu is active
system.cpu.comLoads 715 # Number of Load instructions committed
system.cpu.comStores 673 # Number of Store instructions committed
system.cpu.comBranches 1115 # Number of Branches instructions committed
system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total)
-system.cpu.cpi 7.853952 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 7.857331 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 7.853952 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.127324 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 7.857331 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.127270 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 0.127324 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 37198 # Number of cycles 0 instructions are processed.
+system.cpu.ipc_total 0.127270 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 37216 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 11.090396 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 38644 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 3194 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 7.634208 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 38804 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 3034 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 7.251781 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 40862 # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles 976 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 2.332807 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 38681 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.utilization 11.085627 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 38661 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 7.633314 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 38823 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 7.246273 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 40881 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization 2.329415 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 38699 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 7.545772 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.utilization 7.542527 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 142.676310 # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse 142.708262 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 142.676310 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.069666 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.069666 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 142.708262 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.069682 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.069682 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id
system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses
system.cpu.icache.overall_misses::total 366 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 25425250 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 25425250 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 25425250 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 25425250 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 25425250 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 25425250 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 25412000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 25412000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 25412000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 25412000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses
system.cpu.dcache.overall_misses::total 474 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 4579750 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 4579750 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 28882250 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 28882250 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 33462000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 33462000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 33462000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 33462000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 4588750 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 4588750 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 28972250 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 28972250 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 33561000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 33561000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 33561000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 33561000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75077.868852 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 75077.868852 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69932.808717 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69932.808717 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 70594.936709 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 70594.936709 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 70594.936709 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 70594.936709 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75225.409836 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 75225.409836 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70150.726392 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 70150.726392 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 70803.797468 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 70803.797468 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4082500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4082500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6083000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 6083000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10165500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10165500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10165500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10165500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4091500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4091500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6091750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 6091750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10183250 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10183250 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10183250 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10183250 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75601.851852 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75601.851852 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75098.765432 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75098.765432 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75300 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 75300 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75300 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 75300 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75768.518519 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75768.518519 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75206.790123 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75206.790123 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 2694500 # Number of ticks simulated
final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1015247 # Simulator instruction rate (inst/s)
-host_op_rate 1012545 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 510902541 # Simulator tick rate (ticks/s)
-host_mem_usage 261064 # Number of bytes of host memory used
+host_inst_rate 399685 # Simulator instruction rate (inst/s)
+host_op_rate 399265 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 201759641 # Simulator tick rate (ticks/s)
+host_mem_usage 276260 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bw_total::cpu.inst 7971794396 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3587678605 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11559473001 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 11559473001 # Throughput (bytes/s)
-system.membus.data_through_bus 31147 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 6085 # Transaction distribution
+system.membus.trans_dist::ReadResp 6085 # Transaction distribution
+system.membus.trans_dist::WriteReq 673 # Transaction distribution
+system.membus.trans_dist::WriteResp 673 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 10740 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 2776 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 13516 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 21480 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 9667 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 31147 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 6758 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.794614 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.404013 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 1388 20.54% 20.54% # Request fanout histogram
+system.membus.snoop_fanout::1 5370 79.46% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 6758 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 5390 # number of cpu cycles simulated
sim_ticks 27800000 # Number of ticks simulated
final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 487107 # Simulator instruction rate (inst/s)
-host_op_rate 486440 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2535570960 # Simulator tick rate (ticks/s)
-host_mem_usage 269788 # Number of bytes of host memory used
+host_inst_rate 583909 # Simulator instruction rate (inst/s)
+host_op_rate 583078 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3038583452 # Simulator tick rate (ticks/s)
+host_mem_usage 285748 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bw_total::cpu.inst 587050360 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 308489209 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 895539568 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 895539568 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 308 # Transaction distribution
system.membus.trans_dist::ReadResp 308 # Transaction distribution
system.membus.trans_dist::ReadExReq 81 # Transaction distribution
system.membus.trans_dist::ReadExResp 81 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 24896 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 389 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 389 # Request fanout histogram
system.membus.reqLayer0.occupancy 389000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 3501000 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 902446043 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 311 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16448 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 25088 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16448 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 392 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 392 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks)
---------- Begin Simulation Statistics ----------
sim_seconds 0.000020 # Number of seconds simulated
-sim_ticks 19744000 # Number of ticks simulated
-final_tick 19744000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 19678000 # Number of ticks simulated
+final_tick 19678000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 27433 # Simulator instruction rate (inst/s)
-host_op_rate 49695 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 100653274 # Simulator tick rate (ticks/s)
-host_mem_usage 249652 # Number of bytes of host memory used
-host_seconds 0.20 # Real time elapsed on the host
+host_inst_rate 48979 # Simulator instruction rate (inst/s)
+host_op_rate 88725 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 179100946 # Simulator tick rate (ticks/s)
+host_mem_usage 305852 # Number of bytes of host memory used
+host_seconds 0.11 # Real time elapsed on the host
sim_insts 5380 # Number of instructions simulated
sim_ops 9747 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 891410049 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 457050243 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1348460292 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 891410049 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 891410049 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 891410049 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 457050243 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1348460292 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 894399837 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 458583189 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1352983027 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 894399837 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 894399837 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 894399837 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 458583189 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1352983027 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 417 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 19695500 # Total gap between requests
+system.physmem.totGap 19629500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 128 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 98 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 242.285714 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 159.132678 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 257.193096 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 35 35.71% 35.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 32 32.65% 68.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 12 12.24% 80.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 158.475642 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 257.521253 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 36 36.73% 36.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 30 30.61% 67.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 13 13.27% 80.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 6 6.12% 86.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 6 6.12% 92.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 4 4.08% 96.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 3 3.06% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 98 # Bytes accessed per row activation
-system.physmem.totQLat 4076000 # Total ticks spent queuing
-system.physmem.totMemAccLat 11894750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 4347000 # Total ticks spent queuing
+system.physmem.totMemAccLat 12165750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 9774.58 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 10424.46 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 28524.58 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1351.70 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 29174.46 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1356.24 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1351.70 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1356.24 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 10.56 # Data bus utilization in percentage
-system.physmem.busUtilRead 10.56 # Data bus utilization in percentage for reads
+system.physmem.busUtil 10.60 # Data bus utilization in percentage
+system.physmem.busUtilRead 10.60 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 309 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 74.10 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 47231.41 # Average gap between requests
+system.physmem.avgGap 47073.14 # Average gap between requests
system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
system.physmem.memoryStateTime::REF 520000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 15315250 # Time in different power states
+system.physmem.memoryStateTime::ACT 15318250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 1348460292 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 339 # Transaction distribution
system.membus.trans_dist::ReadResp 338 # Transaction distribution
system.membus.trans_dist::ReadExReq 78 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 26624 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 417 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 417 # Request fanout histogram
system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.6 # Layer utilization (%)
system.membus.respLayer1.occupancy 3897000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 19.7 # Layer utilization (%)
+system.membus.respLayer1.utilization 19.8 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 3423 # Number of BP lookups
system.cpu.branchPred.condPredicted 3423 # Number of conditional branches predicted
system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions.
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 39489 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 10915 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 21893 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.086682 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.393223 # Number of inst fetches per cycle
+system.cpu.fetch.branchRate 0.086973 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.394542 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 10660 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 6840 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 3336 # Number of cycles decode is running
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 17897 # Type of FU issued
-system.cpu.iq.rate 0.453215 # Inst issue rate
+system.cpu.iq.rate 0.454735 # Inst issue rate
system.cpu.iq.fu_busy_cnt 224 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.012516 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 57983 # Number of integer instruction queue reads
system.cpu.iew.exec_refs 3251 # number of memory reference insts executed
system.cpu.iew.exec_branches 1662 # Number of branches executed
system.cpu.iew.exec_stores 1282 # Number of stores executed
-system.cpu.iew.exec_rate 0.428626 # Inst execution rate
+system.cpu.iew.exec_rate 0.430063 # Inst execution rate
system.cpu.iew.wb_sent 16636 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 16374 # cumulative count of insts written-back
system.cpu.iew.wb_producers 11006 # num instructions producing a value
system.cpu.iew.wb_consumers 17135 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.414647 # insts written-back per cycle
+system.cpu.iew.wb_rate 0.416038 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.642311 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 11720 # The number of squashed insts skipped by commit
system.cpu.rob.rob_reads 41132 # The number of ROB reads
system.cpu.rob.rob_writes 44928 # The number of ROB writes
system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 17596 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 17464 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5380 # Number of Instructions Simulated
system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 7.339963 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.339963 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.136240 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.136240 # IPC: Total IPC of All Threads
+system.cpu.cpi 7.315428 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.315428 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.136697 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.136697 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 21340 # number of integer regfile reads
system.cpu.int_regfile_writes 13120 # number of integer regfile writes
system.cpu.fp_regfile_reads 4 # number of floating regfile reads
system.cpu.cc_regfile_writes 5036 # number of cc regfile writes
system.cpu.misc_regfile_reads 7491 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 1351701783 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 78 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 552 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 283 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes)
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-system.cpu.toL2Bus.tot_pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 26688 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
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+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
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+system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 462750 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 234250 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 462500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 131.753616 # Cycle average of tags in use
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system.cpu.icache.tags.total_refs 1800 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 276 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 6.521739 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_task_id_blocks::1024 276 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id
system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses
system.cpu.icache.overall_misses::total 368 # number of overall misses
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system.cpu.icache.ReadReq_accesses::cpu.inst 2168 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2168 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2168 # number of demand (read+write) accesses
system.cpu.icache.demand_miss_rate::total 0.169742 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.169742 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.169742 # miss rate for overall accesses
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::total 276 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.127306 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.127306 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.127306 # mshr miss rate for overall accesses
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
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system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 338 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.002959 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id
system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses
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system.cpu.l2cache.ReadReq_accesses::cpu.inst 276 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 340 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996377 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71275.454545 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77289.062500 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72410.766962 # average ReadReq miss latency
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-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70625 # average ReadExReq miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73628.521127 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72076.738609 # average overall miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73628.521127 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72076.738609 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4156000 # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4539250 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16144250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8695250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 24839500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16144250 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8695250 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 24839500 # number of overall MSHR miss cycles
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4539500 # number of ReadExReq MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8695500 # number of overall MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997059 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58706.363636 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64937.500000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59882.743363 # average ReadReq mshr miss latency
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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58195.512821 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58706.363636 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61234.154930 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59567.146283 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58706.363636 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61234.154930 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59567.146283 # average overall mshr miss latency
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+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59334.545455 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59334.545455 # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 82.450988 # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse 82.331185 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 17.021277 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 82.450988 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.020130 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.020130 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 82.331185 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.020100 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.020100 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id
system.cpu.dcache.overall_misses::total 214 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9815500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 9815500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 5769250 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 5769250 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 15584750 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 15584750 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 15584750 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 15584750 # number of overall miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 5771000 # number of WriteReq miss cycles
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+system.cpu.dcache.overall_miss_latency::total 15586500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1679 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1679 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.overall_miss_rate::total 0.081867 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72172.794118 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 72172.794118 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73964.743590 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 73964.743590 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 72825.934579 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 72825.934579 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 72825.934579 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 72825.934579 # average overall miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73987.179487 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 73987.179487 # average WriteReq miss latency
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+system.cpu.dcache.demand_avg_miss_latency::total 72834.112150 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72834.112150 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5009500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5009500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5586750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 5586750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10596250 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10596250 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10596250 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10596250 # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5588000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5588000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10597500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10597500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10597500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038118 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038118 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.054323 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78273.437500 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78273.437500 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71625 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71625 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74621.478873 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 74621.478873 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74621.478873 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 74621.478873 # average overall mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71641.025641 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71641.025641 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 5615000 # Number of ticks simulated
final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 478524 # Simulator instruction rate (inst/s)
-host_op_rate 865796 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 498092788 # Simulator tick rate (ticks/s)
-host_mem_usage 271572 # Number of bytes of host memory used
+host_inst_rate 365210 # Simulator instruction rate (inst/s)
+host_op_rate 661016 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 380445830 # Simulator tick rate (ticks/s)
+host_mem_usage 292780 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9748 # Number of ops (including micro ops) simulated
system.physmem.bw_total::cpu.inst 9779519145 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2525022262 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12304541407 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 12304541407 # Throughput (bytes/s)
-system.membus.data_through_bus 69090 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 7917 # Transaction distribution
+system.membus.trans_dist::ReadResp 7917 # Transaction distribution
+system.membus.trans_dist::WriteReq 935 # Transaction distribution
+system.membus.trans_dist::WriteResp 935 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13728 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::total 13728 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3976 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::total 3976 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 17704 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 54912 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::total 54912 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 14178 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::total 14178 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 69090 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 8852 # Request fanout histogram
+system.membus.snoop_fanout::mean 2.775418 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.417330 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::2 1988 22.46% 22.46% # Request fanout histogram
+system.membus.snoop_fanout::3 6864 77.54% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 2 # Request fanout histogram
+system.membus.snoop_fanout::max_value 3 # Request fanout histogram
+system.membus.snoop_fanout::total 8852 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 11 # Number of system calls
sim_ticks 28358000 # Number of ticks simulated
final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 260669 # Simulator instruction rate (inst/s)
-host_op_rate 471875 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1371807276 # Simulator tick rate (ticks/s)
-host_mem_usage 281320 # Number of bytes of host memory used
+host_inst_rate 307468 # Simulator instruction rate (inst/s)
+host_op_rate 556583 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1618053178 # Simulator tick rate (ticks/s)
+host_mem_usage 302528 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9748 # Number of ops (including micro ops) simulated
system.physmem.bw_total::cpu.inst 512306933 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 302419070 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 814726003 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 814726003 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 282 # Transaction distribution
system.membus.trans_dist::ReadResp 282 # Transaction distribution
system.membus.trans_dist::ReadExReq 79 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 23104 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 361 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 361 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 361 # Request fanout histogram
system.membus.reqLayer0.occupancy 361000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
system.membus.respLayer1.occupancy 3249000 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 816982862 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 283 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8576 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 23168 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8576 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 362 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks)
---------- Begin Simulation Statistics ----------
sim_seconds 0.000023 # Number of seconds simulated
-sim_ticks 23170000 # Number of ticks simulated
-final_tick 23170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 23061500 # Number of ticks simulated
+final_tick 23061500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 44420 # Simulator instruction rate (inst/s)
-host_op_rate 44416 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 80747825 # Simulator tick rate (ticks/s)
-host_mem_usage 237048 # Number of bytes of host memory used
-host_seconds 0.29 # Real time elapsed on the host
+host_inst_rate 90290 # Simulator instruction rate (inst/s)
+host_op_rate 90281 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 163358622 # Simulator tick rate (ticks/s)
+host_mem_usage 290460 # Number of bytes of host memory used
+host_seconds 0.14 # Real time elapsed on the host
sim_insts 12744 # Number of instructions simulated
sim_ops 12744 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 40384 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 22272 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 40576 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 22080 # Number of bytes read from this memory
system.physmem.bytes_read::total 62656 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 40384 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 40384 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 631 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 348 # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::cpu.inst 40576 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 40576 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 634 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 345 # Number of read requests responded to by this memory
system.physmem.num_reads::total 979 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1742943461 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 961242987 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2704186448 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1742943461 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1742943461 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1742943461 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 961242987 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2704186448 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1759469245 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 957439889 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2716909134 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1759469245 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1759469245 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1759469245 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 957439889 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2716909134 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 979 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 979 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.perBankRdBursts::1 151 # Per bank write bursts
system.physmem.perBankRdBursts::2 78 # Per bank write bursts
system.physmem.perBankRdBursts::3 58 # Per bank write bursts
-system.physmem.perBankRdBursts::4 88 # Per bank write bursts
-system.physmem.perBankRdBursts::5 48 # Per bank write bursts
+system.physmem.perBankRdBursts::4 89 # Per bank write bursts
+system.physmem.perBankRdBursts::5 50 # Per bank write bursts
system.physmem.perBankRdBursts::6 33 # Per bank write bursts
system.physmem.perBankRdBursts::7 51 # Per bank write bursts
system.physmem.perBankRdBursts::8 42 # Per bank write bursts
system.physmem.perBankRdBursts::9 39 # Per bank write bursts
-system.physmem.perBankRdBursts::10 31 # Per bank write bursts
+system.physmem.perBankRdBursts::10 29 # Per bank write bursts
system.physmem.perBankRdBursts::11 34 # Per bank write bursts
system.physmem.perBankRdBursts::12 15 # Per bank write bursts
system.physmem.perBankRdBursts::13 120 # Per bank write bursts
-system.physmem.perBankRdBursts::14 70 # Per bank write bursts
+system.physmem.perBankRdBursts::14 69 # Per bank write bursts
system.physmem.perBankRdBursts::15 37 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 23015000 # Total gap between requests
+system.physmem.totGap 22909000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 351 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 324 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 193 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 75 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 24 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 332 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 191 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 77 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 27 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 196 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 289.959184 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 186.164854 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 288.512504 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 61 31.12% 31.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 60 30.61% 61.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 290.285714 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 185.772581 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 289.019279 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 62 31.63% 31.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 59 30.10% 61.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 22 11.22% 72.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 9 4.59% 77.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 16 8.16% 85.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 6 3.06% 88.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 5 2.55% 91.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 8 4.08% 77.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 15 7.65% 84.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 9 4.59% 89.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 4 2.04% 91.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 4 2.04% 93.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 13 6.63% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 196 # Bytes accessed per row activation
-system.physmem.totQLat 11386250 # Total ticks spent queuing
-system.physmem.totMemAccLat 29742500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 11811000 # Total ticks spent queuing
+system.physmem.totMemAccLat 30167250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 4895000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11630.49 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 12064.35 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30380.49 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 2704.19 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 30814.35 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2716.91 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 2704.19 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2716.91 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 21.13 # Data bus utilization in percentage
-system.physmem.busUtilRead 21.13 # Data bus utilization in percentage for reads
+system.physmem.busUtil 21.23 # Data bus utilization in percentage
+system.physmem.busUtilRead 21.23 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 2.40 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 2.42 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 767 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 78.35 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 23508.68 # Average gap between requests
+system.physmem.avgGap 23400.41 # Average gap between requests
system.physmem.pageHitRate 78.35 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 25750 # Time in different power states
system.physmem.memoryStateTime::REF 520000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 15300500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 2704186448 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 833 # Transaction distribution
system.membus.trans_dist::ReadResp 833 # Transaction distribution
system.membus.trans_dist::ReadExReq 146 # Transaction distribution
system.membus.trans_dist::ReadExResp 146 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1958 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1958 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62656 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 62656 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 62656 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1208500 # Layer occupancy (ticks)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62656 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 62656 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 979 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 979 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 979 # Request fanout histogram
+system.membus.reqLayer0.occupancy 1210000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 5.2 # Layer utilization (%)
-system.membus.respLayer1.occupancy 9081250 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 39.2 # Layer utilization (%)
+system.membus.respLayer1.occupancy 9085500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 39.4 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 7166 # Number of BP lookups
-system.cpu.branchPred.condPredicted 4000 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1467 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 5305 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 908 # Number of BTB hits
+system.cpu.branchPred.lookups 6891 # Number of BP lookups
+system.cpu.branchPred.condPredicted 3900 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1379 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 5156 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 960 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 17.115928 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 981 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 18.619085 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 963 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 72 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 4855 # DTB read hits
-system.cpu.dtb.read_misses 98 # DTB read misses
+system.cpu.dtb.read_hits 4694 # DTB read hits
+system.cpu.dtb.read_misses 106 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 4953 # DTB read accesses
-system.cpu.dtb.write_hits 2092 # DTB write hits
+system.cpu.dtb.read_accesses 4800 # DTB read accesses
+system.cpu.dtb.write_hits 2103 # DTB write hits
system.cpu.dtb.write_misses 62 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 2154 # DTB write accesses
-system.cpu.dtb.data_hits 6947 # DTB hits
-system.cpu.dtb.data_misses 160 # DTB misses
+system.cpu.dtb.write_accesses 2165 # DTB write accesses
+system.cpu.dtb.data_hits 6797 # DTB hits
+system.cpu.dtb.data_misses 168 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 7107 # DTB accesses
-system.cpu.itb.fetch_hits 5289 # ITB hits
+system.cpu.dtb.data_accesses 6965 # DTB accesses
+system.cpu.itb.fetch_hits 5123 # ITB hits
system.cpu.itb.fetch_misses 59 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 5348 # ITB accesses
+system.cpu.itb.fetch_accesses 5182 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload0.num_syscalls 17 # Number of system calls
system.cpu.workload1.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 46341 # number of cpu cycles simulated
+system.cpu.numCycles 46124 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 1308 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 39806 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 7166 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1889 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 11048 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1548 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 233 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines 5289 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 806 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 28474 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.397977 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.796585 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 1227 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 38336 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 6891 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1923 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 10750 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1460 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 320 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines 5123 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 789 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 27999 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.369192 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.769631 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 21786 76.51% 76.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 553 1.94% 78.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 412 1.45% 79.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 526 1.85% 81.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 512 1.80% 83.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 421 1.48% 85.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 497 1.75% 86.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 420 1.48% 88.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 3347 11.75% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 21530 76.90% 76.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 534 1.91% 78.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 415 1.48% 80.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 507 1.81% 82.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 495 1.77% 83.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 425 1.52% 85.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 487 1.74% 87.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 424 1.51% 88.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 3182 11.36% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 28474 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.154636 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.858980 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 37975 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 11845 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 5079 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 648 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1147 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 634 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 427 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 32375 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 893 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1147 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 38612 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 4919 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 1229 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 5110 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5677 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 30348 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 40 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 343 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 655 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 4509 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 22899 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 37890 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 37872 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 27999 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.149402 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.831151 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 37351 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 11762 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 4916 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 633 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1095 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 569 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 385 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 31322 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 859 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1095 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 37970 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 4830 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 1235 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 4957 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 5670 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 29386 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 35 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 318 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 603 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 4545 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 22134 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 36672 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 36654 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 13759 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 60 # count of serializing insts renamed
+system.cpu.rename.UndoneMaps 12994 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 62 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 2110 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2877 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1488 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 42 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores.
-system.cpu.memDep1.insertedLoads 2903 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep1.insertedStores 1354 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep1.conflictingLoads 6 # Number of conflicting loads.
+system.cpu.rename.skidInsts 2157 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2815 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1467 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 39 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 26 # Number of conflicting stores.
+system.cpu.memDep1.insertedLoads 2781 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep1.insertedStores 1339 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep1.conflictingLoads 5 # Number of conflicting loads.
system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 27058 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 26455 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 22518 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 66 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 13496 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 7946 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 22074 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 12913 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 7569 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 28474 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.790827 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.507053 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 27999 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.788385 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.505249 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 20065 70.47% 70.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 2633 9.25% 79.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 1896 6.66% 86.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 1407 4.94% 91.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 1291 4.53% 95.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 643 2.26% 98.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 327 1.15% 99.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 165 0.58% 99.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 47 0.17% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 19729 70.46% 70.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 2607 9.31% 79.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 1874 6.69% 86.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 1399 5.00% 91.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 1239 4.43% 95.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 603 2.15% 98.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 335 1.20% 99.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 163 0.58% 99.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 50 0.18% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 28474 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 27999 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 21 6.95% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 199 65.89% 72.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 82 27.15% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 17 5.72% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 196 65.99% 71.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 84 28.28% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 7409 65.93% 65.95% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.95% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.95% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.97% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2656 23.63% 89.61% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1168 10.39% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 7289 65.97% 65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2595 23.49% 89.50% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1160 10.50% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 11238 # Type of FU issued
+system.cpu.iq.FU_type_0::total 11049 # Type of FU issued
system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_1::IntAlu 7461 66.14% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.19% # Type of FU issued
-system.cpu.iq.FU_type_1::MemRead 2675 23.71% 89.90% # Type of FU issued
-system.cpu.iq.FU_type_1::MemWrite 1139 10.10% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_1::IntAlu 7322 66.41% 66.43% # Type of FU issued
+system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_1::MemRead 2566 23.27% 89.73% # Type of FU issued
+system.cpu.iq.FU_type_1::MemWrite 1132 10.27% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_1::total 11280 # Type of FU issued
-system.cpu.iq.FU_type::total 22518 0.00% 0.00% # Type of FU issued
-system.cpu.iq.rate 0.485920 # Inst issue rate
-system.cpu.iq.fu_busy_cnt::0 151 # FU busy when requested
-system.cpu.iq.fu_busy_cnt::1 151 # FU busy when requested
-system.cpu.iq.fu_busy_cnt::total 302 # FU busy when requested
-system.cpu.iq.fu_busy_rate::0 0.006706 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::1 0.006706 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::total 0.013411 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 73836 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 40624 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 19843 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_1::total 11025 # Type of FU issued
+system.cpu.iq.FU_type::total 22074 0.00% 0.00% # Type of FU issued
+system.cpu.iq.rate 0.478579 # Inst issue rate
+system.cpu.iq.fu_busy_cnt::0 149 # FU busy when requested
+system.cpu.iq.fu_busy_cnt::1 148 # FU busy when requested
+system.cpu.iq.fu_busy_cnt::total 297 # FU busy when requested
+system.cpu.iq.fu_busy_rate::0 0.006750 # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::1 0.006705 # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::total 0.013455 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 72475 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 39437 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 19551 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 22794 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 22345 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 70 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1694 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1632 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 623 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 602 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 321 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread1.forwLoads 81 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.cacheBlocked 311 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.forwLoads 78 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread1.squashedLoads 1720 # Number of loads squashed
-system.cpu.iew.lsq.thread1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread1.memOrderViolation 21 # Number of memory ordering violations
-system.cpu.iew.lsq.thread1.squashedStores 489 # Number of stores squashed
+system.cpu.iew.lsq.thread1.squashedLoads 1598 # Number of loads squashed
+system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread1.memOrderViolation 20 # Number of memory ordering violations
+system.cpu.iew.lsq.thread1.squashedStores 474 # Number of stores squashed
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread1.cacheBlocked 265 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.cacheBlocked 263 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1147 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 2751 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 416 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 27257 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 298 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 5780 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 2842 # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles 1095 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 2708 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 391 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 26654 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 299 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 5596 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 2806 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 53 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 25 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 391 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 39 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 140 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1160 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1300 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 21263 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts::0 2485 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::1 2477 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::total 4962 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1255 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewIQFullEvents 29 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 359 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 38 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 141 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1078 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1219 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 20887 # Number of executed instructions
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+system.cpu.iew.iewExecLoadInsts::1 2389 # Number of load instructions executed
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+system.cpu.iew.iewExecSquashedInsts 1187 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
system.cpu.iew.exec_nop::0 73 # number of nop insts executed
system.cpu.iew.exec_nop::1 73 # number of nop insts executed
system.cpu.iew.exec_nop::total 146 # number of nop insts executed
-system.cpu.iew.exec_refs::0 3579 # number of memory reference insts executed
-system.cpu.iew.exec_refs::1 3558 # number of memory reference insts executed
-system.cpu.iew.exec_refs::total 7137 # number of memory reference insts executed
-system.cpu.iew.exec_branches::0 1685 # Number of branches executed
-system.cpu.iew.exec_branches::1 1728 # Number of branches executed
-system.cpu.iew.exec_branches::total 3413 # Number of branches executed
-system.cpu.iew.exec_stores::0 1094 # Number of stores executed
+system.cpu.iew.exec_refs::0 3521 # number of memory reference insts executed
+system.cpu.iew.exec_refs::1 3470 # number of memory reference insts executed
+system.cpu.iew.exec_refs::total 6991 # number of memory reference insts executed
+system.cpu.iew.exec_branches::0 1644 # Number of branches executed
+system.cpu.iew.exec_branches::1 1667 # Number of branches executed
+system.cpu.iew.exec_branches::total 3311 # Number of branches executed
+system.cpu.iew.exec_stores::0 1101 # Number of stores executed
system.cpu.iew.exec_stores::1 1081 # Number of stores executed
-system.cpu.iew.exec_stores::total 2175 # Number of stores executed
-system.cpu.iew.exec_rate 0.458838 # Inst execution rate
-system.cpu.iew.wb_sent::0 10071 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::1 10174 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::total 20245 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count::0 9887 # cumulative count of insts written-back
-system.cpu.iew.wb_count::1 9976 # cumulative count of insts written-back
-system.cpu.iew.wb_count::total 19863 # cumulative count of insts written-back
-system.cpu.iew.wb_producers::0 5227 # num instructions producing a value
-system.cpu.iew.wb_producers::1 5224 # num instructions producing a value
-system.cpu.iew.wb_producers::total 10451 # num instructions producing a value
-system.cpu.iew.wb_consumers::0 6995 # num instructions consuming a value
-system.cpu.iew.wb_consumers::1 6944 # num instructions consuming a value
-system.cpu.iew.wb_consumers::total 13939 # num instructions consuming a value
+system.cpu.iew.exec_stores::total 2182 # Number of stores executed
+system.cpu.iew.exec_rate 0.452845 # Inst execution rate
+system.cpu.iew.wb_sent::0 9956 # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::1 9970 # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::total 19926 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count::0 9780 # cumulative count of insts written-back
+system.cpu.iew.wb_count::1 9791 # cumulative count of insts written-back
+system.cpu.iew.wb_count::total 19571 # cumulative count of insts written-back
+system.cpu.iew.wb_producers::0 5173 # num instructions producing a value
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+system.cpu.iew.wb_consumers::0 6916 # num instructions consuming a value
+system.cpu.iew.wb_consumers::1 6837 # num instructions consuming a value
+system.cpu.iew.wb_consumers::total 13753 # num instructions consuming a value
system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate::0 0.213353 # insts written-back per cycle
-system.cpu.iew.wb_rate::1 0.215274 # insts written-back per cycle
-system.cpu.iew.wb_rate::total 0.428627 # insts written-back per cycle
-system.cpu.iew.wb_fanout::0 0.747248 # average fanout of values written-back
-system.cpu.iew.wb_fanout::1 0.752304 # average fanout of values written-back
-system.cpu.iew.wb_fanout::total 0.749767 # average fanout of values written-back
+system.cpu.iew.wb_rate::0 0.212037 # insts written-back per cycle
+system.cpu.iew.wb_rate::1 0.212276 # insts written-back per cycle
+system.cpu.iew.wb_rate::total 0.424313 # insts written-back per cycle
+system.cpu.iew.wb_fanout::0 0.747976 # average fanout of values written-back
+system.cpu.iew.wb_fanout::1 0.753254 # average fanout of values written-back
+system.cpu.iew.wb_fanout::total 0.750600 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 14469 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 13856 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1066 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 28402 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.449898 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.318202 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1015 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 27930 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.457501 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.335540 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 23341 82.18% 82.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 2401 8.45% 90.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 1094 3.85% 94.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 390 1.37% 95.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 322 1.13% 96.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 184 0.65% 97.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 208 0.73% 98.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 133 0.47% 98.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 329 1.16% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 22902 82.00% 82.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 2402 8.60% 90.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 1059 3.79% 94.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 373 1.34% 95.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 324 1.16% 96.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 194 0.69% 97.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 197 0.71% 98.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 141 0.50% 98.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 338 1.21% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 28402 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 27930 # Number of insts commited each cycle
system.cpu.commit.committedInsts::0 6389 # Number of instructions committed
system.cpu.commit.committedInsts::1 6389 # Number of instructions committed
system.cpu.commit.committedInsts::total 12778 # Number of instructions committed
system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_1::total 6389 # Class of committed instruction
system.cpu.commit.op_class::total 12778 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.bw_lim_events 329 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 338 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits
system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits
system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 131970 # The number of ROB reads
-system.cpu.rob.rob_writes 57167 # The number of ROB writes
-system.cpu.timesIdled 413 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 17867 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 129256 # The number of ROB reads
+system.cpu.rob.rob_writes 55848 # The number of ROB writes
+system.cpu.timesIdled 409 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 18125 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts::0 6372 # Number of Instructions Simulated
system.cpu.committedInsts::1 6372 # Number of Instructions Simulated
system.cpu.committedInsts::total 12744 # Number of Instructions Simulated
system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated
system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated
system.cpu.committedOps::total 12744 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi::0 7.272599 # CPI: Cycles Per Instruction
-system.cpu.cpi::1 7.272599 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.636299 # CPI: Total CPI of All Threads
-system.cpu.ipc::0 0.137502 # IPC: Instructions Per Cycle
-system.cpu.ipc::1 0.137502 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.275005 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 26712 # number of integer regfile reads
-system.cpu.int_regfile_writes 15170 # number of integer regfile writes
+system.cpu.cpi::0 7.238544 # CPI: Cycles Per Instruction
+system.cpu.cpi::1 7.238544 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.619272 # CPI: Total CPI of All Threads
+system.cpu.ipc::0 0.138149 # IPC: Instructions Per Cycle
+system.cpu.ipc::1 0.138149 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.276299 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 26323 # number of integer regfile reads
+system.cpu.int_regfile_writes 14897 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
system.cpu.misc_regfile_writes 2 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 2709710833 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 835 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 835 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1266 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 696 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1272 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 690 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1962 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40512 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22272 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 62784 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 62784 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22080 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 62784 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 981 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 981 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 981 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 490500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1042000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1047000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 4.5 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 550750 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 547500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.4 # Layer utilization (%)
system.cpu.icache.tags.replacements::0 7 # number of replacements
system.cpu.icache.tags.replacements::1 0 # number of replacements
system.cpu.icache.tags.replacements::total 7 # number of replacements
-system.cpu.icache.tags.tagsinuse 316.397057 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 4348 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 633 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 6.868878 # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 316.469432 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 4175 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 636 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 6.564465 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 316.397057 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.154491 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.154491 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 626 # Occupied blocks per task id
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-system.cpu.icache.tags.occ_task_id_percent::1024 0.305664 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 11201 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 11201 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 4348 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 4348 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 4348 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 4348 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 4348 # number of overall hits
-system.cpu.icache.overall_hits::total 4348 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 936 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 936 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 936 # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::total 936 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 64563991 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 64563991 # number of ReadReq miss cycles
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-system.cpu.icache.overall_miss_latency::total 64563991 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 5284 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 5284 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total 5284 # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total 5284 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.177139 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.177139 # miss rate for ReadReq accesses
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-system.cpu.icache.demand_miss_rate::total 0.177139 # miss rate for demand accesses
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-system.cpu.icache.overall_miss_rate::total 0.177139 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68978.622863 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 68978.622863 # average ReadReq miss latency
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-system.cpu.icache.demand_avg_miss_latency::total 68978.622863 # average overall miss latency
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-system.cpu.icache.overall_avg_miss_latency::total 68978.622863 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 3153 # number of cycles access was blocked
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+system.cpu.icache.tags.occ_task_id_percent::1024 0.307129 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 10870 # Number of tag accesses
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+system.cpu.icache.ReadReq_accesses::cpu.inst 5117 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 303 # number of ReadReq MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses::total 633 # number of ReadReq MSHR misses
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-system.cpu.icache.overall_mshr_misses::total 633 # number of overall MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::total 46517493 # number of ReadReq MSHR miss cycles
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73487.350711 # average ReadReq mshr miss latency
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-system.cpu.icache.demand_avg_mshr_miss_latency::total 73487.350711 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73487.350711 # average overall mshr miss latency
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+system.cpu.icache.demand_avg_mshr_miss_latency::total 73226.012579 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73226.012579 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 73226.012579 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements::0 0 # number of replacements
system.cpu.l2cache.tags.replacements::1 0 # number of replacements
system.cpu.l2cache.tags.replacements::total 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 435.916526 # Cycle average of tags in use
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system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 833 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.002401 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 317.007070 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 118.909455 # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.occ_percent::total 0.013303 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 317.099899 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_task_id_blocks::1024 833 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 350 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 483 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 354 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 479 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025421 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 8827 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 8827 # Number of data accesses
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+system.cpu.dcache.overall_miss_latency::total 74375669 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 4073 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 4073 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 5947 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 5947 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 5947 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 5947 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076120 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.076120 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.408092 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.408092 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.172692 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.172692 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.172692 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.172692 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72832.554517 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 72832.554517 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72956.330028 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 72956.330028 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 72917.642648 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 72917.642648 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 72917.642648 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 72917.642648 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 5674 # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 5803 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 5803 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 5803 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 5803 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078075 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.078075 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409249 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.409249 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.176805 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.176805 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.176805 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.176805 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71667.452830 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 71667.452830 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72860.761299 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 72860.761299 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72490.905458 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72490.905458 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72490.905458 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72490.905458 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 5512 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 139 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 138 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.820144 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.942029 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 119 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 560 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 560 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 679 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 679 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 679 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 679 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 562 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 562 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 681 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 681 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 681 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 681 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 199 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 199 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 348 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 348 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 348 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 348 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16537500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 16537500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11999490 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 11999490 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28536990 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 28536990 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28536990 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 28536990 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.047901 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.047901 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data 345 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 345 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16277750 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 16277750 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12037990 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 12037990 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28315740 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 28315740 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28315740 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 28315740 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048858 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048858 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058517 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.058517 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058517 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.058517 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81868.811881 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81868.811881 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82188.287671 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82188.287671 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82002.844828 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 82002.844828 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82002.844828 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 82002.844828 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059452 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.059452 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059452 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.059452 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81797.738693 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81797.738693 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82451.986301 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82451.986301 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82074.608696 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 82074.608696 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82074.608696 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 82074.608696 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
sim_seconds 0.000028 # Number of seconds simulated
-sim_ticks 27662000 # Number of ticks simulated
-final_tick 27662000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 27671000 # Number of ticks simulated
+final_tick 27671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 71683 # Simulator instruction rate (inst/s)
-host_op_rate 71677 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 130761776 # Simulator tick rate (ticks/s)
-host_mem_usage 270740 # Number of bytes of host memory used
-host_seconds 0.21 # Real time elapsed on the host
+host_inst_rate 87465 # Simulator instruction rate (inst/s)
+host_op_rate 87458 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 159601098 # Simulator tick rate (ticks/s)
+host_mem_usage 286440 # Number of bytes of host memory used
+host_seconds 0.17 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.num_reads::cpu.inst 297 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
system.physmem.num_reads::total 435 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 687152050 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 319282771 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1006434820 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 687152050 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 687152050 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 687152050 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 319282771 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1006434820 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 686928553 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 319178924 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1006107477 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 686928553 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 686928553 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 686928553 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 319178924 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1006107477 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 436 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 436 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 27628500 # Total gap between requests
+system.physmem.totGap 27637500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 115 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.bytesPerActivate::768-895 3 4.55% 83.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 11 16.67% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 66 # Bytes accessed per row activation
-system.physmem.totQLat 2526750 # Total ticks spent queuing
-system.physmem.totMemAccLat 10701750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 2648750 # Total ticks spent queuing
+system.physmem.totMemAccLat 10823750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2180000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 5795.30 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 6075.11 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 24545.30 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1008.75 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 24825.11 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1008.42 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1008.75 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1008.42 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 7.88 # Data bus utilization in percentage
system.physmem.busUtilRead 7.88 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.49 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.50 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 362 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.03 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 63368.12 # Average gap between requests
+system.physmem.avgGap 63388.76 # Average gap between requests
system.physmem.pageHitRate 83.03 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 1258750 # Time in different power states
system.physmem.memoryStateTime::REF 780000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 21617500 # Time in different power states
+system.physmem.memoryStateTime::ACT 21626500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 1006434820 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 351 # Transaction distribution
system.membus.trans_dist::ReadResp 350 # Transaction distribution
system.membus.trans_dist::ReadExReq 85 # Transaction distribution
system.membus.trans_dist::ReadExResp 85 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 871 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 871 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27840 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 27840 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 27840 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27840 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 27840 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 436 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 436 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 436 # Request fanout histogram
system.membus.reqLayer0.occupancy 519500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.9 # Layer utilization (%)
system.membus.respLayer1.occupancy 4048500 # Layer occupancy (ticks)
system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 18 # Number of system calls
-system.cpu.numCycles 55325 # number of cpu cycles simulated
+system.cpu.numCycles 55343 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True).
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 21861 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 21863 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 438 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 37757 # Number of cycles cpu's stages were not processed
+system.cpu.timesIdled 440 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 37775 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 17568 # Number of cycles cpu stages are processed.
-system.cpu.activity 31.754180 # Percentage of cycles cpu is active
+system.cpu.activity 31.743852 # Percentage of cycles cpu is active
system.cpu.comLoads 2225 # Number of Load instructions committed
system.cpu.comStores 1448 # Number of Store instructions committed
system.cpu.comBranches 3358 # Number of Branches instructions committed
system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total)
-system.cpu.cpi 3.648925 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 3.650112 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 3.648925 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.274053 # IPC: Instructions Per Cycle (Per-Thread)
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+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54914.715719 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57909.420290 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55860.411899 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54884.615385 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57974.637681 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54914.715719 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57909.420290 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55860.411899 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 98.520897 # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse 98.529834 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 98.520897 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.024053 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.024053 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 98.529834 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.024055 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.024055 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
system.cpu.dcache.overall_misses::total 480 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4268250 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 4268250 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 25916250 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 25916250 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 30184500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 30184500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 30184500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 30184500 # number of overall miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 25898250 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 25898250 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 30166500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 30166500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 30166500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 30166500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73590.517241 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 73590.517241 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61412.914692 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61412.914692 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 62884.375000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 62884.375000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 62884.375000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 62884.375000 # average overall miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61370.260664 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 61370.260664 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 62846.875000 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 62846.875000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 62846.875000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 62846.875000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 1102 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3749750 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3749750 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6096750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 6096750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9846500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 9846500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9846500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 9846500 # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6087750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 6087750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9837500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 9837500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9837500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 9837500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70750 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70750 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71726.470588 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71726.470588 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71351.449275 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 71351.449275 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71351.449275 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 71351.449275 # average overall mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71620.588235 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71620.588235 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71286.231884 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 71286.231884 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71286.231884 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 71286.231884 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 25944000 # Number of ticks simulated
final_tick 25944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 14664 # Simulator instruction rate (inst/s)
-host_op_rate 14664 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 26353337 # Simulator tick rate (ticks/s)
-host_mem_usage 237548 # Number of bytes of host memory used
-host_seconds 0.98 # Real time elapsed on the host
+host_inst_rate 79125 # Simulator instruction rate (inst/s)
+host_op_rate 79119 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 142180718 # Simulator tick rate (ticks/s)
+host_mem_usage 289004 # Number of bytes of host memory used
+host_seconds 0.18 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.bytesPerActivate::896-1023 1 1.39% 84.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 11 15.28% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 72 # Bytes accessed per row activation
-system.physmem.totQLat 2648500 # Total ticks spent queuing
-system.physmem.totMemAccLat 11873500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 2786000 # Total ticks spent queuing
+system.physmem.totMemAccLat 12011000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2460000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 5383.13 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 5662.60 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 24133.13 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 24412.60 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1213.69 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1213.69 # Average system read bandwidth in MiByte/s
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 22761250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 1211224175 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 409 # Transaction distribution
system.membus.trans_dist::ReadResp 408 # Transaction distribution
system.membus.trans_dist::ReadExReq 83 # Transaction distribution
system.membus.trans_dist::ReadExResp 83 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 983 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 983 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 31424 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 492 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 492 # Request fanout histogram
system.membus.reqLayer0.occupancy 611000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 4586750 # Layer occupancy (ticks)
system.cpu.int_regfile_writes 18599 # number of integer regfile writes
system.cpu.misc_regfile_reads 7136 # number of misc regfile reads
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 1216157879 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 295 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 987 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 31552 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 494 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 494 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 579250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.occupancy 233000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 192.510615 # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse 192.510962 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 5925 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 346 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 17.124277 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 192.510615 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst 192.510962 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.093999 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.093999 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id
system.cpu.icache.demand_misses::total 528 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 528 # number of overall misses
system.cpu.icache.overall_misses::total 528 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 32454000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 32454000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 32454000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 32454000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 32454000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 32454000 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 32445000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 32445000 # number of ReadReq miss cycles
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+system.cpu.icache.demand_miss_latency::total 32445000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 32445000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 32445000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 6453 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 6453 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 6453 # number of demand (read+write) accesses
system.cpu.icache.demand_miss_rate::total 0.081822 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.081822 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.081822 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61465.909091 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 61465.909091 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 61465.909091 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 61465.909091 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 61465.909091 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 61465.909091 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61448.863636 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 61448.863636 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 61448.863636 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 61448.863636 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 42 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 346 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 346 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 346 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23048750 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 23048750 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23048750 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 23048750 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23048750 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 23048750 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23039750 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 23039750 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23039750 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 23039750 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23039750 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 23039750 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.053618 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.053618 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.053618 # mshr miss rate for overall accesses
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-system.cpu.icache.demand_avg_mshr_miss_latency::total 66614.884393 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 226.536653 # Cycle average of tags in use
system.cpu.l2cache.tags.sampled_refs 408 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.004902 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.902478 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 34.634175 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.902825 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::cpu.data 0.001057 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.006913 # Average percentage of cache occupancy
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 492 # number of overall MSHR misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22236750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5131500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5131500 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_latency::total 27368250 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995951 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53361.191860 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54368.581907 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61825.301205 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61825.301205 # average ReadExReq mshr miss latency
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60891.891892 # average overall mshr miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 98.823641 # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse 98.823294 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 4124 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 28.054422 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 98.823641 # Average occupied blocks per requestor
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system.cpu.dcache.tags.occ_percent::cpu.data 0.024127 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.024127 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id
system.cpu.dcache.demand_misses::total 548 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 548 # number of overall misses
system.cpu.dcache.overall_misses::total 548 # number of overall misses
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 26093224 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 26093224 # number of WriteReq miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.data 3224 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 3224 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_miss_rate::total 0.117445 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.117445 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.117445 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62314.748201 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 62314.748201 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63797.613692 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 63797.613692 # average WriteReq miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 955 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses
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system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6235500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6235500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020161 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020161 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.031719 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.031719 # mshr miss rate for overall accesses
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75126.506024 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75126.506024 # average WriteReq mshr miss latency
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+system.cpu.dcache.overall_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 7612000 # Number of ticks simulated
final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 945144 # Simulator instruction rate (inst/s)
-host_op_rate 944261 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 473677660 # Simulator tick rate (ticks/s)
-host_mem_usage 260980 # Number of bytes of host memory used
+host_inst_rate 893248 # Simulator instruction rate (inst/s)
+host_op_rate 892512 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 447738368 # Simulator tick rate (ticks/s)
+host_mem_usage 276192 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.physmem.bw_total::cpu.inst 7991066737 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2677877036 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10668943773 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 10676563321 # Throughput (bytes/s)
-system.membus.data_through_bus 81270 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 17432 # Transaction distribution
+system.membus.trans_dist::ReadResp 17432 # Transaction distribution
+system.membus.trans_dist::WriteReq 1442 # Transaction distribution
+system.membus.trans_dist::WriteResp 1442 # Transaction distribution
+system.membus.trans_dist::SwapReq 6 # Transaction distribution
+system.membus.trans_dist::SwapResp 6 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 30414 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 7346 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 37760 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 60828 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 20442 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 81270 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 18880 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.805456 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.395860 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 3673 19.45% 19.45% # Request fanout histogram
+system.membus.snoop_fanout::1 15207 80.55% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 18880 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 15225 # number of cpu cycles simulated
sim_ticks 41368000 # Number of ticks simulated
final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 324057 # Simulator instruction rate (inst/s)
-host_op_rate 323947 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 883591781 # Simulator tick rate (ticks/s)
-host_mem_usage 269720 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 245276 # Simulator instruction rate (inst/s)
+host_op_rate 245221 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 668919684 # Simulator tick rate (ticks/s)
+host_mem_usage 285672 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 430090892 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 213498356 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 643589248 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 643589248 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 331 # Transaction distribution
system.membus.trans_dist::ReadResp 331 # Transaction distribution
system.membus.trans_dist::ReadExReq 85 # Transaction distribution
system.membus.trans_dist::ReadExResp 85 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 26624 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 416 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 416 # Request fanout histogram
system.membus.reqLayer0.occupancy 416000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 3744000 # Layer occupancy (ticks)
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 646683427 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 333 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 418 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks)
---------- Begin Simulation Statistics ----------
sim_seconds 0.000106 # Number of seconds simulated
-sim_ticks 105639000 # Number of ticks simulated
-final_tick 105639000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 105696000 # Number of ticks simulated
+final_tick 105696000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 115016 # Simulator instruction rate (inst/s)
-host_op_rate 115016 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 12246117 # Simulator tick rate (ticks/s)
-host_mem_usage 253808 # Number of bytes of host memory used
-host_seconds 8.63 # Real time elapsed on the host
-sim_insts 992165 # Number of instructions simulated
-sim_ops 992165 # Number of ops (including micro ops) simulated
+host_inst_rate 162054 # Simulator instruction rate (inst/s)
+host_op_rate 162054 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 17251704 # Simulator tick rate (ticks/s)
+host_mem_usage 304448 # Number of bytes of host memory used
+host_seconds 6.13 # Real time elapsed on the host
+sim_insts 992854 # Number of instructions simulated
+sim_ops 992854 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.inst 23104 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 896 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 4928 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 4800 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
system.physmem.bytes_read::total 42752 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 23104 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 4928 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 896 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 4800 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 29056 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst 361 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 14 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 77 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 75 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::total 668 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 218707106 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 101780592 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 7270042 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 7875879 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 46649438 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 12116737 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 2423347 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 7875879 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 404699022 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 218707106 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 7270042 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 46649438 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 2423347 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 275049934 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 218707106 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 101780592 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 7270042 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 7875879 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 46649438 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 12116737 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 2423347 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 7875879 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 404699022 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 218589161 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 101725704 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 8477142 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 7871632 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 45413261 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 12110203 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 2422041 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 7871632 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 404480775 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 218589161 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 8477142 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 45413261 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 2422041 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 274901605 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 218589161 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 101725704 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 8477142 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 7871632 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 45413261 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 12110203 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 2422041 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 7871632 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 404480775 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 669 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 669 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 105611000 # Total gap between requests
+system.physmem.totGap 105668000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 400 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 193 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 399 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 194 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 144 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 278.222222 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 188.203281 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 257.152031 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 43 29.86% 29.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 39 27.08% 56.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 24 16.67% 73.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 13 9.03% 82.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 6 4.17% 86.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 6 4.17% 90.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 6 4.17% 95.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 2 1.39% 96.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 5 3.47% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 144 # Bytes accessed per row activation
-system.physmem.totQLat 6117250 # Total ticks spent queuing
-system.physmem.totMemAccLat 18661000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples 143 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 280.167832 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 190.166692 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 257.214493 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 42 29.37% 29.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 39 27.27% 56.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 24 16.78% 73.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 13 9.09% 82.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 6 4.20% 86.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 6 4.20% 90.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 6 4.20% 95.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 2 1.40% 96.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 5 3.50% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 143 # Bytes accessed per row activation
+system.physmem.totQLat 6392250 # Total ticks spent queuing
+system.physmem.totMemAccLat 18936000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 3345000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 9143.87 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 9554.93 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 27893.87 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 405.30 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 28304.93 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 405.09 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 405.30 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 405.09 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 3.17 # Data bus utilization in percentage
-system.physmem.busUtilRead 3.17 # Data bus utilization in percentage for reads
+system.physmem.busUtil 3.16 # Data bus utilization in percentage
+system.physmem.busUtilRead 3.16 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 514 # Number of row buffer hits during reads
+system.physmem.readRowHits 515 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 76.83 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 76.98 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 157863.98 # Average gap between requests
-system.physmem.pageHitRate 76.83 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 46009250 # Time in different power states
+system.physmem.avgGap 157949.18 # Average gap between requests
+system.physmem.pageHitRate 76.98 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 46119750 # Time in different power states
system.physmem.memoryStateTime::REF 3380000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 52645250 # Time in different power states
+system.physmem.memoryStateTime::ACT 52590250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 404699022 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 538 # Transaction distribution
system.membus.trans_dist::ReadResp 537 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 272 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 276 # Transaction distribution
system.membus.trans_dist::UpgradeResp 78 # Transaction distribution
-system.membus.trans_dist::ReadExReq 182 # Transaction distribution
+system.membus.trans_dist::ReadExReq 177 # Transaction distribution
system.membus.trans_dist::ReadExResp 131 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1738 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1738 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42752 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 42752 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 42752 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 937500 # Layer occupancy (ticks)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1737 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1737 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42752 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 42752 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 244 # Total snoops (count)
+system.membus.snoop_fanout::samples 991 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 991 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 991 # Request fanout histogram
+system.membus.reqLayer0.occupancy 940500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
-system.membus.respLayer1.occupancy 6389922 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 6384422 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 6.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.l2c.tags.replacements 0 # number of replacements
-system.l2c.tags.tagsinuse 424.251527 # Cycle average of tags in use
-system.l2c.tags.total_refs 1658 # Total number of references to valid blocks.
+system.l2c.tags.tagsinuse 424.241443 # Cycle average of tags in use
+system.l2c.tags.total_refs 1667 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 535 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 3.099065 # Average number of references to valid blocks.
+system.l2c.tags.avg_refs 3.115888 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 0.793481 # Average occupied blocks per requestor
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-system.toL2Bus.trans_dist::ReadResp 2757 # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq 2766 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2765 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 413 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 413 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 279 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 279 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 406 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 406 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1225 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 584 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 583 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 361 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 980 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 986 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 371 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 5866 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39168 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31808 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31360 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31552 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 149696 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 149696 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 53248 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 1733986 # Layer occupancy (ticks)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 986 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 353 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 998 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 375 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 5880 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39168 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31808 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31552 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31936 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 150272 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 1022 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 3452 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 3452 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3452 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 1739480 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 2820249 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 2819999 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 1469763 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 1460516 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 2240244 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 2239746 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 2.1 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 1184253 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 1188247 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 2220245 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.occupancy 2234243 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 2.1 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 1188993 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy 1152996 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 2220246 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy 2246748 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 2.1 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 1196995 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy 1204495 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%)
-system.cpu0.branchPred.lookups 81365 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 78481 # Number of conditional branches predicted
+system.cpu0.branchPred.lookups 81418 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 78534 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 1187 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 78090 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 75342 # Number of BTB hits
+system.cpu0.branchPred.BTBLookups 78143 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 75395 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 96.480983 # BTB Hit Percentage
+system.cpu0.branchPred.BTBHitPct 96.483370 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 733 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions.
system.cpu0.workload.num_syscalls 89 # Number of system calls
-system.cpu0.numCycles 211279 # number of cpu cycles simulated
+system.cpu0.numCycles 211393 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 20058 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 480743 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 81365 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 76075 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 164045 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.icacheStallCycles 20064 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 481063 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 81418 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 76128 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 164143 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 2674 # Number of cycles fetch has spent squashing
system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 1880 # Number of stall cycles due to pending traps
system.cpu0.fetch.CacheLines 7123 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 658 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples 187323 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 2.566385 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.225399 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::samples 187427 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 2.566669 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.225288 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 30153 16.10% 16.10% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 77599 41.43% 57.52% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 30149 16.09% 16.09% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 77654 41.43% 57.52% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 823 0.44% 57.96% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 1078 0.58% 58.54% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 624 0.33% 58.87% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 72927 38.93% 97.80% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 1078 0.58% 58.53% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 624 0.33% 58.86% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 72980 38.94% 97.80% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 691 0.37% 98.17% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 437 0.23% 98.40% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 2991 1.60% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 187323 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.385107 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 2.275394 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 15731 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 17849 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 151731 # Number of cycles decode is running
+system.cpu0.fetch.rateDist::total 187427 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.385150 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 2.275681 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 15737 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 17837 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 151841 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 675 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1337 # Number of cycles decode is squashing
-system.cpu0.decode.DecodedInsts 468882 # Number of instructions handled by decode
+system.cpu0.decode.DecodedInsts 469212 # Number of instructions handled by decode
system.cpu0.rename.SquashCycles 1337 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 16349 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 2025 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 14605 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 151742 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 1265 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 465427 # Number of instructions processed by rename
+system.cpu0.rename.IdleCycles 16355 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 2021 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 14599 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 151852 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 1263 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 465757 # Number of instructions processed by rename
system.cpu0.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents 18 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 756 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands 318792 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 928161 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 701504 # Number of integer rename lookups
-system.cpu0.rename.CommittedMaps 304835 # Number of HB maps that are committed
+system.cpu0.rename.RenamedOperands 319012 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 928821 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 701999 # Number of integer rename lookups
+system.cpu0.rename.CommittedMaps 305055 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 13957 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 896 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 905 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 4588 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 148468 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 75131 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 72391 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 72142 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 389496 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.rename.skidInsts 4572 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 148578 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 75186 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 72446 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 72197 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 389771 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 964 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 386182 # Number of instructions issued
+system.cpu0.iq.iqInstsIssued 386457 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 12213 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 11099 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedOperandsExamined 11103 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 405 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 187323 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 2.061583 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.125394 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::samples 187427 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 2.061907 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.125198 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 33109 17.67% 17.67% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 4301 2.30% 19.97% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 73576 39.28% 59.25% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 73130 39.04% 98.29% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 1662 0.89% 99.18% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 894 0.48% 99.65% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 408 0.22% 99.87% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 33106 17.66% 17.66% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 4299 2.29% 19.96% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 73629 39.28% 59.24% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 73187 39.05% 98.29% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 1656 0.88% 99.17% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 900 0.48% 99.65% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 407 0.22% 99.87% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 171 0.09% 99.96% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 72 0.04% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 187323 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 187427 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 97 34.15% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 34.15% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 84 29.58% 63.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 103 36.27% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 96 33.92% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.92% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 84 29.68% 63.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 103 36.40% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 163788 42.41% 42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 163898 42.41% 42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.41% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 147930 38.31% 80.72% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 74464 19.28% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 148040 38.31% 80.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 74519 19.28% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 386182 # Type of FU issued
-system.cpu0.iq.rate 1.827830 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 284 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.000735 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 959994 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 402726 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 384333 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.FU_type_0::total 386457 # Type of FU issued
+system.cpu0.iq.rate 1.828145 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 283 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.000732 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 960647 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 403001 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 384607 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 386466 # Number of integer alu accesses
+system.cpu0.iq.int_alu_accesses 386740 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 71762 # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.forwLoads 71819 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 2461 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 1337 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 1986 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 48 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 463277 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewBlockCycles 1980 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 463607 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 160 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 148468 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 75131 # Number of dispatched store instructions
+system.cpu0.iew.iewDispLoadInsts 148578 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 75186 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 843 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 43 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewIQFullEvents 45 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 323 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 1099 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 1422 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 385174 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 147630 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 1008 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewExecutedInsts 385445 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 147736 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 72817 # number of nop insts executed
-system.cpu0.iew.exec_refs 221956 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 76403 # Number of branches executed
-system.cpu0.iew.exec_stores 74326 # Number of stores executed
-system.cpu0.iew.exec_rate 1.823059 # Inst execution rate
-system.cpu0.iew.wb_sent 384701 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 384333 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 227933 # num instructions producing a value
-system.cpu0.iew.wb_consumers 231165 # num instructions consuming a value
+system.cpu0.iew.exec_nop 72872 # number of nop insts executed
+system.cpu0.iew.exec_refs 222117 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 76458 # Number of branches executed
+system.cpu0.iew.exec_stores 74381 # Number of stores executed
+system.cpu0.iew.exec_rate 1.823357 # Inst execution rate
+system.cpu0.iew.wb_sent 384977 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 384607 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 228096 # num instructions producing a value
+system.cpu0.iew.wb_consumers 231328 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 1.819078 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.986019 # average fanout of values written-back
+system.cpu0.iew.wb_rate 1.819393 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.986028 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts 13622 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 1187 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 184699 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 2.434252 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 2.147591 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::samples 184803 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 2.434668 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 2.147538 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 33306 18.03% 18.03% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 75499 40.88% 58.91% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 2011 1.09% 60.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 643 0.35% 60.35% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 527 0.29% 60.63% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 71457 38.69% 99.32% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 519 0.28% 99.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 33298 18.02% 18.02% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 75556 40.88% 58.90% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 2014 1.09% 59.99% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 640 0.35% 60.34% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 527 0.29% 60.62% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 71511 38.70% 99.32% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 520 0.28% 99.60% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 249 0.13% 99.74% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 488 0.26% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 184699 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 449604 # Number of instructions committed
-system.cpu0.commit.committedOps 449604 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 184803 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 449934 # Number of instructions committed
+system.cpu0.commit.committedOps 449934 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 219517 # Number of memory references committed
-system.cpu0.commit.loads 146007 # Number of loads committed
+system.cpu0.commit.refs 219682 # Number of memory references committed
+system.cpu0.commit.loads 146117 # Number of loads committed
system.cpu0.commit.membars 84 # Number of memory barriers committed
-system.cpu0.commit.branches 75397 # Number of branches committed
+system.cpu0.commit.branches 75452 # Number of branches committed
system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 303166 # Number of committed integer instructions.
+system.cpu0.commit.int_insts 303386 # Number of committed integer instructions.
system.cpu0.commit.function_calls 223 # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass 72129 16.04% 16.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 157874 35.11% 51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::No_OpClass 72184 16.04% 16.04% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 157984 35.11% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 146091 32.49% 83.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 73510 16.35% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead 146201 32.49% 83.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite 73565 16.35% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total 449604 # Class of committed instruction
+system.cpu0.commit.op_class_0::total 449934 # Class of committed instruction
system.cpu0.commit.bw_lim_events 488 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 646276 # The number of ROB reads
-system.cpu0.rob.rob_writes 929096 # The number of ROB writes
-system.cpu0.timesIdled 317 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 23956 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.committedInsts 377391 # Number of Instructions Simulated
-system.cpu0.committedOps 377391 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 0.559841 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 0.559841 # CPI: Total CPI of All Threads
-system.cpu0.ipc 1.786221 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 1.786221 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 688854 # number of integer regfile reads
-system.cpu0.int_regfile_writes 310766 # number of integer regfile writes
+system.cpu0.rob.rob_reads 646710 # The number of ROB reads
+system.cpu0.rob.rob_writes 929756 # The number of ROB writes
+system.cpu0.timesIdled 318 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 23966 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.committedInsts 377666 # Number of Instructions Simulated
+system.cpu0.committedOps 377666 # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi 0.559735 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 0.559735 # CPI: Total CPI of All Threads
+system.cpu0.ipc 1.786559 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 1.786559 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 689341 # number of integer regfile reads
+system.cpu0.int_regfile_writes 310987 # number of integer regfile writes
system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
-system.cpu0.misc_regfile_reads 223843 # number of misc regfile reads
+system.cpu0.misc_regfile_reads 224004 # number of misc regfile reads
system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
system.cpu0.icache.tags.replacements 322 # number of replacements
-system.cpu0.icache.tags.tagsinuse 240.566848 # Cycle average of tags in use
+system.cpu0.icache.tags.tagsinuse 240.567538 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 6326 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 612 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 10.336601 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 240.566848 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.469857 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.469857 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 240.567538 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.469858 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.469858 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id
system.cpu0.icache.demand_misses::total 797 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 797 # number of overall misses
system.cpu0.icache.overall_misses::total 797 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 36681496 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 36681496 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 36681496 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 36681496 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 36681496 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 36681496 # number of overall miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 36689746 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 36689746 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 36689746 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 36689746 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 36689746 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 36689746 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 7123 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 7123 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 7123 # number of demand (read+write) accesses
system.cpu0.icache.demand_miss_rate::total 0.111891 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111891 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.111891 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46024.461731 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 46024.461731 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46024.461731 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 46024.461731 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46024.461731 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 46024.461731 # average overall miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46034.813049 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 46034.813049 # average ReadReq miss latency
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-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41302.944134 # average WriteReq mshr miss latency
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+system.cpu0.dcache.demand_mshr_miss_rate::total 0.002417 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002417 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.002417 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34387.401099 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34387.401099 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41272.217877 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41272.217877 # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17375 # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17375 # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37755.488950 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37755.488950 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37755.488950 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37755.488950 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37801.202216 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37801.202216 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37801.202216 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37801.202216 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 54588 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 51200 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 1286 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 47257 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 46317 # Number of BTB hits
+system.cpu1.branchPred.lookups 52620 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 49209 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 1295 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 45306 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 44357 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 98.010877 # BTB Hit Percentage
+system.cpu1.branchPred.BTBHitPct 97.905355 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 875 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
-system.cpu1.numCycles 167979 # number of cpu cycles simulated
+system.cpu1.numCycles 161023 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 29917 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 303462 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 54588 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 47192 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 126841 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 2730 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.icacheStallCycles 31247 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 289875 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 52620 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 45232 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 125550 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 2747 # Number of cycles fetch has spent squashing
system.cpu1.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.NoActiveThreadStallCycles 7060 # Number of stall cycles due to no active thread to fetch from
-system.cpu1.fetch.PendingTrapStallCycles 1096 # Number of stall cycles due to pending traps
-system.cpu1.fetch.CacheLines 21062 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 421 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 166282 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 1.824984 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.191628 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
+system.cpu1.fetch.PendingTrapStallCycles 1122 # Number of stall cycles due to pending traps
+system.cpu1.fetch.CacheLines 22380 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 446 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples 159305 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.819623 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.179377 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 60365 36.30% 36.30% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 53424 32.13% 68.43% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 6309 3.79% 72.23% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 3483 2.09% 74.32% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1022 0.61% 74.93% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 35711 21.48% 96.41% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1327 0.80% 97.21% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 762 0.46% 97.67% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 3879 2.33% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 56744 35.62% 35.62% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 52063 32.68% 68.30% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 6924 4.35% 72.65% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 3540 2.22% 74.87% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1103 0.69% 75.56% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 33079 20.76% 96.33% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1261 0.79% 97.12% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 757 0.48% 97.59% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 3834 2.41% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 166282 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.324969 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 1.806547 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 17455 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 52641 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 84496 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 3265 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 1365 # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts 289136 # Number of instructions handled by decode
-system.cpu1.rename.SquashCycles 1365 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 18178 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 24205 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 12371 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 85331 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 17772 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 285586 # Number of instructions processed by rename
-system.cpu1.rename.IQFullEvents 15350 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full
+system.cpu1.fetch.rateDist::total 159305 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.326786 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 1.800209 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 17668 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 57241 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 79500 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 3513 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 1373 # Number of cycles decode is squashing
+system.cpu1.decode.DecodedInsts 275603 # Number of instructions handled by decode
+system.cpu1.rename.SquashCycles 1373 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 18384 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 26779 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 12577 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 80781 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 19401 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 272270 # Number of instructions processed by rename
+system.cpu1.rename.IQFullEvents 17163 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 27 # Number of times rename has blocked due to LQ full
system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 200979 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 548958 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 426905 # Number of integer rename lookups
-system.cpu1.rename.CommittedMaps 186309 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 14670 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 1186 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 1247 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 22653 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 80668 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 38514 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 38418 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 33330 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 237514 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 6089 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 238789 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 33 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 12748 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 11558 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 612 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 166282 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 1.436048 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.378738 # Number of insts issued each cycle
+system.cpu1.rename.RenamedOperands 191050 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 520032 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 405162 # Number of integer rename lookups
+system.cpu1.rename.CommittedMaps 176680 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 14370 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 1196 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 1257 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 24088 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 76067 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 35939 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 36374 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 30769 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 225624 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 6666 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 227547 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 18 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 12526 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 11238 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 649 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 159305 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 1.428373 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.374842 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 63923 38.44% 38.44% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 20825 12.52% 50.97% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 37813 22.74% 73.71% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 37389 22.49% 96.19% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 3420 2.06% 98.25% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1614 0.97% 99.22% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 862 0.52% 99.74% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 239 0.14% 99.88% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 60375 37.90% 37.90% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 22487 14.12% 52.01% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 35297 22.16% 74.17% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 34879 21.89% 96.07% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 3406 2.14% 98.20% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1579 0.99% 99.20% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 861 0.54% 99.74% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 224 0.14% 99.88% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 197 0.12% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 166282 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 159305 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 89 25.65% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 49 14.12% 39.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 209 60.23% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 89 26.49% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 26.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 38 11.31% 37.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 209 62.20% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 116312 48.71% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 84679 35.46% 84.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 37798 15.83% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 111688 49.08% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 80614 35.43% 84.51% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 35245 15.49% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 238789 # Type of FU issued
-system.cpu1.iq.rate 1.421541 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 347 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.001453 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 644240 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 256392 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 237045 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.FU_type_0::total 227547 # Type of FU issued
+system.cpu1.iq.rate 1.413134 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 336 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.001477 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 614753 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 244854 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 225845 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 239136 # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses 227883 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 33095 # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads 30551 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 2693 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2638 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1647 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1613 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 1365 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 6579 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 282823 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 167 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 80668 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 38514 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 1105 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewSquashCycles 1373 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 7085 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 269526 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 186 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 76067 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 35939 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 1117 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 476 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 1037 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 1507 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 237631 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 79596 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 1158 # Number of squashed instructions skipped in execute
+system.cpu1.iew.branchMispredicts 1513 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 226408 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 75003 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1139 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 39220 # number of nop insts executed
-system.cpu1.iew.exec_refs 117284 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 48640 # Number of branches executed
-system.cpu1.iew.exec_stores 37688 # Number of stores executed
-system.cpu1.iew.exec_rate 1.414647 # Inst execution rate
-system.cpu1.iew.wb_sent 237349 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 237045 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 134973 # num instructions producing a value
-system.cpu1.iew.wb_consumers 141559 # num instructions consuming a value
+system.cpu1.iew.exec_nop 37236 # number of nop insts executed
+system.cpu1.iew.exec_refs 110148 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 46633 # Number of branches executed
+system.cpu1.iew.exec_stores 35145 # Number of stores executed
+system.cpu1.iew.exec_rate 1.406060 # Inst execution rate
+system.cpu1.iew.wb_sent 226126 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 225845 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 127804 # num instructions producing a value
+system.cpu1.iew.wb_consumers 134338 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 1.411159 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.953475 # average fanout of values written-back
+system.cpu1.iew.wb_rate 1.402564 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.951361 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 14310 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 5477 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 1286 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 156616 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 1.714129 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 2.075319 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 14108 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 6017 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 1295 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 156709 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 1.629549 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 2.048246 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 61979 39.57% 39.57% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 45369 28.97% 68.54% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 5243 3.35% 71.89% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 6285 4.01% 75.90% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1549 0.99% 76.89% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 33128 21.15% 98.04% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 818 0.52% 98.57% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 954 0.61% 99.18% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1291 0.82% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 66028 42.13% 42.13% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 43411 27.70% 69.84% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 5268 3.36% 73.20% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 6809 4.34% 77.54% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1543 0.98% 78.53% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 30606 19.53% 98.06% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 798 0.51% 98.57% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 967 0.62% 99.18% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1279 0.82% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 156616 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 268460 # Number of instructions committed
-system.cpu1.commit.committedOps 268460 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 156709 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 255365 # Number of instructions committed
+system.cpu1.commit.committedOps 255365 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 114842 # Number of memory references committed
-system.cpu1.commit.loads 77975 # Number of loads committed
-system.cpu1.commit.membars 4761 # Number of memory barriers committed
-system.cpu1.commit.branches 47591 # Number of branches committed
+system.cpu1.commit.refs 107755 # Number of memory references committed
+system.cpu1.commit.loads 73429 # Number of loads committed
+system.cpu1.commit.membars 5300 # Number of memory barriers committed
+system.cpu1.commit.branches 45589 # Number of branches committed
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 184553 # Number of committed integer instructions.
+system.cpu1.commit.int_insts 175463 # Number of committed integer instructions.
system.cpu1.commit.function_calls 322 # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass 38379 14.30% 14.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 110478 41.15% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 82736 30.82% 86.27% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 36867 13.73% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::No_OpClass 36376 14.24% 14.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 105934 41.48% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead 78729 30.83% 86.56% # Class of committed instruction
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system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 268460 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 1291 # number cycles where commit BW limit reached
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system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 437508 # The number of ROB reads
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-system.cpu1.timesIdled 207 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 1697 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 43298 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 225320 # Number of Instructions Simulated
-system.cpu1.committedOps 225320 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 0.745513 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 0.745513 # CPI: Total CPI of All Threads
-system.cpu1.ipc 1.341358 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 1.341358 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 411671 # number of integer regfile reads
-system.cpu1.int_regfile_writes 192443 # number of integer regfile writes
+system.cpu1.rob.rob_reads 424317 # The number of ROB reads
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+system.cpu1.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 1718 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 43314 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 213689 # Number of Instructions Simulated
+system.cpu1.committedOps 213689 # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi 0.753539 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 0.753539 # CPI: Total CPI of All Threads
+system.cpu1.ipc 1.327071 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 1.327071 # IPC: Total IPC of All Threads
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system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 118908 # number of misc regfile reads
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system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
system.cpu1.icache.tags.replacements 388 # number of replacements
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system.cpu1.icache.tags.sampled_refs 497 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 41.241449 # Average number of references to valid blocks.
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system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu1.icache.tags.occ_task_id_blocks::1024 109 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 0.212891 # Percentage of cache occupancy per task id
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-system.cpu1.icache.overall_hits::total 20497 # number of overall hits
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-system.cpu1.icache.ReadReq_misses::total 565 # number of ReadReq misses
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-system.cpu1.icache.demand_misses::total 565 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 565 # number of overall misses
-system.cpu1.icache.overall_misses::total 565 # number of overall misses
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-system.cpu1.icache.ReadReq_miss_latency::total 8463744 # number of ReadReq miss cycles
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-system.cpu1.icache.demand_miss_latency::total 8463744 # number of demand (read+write) miss cycles
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-system.cpu1.icache.overall_miss_latency::total 8463744 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 21062 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 21062 # number of ReadReq accesses(hits+misses)
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-system.cpu1.icache.ReadReq_avg_miss_latency::total 14980.077876 # average ReadReq miss latency
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-system.cpu1.icache.overall_avg_miss_latency::total 14980.077876 # average overall miss latency
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+system.cpu1.icache.overall_misses::total 559 # number of overall misses
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+system.cpu1.icache.ReadReq_miss_latency::total 8425746 # number of ReadReq miss cycles
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system.cpu1.icache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
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-system.cpu1.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits
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-system.cpu1.icache.overall_mshr_hits::total 68 # number of overall MSHR hits
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system.cpu1.icache.demand_mshr_misses::cpu1.inst 497 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 497 # number of demand (read+write) MSHR misses
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system.cpu1.icache.overall_mshr_misses::total 497 # number of overall MSHR misses
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-system.cpu1.icache.ReadReq_mshr_miss_latency::total 6616756 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6616756 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 6616756 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6616756 # number of overall MSHR miss cycles
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-system.cpu1.icache.demand_avg_mshr_miss_latency::total 13313.392354 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13313.392354 # average overall mshr miss latency
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+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13376.768612 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 13376.768612 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements 0 # number of replacements
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system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu1.dcache.overall_misses::total 567 # number of overall misses
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-system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
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-system.cpu1.dcache.overall_accesses::cpu1.data 83283 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 83283 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009186 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.009186 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003805 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.003805 # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.814286 # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total 0.814286 # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006808 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.006808 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006808 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.006808 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13389.002342 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 13389.002342 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20289.364286 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 20289.364286 # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 8175.543860 # average SwapReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::total 8175.543860 # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15092.795414 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 15092.795414 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15092.795414 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 15092.795414 # average overall miss latency
+system.cpu1.dcache.demand_hits::cpu1.data 78117 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 78117 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 78117 # number of overall hits
+system.cpu1.dcache.overall_hits::total 78117 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 439 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 439 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 136 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 136 # number of WriteReq misses
+system.cpu1.dcache.SwapReq_misses::cpu1.data 58 # number of SwapReq misses
+system.cpu1.dcache.SwapReq_misses::total 58 # number of SwapReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 575 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 575 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 575 # number of overall misses
+system.cpu1.dcache.overall_misses::total 575 # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5820038 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 5820038 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2819511 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 2819511 # number of WriteReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 502006 # number of SwapReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::total 502006 # number of SwapReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 8639549 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 8639549 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 8639549 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 8639549 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 44437 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 44437 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 34255 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 34255 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 78692 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 78692 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 78692 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 78692 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009879 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.009879 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003970 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.003970 # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.816901 # miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007307 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.007307 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007307 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.007307 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13257.489749 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 13257.489749 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20731.698529 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 20731.698529 # average WriteReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 8655.275862 # average SwapReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::total 8655.275862 # average SwapReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15025.302609 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 15025.302609 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15025.302609 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 15025.302609 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 269 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 269 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 35 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 304 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 304 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 304 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 304 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 158 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1020514 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1020514 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1289239 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1289239 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 351994 # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::total 351994 # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2309753 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 2309753 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2309753 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 2309753 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003399 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003399 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002853 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002853 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.814286 # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.814286 # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003158 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.003158 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003158 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.003158 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6458.949367 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6458.949367 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12278.466667 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12278.466667 # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6175.333333 # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6175.333333 # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 8782.330798 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 8782.330798 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 8782.330798 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 8782.330798 # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 276 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 276 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 308 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 308 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 308 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 308 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 104 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 58 # number of SwapReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 267 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 267 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1085520 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1085520 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1288239 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1288239 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 385994 # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total 385994 # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2373759 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 2373759 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2373759 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 2373759 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003668 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003668 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003036 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003036 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.816901 # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003393 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.003393 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003393 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.003393 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6659.631902 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6659.631902 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12386.913462 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12386.913462 # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6655.068966 # average SwapReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6655.068966 # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 8890.483146 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 8890.483146 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 8890.483146 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 8890.483146 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.branchPred.lookups 50591 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 46824 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 1298 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 43166 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 41772 # Number of BTB hits
+system.cpu2.branchPred.lookups 52660 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 48877 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 1286 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 45218 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 43881 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 96.770606 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 904 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.BTBHitPct 97.043213 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 913 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
-system.cpu2.numCycles 167617 # number of cpu cycles simulated
+system.cpu2.numCycles 160663 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 31796 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 277876 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 50591 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 42676 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 121192 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 2752 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.icacheStallCycles 30584 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 291962 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 52660 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 44794 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 122431 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 2729 # Number of cycles fetch has spent squashing
system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.NoActiveThreadStallCycles 7062 # Number of stall cycles due to no active thread to fetch from
-system.cpu2.fetch.PendingTrapStallCycles 1110 # Number of stall cycles due to pending traps
+system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
+system.cpu2.fetch.PendingTrapStallCycles 1111 # Number of stall cycles due to pending traps
system.cpu2.fetch.IcacheWaitRetryStallCycles 3 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 22366 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 459 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples 162543 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.709554 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.176994 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.CacheLines 21169 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 445 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples 155507 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.877485 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.219728 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 64711 39.81% 39.81% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 49634 30.54% 70.35% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 6798 4.18% 74.53% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 3442 2.12% 76.65% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 952 0.59% 77.23% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 30771 18.93% 96.16% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 1187 0.73% 96.89% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 849 0.52% 97.42% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 4199 2.58% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 53998 34.72% 34.72% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 51209 32.93% 67.65% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 6210 3.99% 71.65% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 3413 2.19% 73.84% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 933 0.60% 74.44% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 33386 21.47% 95.91% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 1293 0.83% 96.74% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 846 0.54% 97.29% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 4219 2.71% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 162543 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.301825 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 1.657803 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 17997 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 57677 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 74910 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 3521 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 1376 # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts 262355 # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles 1376 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 18679 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 27128 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 12799 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 76466 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 19033 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 259235 # Number of instructions processed by rename
-system.cpu2.rename.IQFullEvents 17033 # Number of times rename has blocked due to IQ full
+system.cpu2.fetch.rateDist::total 155507 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.327767 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 1.817232 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 17863 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 52592 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 80411 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 3267 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 1364 # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts 276853 # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles 1364 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 18564 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 24147 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 12636 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 81735 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 17051 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 273529 # Number of instructions processed by rename
+system.cpu2.rename.IQFullEvents 15090 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full
system.cpu2.rename.FullRegisterEvents 6 # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands 182575 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 494395 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 386046 # Number of integer rename lookups
-system.cpu2.rename.CommittedMaps 167620 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 14955 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 1169 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 1235 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 23554 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 71776 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 33725 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 34298 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 28594 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 214929 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 6621 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 216336 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 13228 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 12296 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 674 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 162543 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.330946 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.384454 # Number of insts issued each cycle
+system.cpu2.rename.RenamedOperands 193256 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 525177 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 409210 # Number of integer rename lookups
+system.cpu2.rename.CommittedMaps 178291 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 14965 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 1175 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 1247 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 21746 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 76624 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 36478 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 36325 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 31287 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 227715 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 6015 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 228842 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 34 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 13120 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 11533 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 647 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 155507 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.471586 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.386146 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 68368 42.06% 42.06% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 22285 13.71% 55.77% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 32950 20.27% 76.04% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 32546 20.02% 96.07% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 3459 2.13% 98.19% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 1594 0.98% 99.17% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 888 0.55% 99.72% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 245 0.15% 99.87% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 208 0.13% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 57410 36.92% 36.92% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 20565 13.22% 50.14% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 35759 23.00% 73.14% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 35374 22.75% 95.89% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 3397 2.18% 98.07% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 1636 1.05% 99.12% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 896 0.58% 99.70% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 267 0.17% 99.87% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 203 0.13% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 162543 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 155507 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 90 24.93% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 24.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 62 17.17% 42.11% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 209 57.89% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 89 26.57% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 26.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 37 11.04% 37.61% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 209 62.39% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 107190 49.55% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.55% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 76124 35.19% 84.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 33022 15.26% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 112448 49.14% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 80571 35.21% 84.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 35823 15.65% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 216336 # Type of FU issued
-system.cpu2.iq.rate 1.290657 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 361 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.001669 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 595623 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 234822 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 214628 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.FU_type_0::total 228842 # Type of FU issued
+system.cpu2.iq.rate 1.424360 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 335 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.001464 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 613560 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 246890 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 227101 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 216697 # Number of integer alu accesses
+system.cpu2.iq.int_alu_accesses 229177 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 28314 # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.forwLoads 31107 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 2909 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 2702 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 1648 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 1596 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 1376 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 7567 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 67 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 256538 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 192 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 71776 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 33725 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 1099 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewSquashCycles 1364 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 6807 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 270837 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 190 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 76624 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 36478 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 1098 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 44 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 464 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 1069 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 1533 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 215226 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 70571 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 1110 # Number of squashed instructions skipped in execute
+system.cpu2.iew.memOrderViolationEvents 40 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 1049 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 1519 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 227700 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 75599 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 1142 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 34988 # number of nop insts executed
-system.cpu2.iew.exec_refs 103485 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 44292 # Number of branches executed
-system.cpu2.iew.exec_stores 32914 # Number of stores executed
-system.cpu2.iew.exec_rate 1.284034 # Inst execution rate
-system.cpu2.iew.wb_sent 214935 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 214628 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 121102 # num instructions producing a value
-system.cpu2.iew.wb_consumers 127756 # num instructions consuming a value
+system.cpu2.iew.exec_nop 37107 # number of nop insts executed
+system.cpu2.iew.exec_refs 111310 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 46563 # Number of branches executed
+system.cpu2.iew.exec_stores 35711 # Number of stores executed
+system.cpu2.iew.exec_rate 1.417252 # Inst execution rate
+system.cpu2.iew.wb_sent 227402 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 227101 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 129036 # num instructions producing a value
+system.cpu2.iew.wb_consumers 135804 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 1.280467 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.947916 # average fanout of values written-back
+system.cpu2.iew.wb_rate 1.413524 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.950163 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 14883 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 5947 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 1298 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 152800 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.581165 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 2.037167 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 14614 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 5368 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 1286 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 152859 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.675858 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 2.068536 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 66891 43.78% 43.78% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 41018 26.84% 70.62% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 5166 3.38% 74.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 6776 4.43% 78.44% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 1516 0.99% 79.43% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 28304 18.52% 97.95% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 869 0.57% 98.52% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 954 0.62% 99.15% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 1306 0.85% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 62472 40.87% 40.87% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 43239 28.29% 69.16% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 5166 3.38% 72.54% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 6247 4.09% 76.62% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 1528 1.00% 77.62% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 31073 20.33% 97.95% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 875 0.57% 98.52% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 941 0.62% 99.14% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 1318 0.86% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 152800 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 241602 # Number of instructions committed
-system.cpu2.commit.committedOps 241602 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 152859 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 256170 # Number of instructions committed
+system.cpu2.commit.committedOps 256170 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 100944 # Number of memory references committed
-system.cpu2.commit.loads 68867 # Number of loads committed
-system.cpu2.commit.membars 5232 # Number of memory barriers committed
-system.cpu2.commit.branches 43270 # Number of branches committed
+system.cpu2.commit.refs 108804 # Number of memory references committed
+system.cpu2.commit.loads 73922 # Number of loads committed
+system.cpu2.commit.membars 4659 # Number of memory barriers committed
+system.cpu2.commit.branches 45502 # Number of branches committed
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 166336 # Number of committed integer instructions.
+system.cpu2.commit.int_insts 176434 # Number of committed integer instructions.
system.cpu2.commit.function_calls 322 # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass 34059 14.10% 14.10% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu 101367 41.96% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead 74099 30.67% 86.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite 32077 13.28% 100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::No_OpClass 36297 14.17% 14.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu 106410 41.54% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead 78581 30.68% 86.38% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite 34882 13.62% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total 241602 # Class of committed instruction
-system.cpu2.commit.bw_lim_events 1306 # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total 256170 # Class of committed instruction
+system.cpu2.commit.bw_lim_events 1318 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 407392 # The number of ROB reads
-system.cpu2.rob.rob_writes 515662 # The number of ROB writes
-system.cpu2.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 5074 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 43660 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 202311 # Number of Instructions Simulated
-system.cpu2.committedOps 202311 # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi 0.828512 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 0.828512 # CPI: Total CPI of All Threads
-system.cpu2.ipc 1.206984 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 1.206984 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 370344 # number of integer regfile reads
-system.cpu2.int_regfile_writes 173891 # number of integer regfile writes
+system.cpu2.rob.rob_reads 421739 # The number of ROB reads
+system.cpu2.rob.rob_writes 544215 # The number of ROB writes
+system.cpu2.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 5156 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 43676 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 215214 # Number of Instructions Simulated
+system.cpu2.committedOps 215214 # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi 0.746527 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 0.746527 # CPI: Total CPI of All Threads
+system.cpu2.ipc 1.339537 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 1.339537 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 394013 # number of integer regfile reads
+system.cpu2.int_regfile_writes 184721 # number of integer regfile writes
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 105089 # number of misc regfile reads
+system.cpu2.misc_regfile_reads 112958 # number of misc regfile reads
system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
-system.cpu2.icache.tags.replacements 378 # number of replacements
-system.cpu2.icache.tags.tagsinuse 84.908829 # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs 21796 # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs 490 # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs 44.481633 # Average number of references to valid blocks.
+system.cpu2.icache.tags.replacements 380 # number of replacements
+system.cpu2.icache.tags.tagsinuse 85.367642 # Cycle average of tags in use
+system.cpu2.icache.tags.total_refs 20592 # Total number of references to valid blocks.
+system.cpu2.icache.tags.sampled_refs 493 # Sample count of references to valid blocks.
+system.cpu2.icache.tags.avg_refs 41.768763 # Average number of references to valid blocks.
system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst 84.908829 # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst 0.165838 # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total 0.165838 # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_task_id_blocks::1024 112 # Occupied blocks per task id
+system.cpu2.icache.tags.occ_blocks::cpu2.inst 85.367642 # Average occupied blocks per requestor
+system.cpu2.icache.tags.occ_percent::cpu2.inst 0.166734 # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_percent::total 0.166734 # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id
-system.cpu2.icache.tags.occ_task_id_percent::1024 0.218750 # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses 22856 # Number of tag accesses
-system.cpu2.icache.tags.data_accesses 22856 # Number of data accesses
-system.cpu2.icache.ReadReq_hits::cpu2.inst 21796 # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total 21796 # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst 21796 # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total 21796 # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst 21796 # number of overall hits
-system.cpu2.icache.overall_hits::total 21796 # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst 570 # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total 570 # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst 570 # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total 570 # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst 570 # number of overall misses
-system.cpu2.icache.overall_misses::total 570 # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 13348494 # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total 13348494 # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst 13348494 # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total 13348494 # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst 13348494 # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total 13348494 # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst 22366 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total 22366 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst 22366 # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total 22366 # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst 22366 # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total 22366 # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.025485 # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total 0.025485 # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst 0.025485 # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total 0.025485 # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst 0.025485 # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total 0.025485 # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23418.410526 # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 23418.410526 # average ReadReq miss latency
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+system.cpu2.dcache.SwapReq_avg_miss_latency::total 9204.204082 # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 19724.793961 # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 19724.793961 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19724.793961 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 19724.793961 # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
-system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 261 # number of ReadReq MSHR hits
-system.cpu2.dcache.ReadReq_mshr_hits::total 261 # number of ReadReq MSHR hits
+system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 262 # number of ReadReq MSHR hits
+system.cpu2.dcache.ReadReq_mshr_hits::total 262 # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 40 # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total 40 # number of WriteReq MSHR hits
-system.cpu2.dcache.demand_mshr_hits::cpu2.data 301 # number of demand (read+write) MSHR hits
-system.cpu2.dcache.demand_mshr_hits::total 301 # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits::cpu2.data 301 # number of overall MSHR hits
-system.cpu2.dcache.overall_mshr_hits::total 301 # number of overall MSHR hits
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 55 # number of SwapReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1541774 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1541774 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1509739 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1509739 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 389494 # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::total 389494 # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3051513 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total 3051513 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3051513 # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total 3051513 # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003812 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003812 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003312 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003312 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.797101 # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.797101 # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003596 # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total 0.003596 # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003596 # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total 0.003596 # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9576.236025 # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9576.236025 # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14242.820755 # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14242.820755 # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7081.709091 # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7081.709091 # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11428.887640 # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11428.887640 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11428.887640 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11428.887640 # average overall mshr miss latency
+system.cpu2.dcache.demand_mshr_hits::cpu2.data 302 # number of demand (read+write) MSHR hits
+system.cpu2.dcache.demand_mshr_hits::total 302 # number of demand (read+write) MSHR hits
+system.cpu2.dcache.overall_mshr_hits::cpu2.data 302 # number of overall MSHR hits
+system.cpu2.dcache.overall_mshr_hits::total 302 # number of overall MSHR hits
+system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 153 # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 49 # number of SwapReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::total 49 # number of SwapReq MSHR misses
+system.cpu2.dcache.demand_mshr_misses::cpu2.data 261 # number of demand (read+write) MSHR misses
+system.cpu2.dcache.demand_mshr_misses::total 261 # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses::cpu2.data 261 # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_misses::total 261 # number of overall MSHR misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1686771 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1686771 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1511239 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1511239 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 352994 # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::total 352994 # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3198010 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total 3198010 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3198010 # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total 3198010 # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003440 # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003440 # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003102 # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003102 # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.777778 # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.777778 # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003292 # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_miss_rate::total 0.003292 # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003292 # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_miss_rate::total 0.003292 # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11024.647059 # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11024.647059 # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13992.953704 # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13992.953704 # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7203.959184 # average SwapReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7203.959184 # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12252.911877 # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12252.911877 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12252.911877 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12252.911877 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.branchPred.lookups 48151 # Number of BP lookups
-system.cpu3.branchPred.condPredicted 44685 # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect 1287 # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups 41038 # Number of BTB lookups
-system.cpu3.branchPred.BTBHits 39836 # Number of BTB hits
+system.cpu3.branchPred.lookups 48141 # Number of BP lookups
+system.cpu3.branchPred.condPredicted 44605 # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect 1305 # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups 40897 # Number of BTB lookups
+system.cpu3.branchPred.BTBHits 39710 # Number of BTB hits
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct 97.071007 # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS 888 # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.BTBHitPct 97.097587 # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS 884 # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
-system.cpu3.numCycles 167273 # number of cpu cycles simulated
+system.cpu3.numCycles 160319 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles 33692 # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts 260486 # Number of instructions fetch has processed
-system.cpu3.fetch.Branches 48151 # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches 40724 # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles 122974 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles 2726 # Number of cycles fetch has spent squashing
+system.cpu3.fetch.icacheStallCycles 33851 # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts 260297 # Number of instructions fetch has processed
+system.cpu3.fetch.Branches 48141 # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches 40594 # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles 122891 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles 2765 # Number of cycles fetch has spent squashing
system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.NoActiveThreadStallCycles 7060 # Number of stall cycles due to no active thread to fetch from
+system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles 1076 # Number of stall cycles due to pending traps
-system.cpu3.fetch.CacheLines 24907 # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes 418 # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples 166168 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean 1.567606 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev 2.102870 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.CacheLines 24972 # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes 417 # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.rateDist::samples 159213 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean 1.634898 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev 2.125574 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0 71279 42.90% 42.90% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1 48852 29.40% 72.29% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2 8282 4.98% 77.28% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3 3511 2.11% 79.39% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4 1059 0.64% 80.03% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5 27347 16.46% 96.49% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6 1190 0.72% 97.20% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7 758 0.46% 97.66% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8 3890 2.34% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0 64563 40.55% 40.55% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1 48696 30.59% 71.14% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2 8235 5.17% 76.31% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3 3504 2.20% 78.51% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4 1064 0.67% 79.18% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5 27204 17.09% 96.26% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6 1240 0.78% 97.04% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7 753 0.47% 97.52% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8 3954 2.48% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total 166168 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate 0.287859 # Number of branch fetches per cycle
-system.cpu3.fetch.rate 1.557251 # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles 17558 # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles 68128 # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles 67891 # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles 4168 # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles 1363 # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts 246104 # Number of instructions handled by decode
-system.cpu3.rename.SquashCycles 1363 # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles 18233 # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles 33368 # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles 12463 # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles 69060 # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles 24621 # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts 242881 # Number of instructions processed by rename
-system.cpu3.rename.IQFullEvents 21589 # Number of times rename has blocked due to IQ full
+system.cpu3.fetch.rateDist::total 159213 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate 0.300283 # Number of branch fetches per cycle
+system.cpu3.fetch.rate 1.623619 # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles 17777 # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles 68157 # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles 67726 # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles 4161 # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles 1382 # Number of cycles decode is squashing
+system.cpu3.decode.DecodedInsts 245360 # Number of instructions handled by decode
+system.cpu3.rename.SquashCycles 1382 # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles 18479 # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles 33142 # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles 12841 # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles 69300 # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles 24059 # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts 241885 # Number of instructions processed by rename
+system.cpu3.rename.IQFullEvents 21460 # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full
system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers
-system.cpu3.rename.RenamedOperands 169259 # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups 456177 # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups 357242 # Number of integer rename lookups
-system.cpu3.rename.CommittedMaps 154687 # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps 14572 # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts 1184 # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts 1245 # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts 29195 # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads 65863 # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores 30140 # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads 31966 # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores 25009 # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded 199372 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded 7958 # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued 202308 # Number of instructions issued
+system.cpu3.rename.RenamedOperands 168616 # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups 454082 # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups 355646 # Number of integer rename lookups
+system.cpu3.rename.CommittedMaps 153987 # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps 14629 # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts 1214 # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts 1272 # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts 28919 # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads 65522 # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores 29976 # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads 31799 # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores 24828 # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded 198526 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded 7988 # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued 201423 # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued 33 # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined 12859 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined 11887 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved 683 # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples 166168 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean 1.217491 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev 1.364227 # Number of insts issued each cycle
+system.cpu3.iq.iqSquashedInstsExamined 12862 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined 11999 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved 692 # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples 159213 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean 1.265117 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev 1.367863 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0 75148 45.22% 45.22% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1 26256 15.80% 61.02% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2 29417 17.70% 78.73% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3 29010 17.46% 96.19% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4 3447 2.07% 98.26% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5 1582 0.95% 99.21% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6 873 0.53% 99.74% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7 228 0.14% 99.88% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8 207 0.12% 100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0 68514 43.03% 43.03% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1 26230 16.47% 59.51% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2 29303 18.40% 77.91% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3 28880 18.14% 96.05% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4 3418 2.15% 98.20% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5 1568 0.98% 99.18% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6 871 0.55% 99.73% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7 223 0.14% 99.87% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8 206 0.13% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total 166168 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total 159213 # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu 93 25.83% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.83% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead 58 16.11% 41.94% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite 209 58.06% 100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu 92 26.36% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead 48 13.75% 40.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite 209 59.89% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu 101290 50.07% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead 71575 35.38% 85.45% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite 29443 14.55% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu 100972 50.13% 50.13% # Type of FU issued
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+system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead 71204 35.35% 85.48% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite 29247 14.52% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total 202308 # Type of FU issued
-system.cpu3.iq.rate 1.209448 # Inst issue rate
-system.cpu3.iq.fu_busy_cnt 360 # FU busy when requested
-system.cpu3.iq.fu_busy_rate 0.001779 # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads 571177 # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes 220229 # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses 200600 # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.FU_type_0::total 201423 # Type of FU issued
+system.cpu3.iq.rate 1.256389 # Inst issue rate
+system.cpu3.iq.fu_busy_cnt 349 # FU busy when requested
+system.cpu3.iq.fu_busy_rate 0.001733 # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads 562441 # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes 219414 # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses 199715 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses 202668 # Number of integer alu accesses
+system.cpu3.iq.int_alu_accesses 201772 # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads 24749 # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.forwLoads 24567 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads 2800 # Number of loads squashed
+system.cpu3.iew.lsq.thread0.squashedLoads 2806 # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores 1627 # Number of stores squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores 1637 # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles 1363 # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles 8604 # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles 61 # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts 240098 # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts 201 # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts 65863 # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts 30140 # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts 1100 # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewSquashCycles 1382 # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles 8523 # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts 239131 # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts 178 # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts 65522 # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts 29976 # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts 1120 # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents 32 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents 40 # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect 473 # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect 1038 # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts 1511 # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts 201185 # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts 64698 # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts 1123 # Number of squashed instructions skipped in execute
+system.cpu3.iew.memOrderViolationEvents 38 # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect 471 # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect 1054 # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts 1525 # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts 200291 # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts 64311 # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts 1132 # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp 0 # number of swp insts executed
-system.cpu3.iew.exec_nop 32768 # number of nop insts executed
-system.cpu3.iew.exec_refs 94032 # number of memory reference insts executed
-system.cpu3.iew.exec_branches 42068 # Number of branches executed
-system.cpu3.iew.exec_stores 29334 # Number of stores executed
-system.cpu3.iew.exec_rate 1.202734 # Inst execution rate
-system.cpu3.iew.wb_sent 200904 # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count 200600 # cumulative count of insts written-back
-system.cpu3.iew.wb_producers 111689 # num instructions producing a value
-system.cpu3.iew.wb_consumers 118263 # num instructions consuming a value
+system.cpu3.iew.exec_nop 32617 # number of nop insts executed
+system.cpu3.iew.exec_refs 93457 # number of memory reference insts executed
+system.cpu3.iew.exec_branches 41928 # Number of branches executed
+system.cpu3.iew.exec_stores 29146 # Number of stores executed
+system.cpu3.iew.exec_rate 1.249328 # Inst execution rate
+system.cpu3.iew.wb_sent 200012 # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count 199715 # cumulative count of insts written-back
+system.cpu3.iew.wb_producers 111117 # num instructions producing a value
+system.cpu3.iew.wb_consumers 117670 # num instructions consuming a value
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate 1.199237 # insts written-back per cycle
-system.cpu3.iew.wb_fanout 0.944412 # average fanout of values written-back
+system.cpu3.iew.wb_rate 1.245735 # insts written-back per cycle
+system.cpu3.iew.wb_fanout 0.944310 # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitSquashedInsts 14520 # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls 7275 # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts 1287 # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples 156480 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean 1.441238 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev 1.976154 # Number of insts commited each cycle
+system.cpu3.commit.commitSquashedInsts 14558 # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls 7296 # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts 1305 # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples 156559 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean 1.434092 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev 1.973064 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0 74989 47.92% 47.92% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1 38816 24.81% 72.73% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2 5199 3.32% 76.05% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3 8093 5.17% 81.22% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4 1536 0.98% 82.20% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5 24757 15.82% 98.03% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6 830 0.53% 98.56% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7 957 0.61% 99.17% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8 1303 0.83% 100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0 75373 48.14% 48.14% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1 38673 24.70% 72.85% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2 5214 3.33% 76.18% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3 8076 5.16% 81.33% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4 1539 0.98% 82.32% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5 24642 15.74% 98.06% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6 775 0.50% 98.55% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7 961 0.61% 99.17% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8 1306 0.83% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total 156480 # Number of insts commited each cycle
-system.cpu3.commit.committedInsts 225525 # Number of instructions committed
-system.cpu3.commit.committedOps 225525 # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total 156559 # Number of insts commited each cycle
+system.cpu3.commit.committedInsts 224520 # Number of instructions committed
+system.cpu3.commit.committedOps 224520 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu3.commit.refs 91576 # Number of memory references committed
-system.cpu3.commit.loads 63063 # Number of loads committed
-system.cpu3.commit.membars 6559 # Number of memory barriers committed
-system.cpu3.commit.branches 41035 # Number of branches committed
+system.cpu3.commit.refs 91055 # Number of memory references committed
+system.cpu3.commit.loads 62716 # Number of loads committed
+system.cpu3.commit.membars 6575 # Number of memory barriers committed
+system.cpu3.commit.branches 40877 # Number of branches committed
system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu3.commit.int_insts 154730 # Number of committed integer instructions.
+system.cpu3.commit.int_insts 154046 # Number of committed integer instructions.
system.cpu3.commit.function_calls 322 # Number of function calls committed.
-system.cpu3.commit.op_class_0::No_OpClass 31823 14.11% 14.11% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu 95567 42.38% 56.49% # Class of committed instruction
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-system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.49% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.49% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.49% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.49% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.49% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.49% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.49% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.49% # Class of committed instruction
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-system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.49% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.49% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.49% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.49% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.49% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.49% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.49% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.49% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.49% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.49% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.49% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.49% # Class of committed instruction
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-system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.49% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead 69622 30.87% 87.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite 28513 12.64% 100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::No_OpClass 31660 14.10% 14.10% # Class of committed instruction
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system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
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-system.cpu3.commit.op_class_0::total 225525 # Class of committed instruction
-system.cpu3.commit.bw_lim_events 1303 # number cycles where commit BW limit reached
+system.cpu3.commit.op_class_0::total 224520 # Class of committed instruction
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system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu3.rob.rob_reads 394635 # The number of ROB reads
-system.cpu3.rob.rob_writes 482728 # The number of ROB writes
-system.cpu3.timesIdled 203 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles 1105 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles 44004 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts 187143 # Number of Instructions Simulated
-system.cpu3.committedOps 187143 # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi 0.893825 # CPI: Cycles Per Instruction
-system.cpu3.cpi_total 0.893825 # CPI: Total CPI of All Threads
-system.cpu3.ipc 1.118788 # IPC: Instructions Per Cycle
-system.cpu3.ipc_total 1.118788 # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads 341840 # number of integer regfile reads
-system.cpu3.int_regfile_writes 160726 # number of integer regfile writes
+system.cpu3.rob.rob_reads 393745 # The number of ROB reads
+system.cpu3.rob.rob_writes 480811 # The number of ROB writes
+system.cpu3.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles 1106 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles 44020 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts 186285 # Number of Instructions Simulated
+system.cpu3.committedOps 186285 # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi 0.860611 # CPI: Cycles Per Instruction
+system.cpu3.cpi_total 0.860611 # CPI: Total CPI of All Threads
+system.cpu3.ipc 1.161965 # IPC: Instructions Per Cycle
+system.cpu3.ipc_total 1.161965 # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads 340113 # number of integer regfile reads
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system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu3.misc_regfile_reads 95629 # number of misc regfile reads
+system.cpu3.misc_regfile_reads 95078 # number of misc regfile reads
system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
-system.cpu3.icache.tags.replacements 380 # number of replacements
-system.cpu3.icache.tags.tagsinuse 77.789470 # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs 24352 # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs 493 # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs 49.395538 # Average number of references to valid blocks.
+system.cpu3.icache.tags.replacements 386 # number of replacements
+system.cpu3.icache.tags.tagsinuse 77.771025 # Cycle average of tags in use
+system.cpu3.icache.tags.total_refs 24411 # Total number of references to valid blocks.
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+system.cpu3.icache.tags.avg_refs 48.919840 # Average number of references to valid blocks.
system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.789470 # Average occupied blocks per requestor
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-system.cpu3.icache.tags.occ_percent::total 0.151933 # Average percentage of cache occupancy
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system.cpu3.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id
system.cpu3.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id
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-system.cpu3.icache.ReadReq_hits::total 24352 # number of ReadReq hits
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-system.cpu3.icache.overall_misses::total 555 # number of overall misses
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-system.cpu3.icache.ReadReq_miss_latency::total 7324995 # number of ReadReq miss cycles
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-system.cpu3.icache.demand_miss_latency::total 7324995 # number of demand (read+write) miss cycles
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-system.cpu3.icache.ReadReq_accesses::cpu3.inst 24907 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total 24907 # number of ReadReq accesses(hits+misses)
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-system.cpu3.icache.overall_miss_rate::total 0.022283 # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13198.189189 # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 13198.189189 # average ReadReq miss latency
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-system.cpu3.icache.demand_avg_miss_latency::total 13198.189189 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13198.189189 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 13198.189189 # average overall miss latency
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+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13192.508021 # average overall miss latency
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system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits
system.cpu3.icache.overall_mshr_hits::cpu3.inst 62 # number of overall MSHR hits
system.cpu3.icache.overall_mshr_hits::total 62 # number of overall MSHR hits
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-system.cpu3.icache.demand_mshr_misses::total 493 # number of demand (read+write) MSHR misses
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-system.cpu3.icache.overall_mshr_misses::total 493 # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5824754 # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total 5824754 # number of ReadReq MSHR miss cycles
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-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.019794 # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.019794 # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.019794 # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total 0.019794 # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.019794 # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total 0.019794 # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11814.916836 # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11814.916836 # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11814.916836 # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 11814.916836 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11814.916836 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 11814.916836 # average overall mshr miss latency
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+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12538.718447 # average WriteReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 6782.129032 # average SwapReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 6782.129032 # average SwapReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9221.237918 # average overall mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9221.237918 # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9221.237918 # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9221.237918 # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 87707000 # Number of ticks simulated
final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1618143 # Simulator instruction rate (inst/s)
-host_op_rate 1618081 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 209518099 # Simulator tick rate (ticks/s)
-host_mem_usage 283888 # Number of bytes of host memory used
-host_seconds 0.42 # Real time elapsed on the host
-sim_insts 677327 # Number of instructions simulated
-sim_ops 677327 # Number of ops (including micro ops) simulated
+host_inst_rate 1398636 # Simulator instruction rate (inst/s)
+host_op_rate 1398593 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 181097192 # Simulator tick rate (ticks/s)
+host_mem_usage 299844 # Number of bytes of host memory used
+host_seconds 0.48 # Real time elapsed on the host
+sim_insts 677333 # Number of instructions simulated
+sim_ops 677333 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
system.physmem.bytes_read::total 35776 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::total 559 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 1459405 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 2189107 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 1459405 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 729702 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 1459405 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 1459405 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 2189107 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 729702 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 1459405 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 2189107 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 1459405 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 729702 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 407903588 # Throughput (bytes/s)
-system.membus.data_through_bus 35776 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 423 # Transaction distribution
+system.membus.trans_dist::ReadResp 423 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 273 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 80 # Transaction distribution
+system.membus.trans_dist::ReadExReq 412 # Transaction distribution
+system.membus.trans_dist::ReadExResp 136 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1747 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1747 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 1108 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 1108 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 1108 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.l2c.tags.replacements 0 # number of replacements
-system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use
+system.l2c.tags.tagsinuse 366.582953 # Cycle average of tags in use
system.l2c.tags.total_refs 1220 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 55.207589 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 6.721185 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data 0.935416 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data 0.905646 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy
system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.006424 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 15488 # Number of tag accesses
-system.l2c.tags.data_accesses 15488 # Number of data accesses
+system.l2c.tags.tag_accesses 15456 # Number of tag accesses
+system.l2c.tags.data_accesses 15456 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits
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system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
system.l2c.demand_hits::total 1220 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 185 # number of overall hits
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
system.l2c.overall_hits::cpu1.inst 296 # number of overall hits
system.l2c.overall_hits::cpu1.data 3 # number of overall hits
-system.l2c.overall_hits::cpu2.inst 356 # number of overall hits
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system.l2c.overall_hits::cpu2.data 9 # number of overall hits
-system.l2c.overall_hits::cpu3.inst 357 # number of overall hits
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system.l2c.overall_hits::cpu3.data 9 # number of overall hits
system.l2c.overall_hits::total 1220 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst 3 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.inst 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
system.l2c.ReadReq_misses::total 423 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst 3 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
system.l2c.demand_misses::total 559 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 282 # number of overall misses
system.l2c.overall_misses::cpu0.data 165 # number of overall misses
system.l2c.overall_misses::cpu1.inst 62 # number of overall misses
system.l2c.overall_misses::cpu1.data 20 # number of overall misses
-system.l2c.overall_misses::cpu2.inst 2 # number of overall misses
+system.l2c.overall_misses::cpu2.inst 3 # number of overall misses
system.l2c.overall_misses::cpu2.data 13 # number of overall misses
-system.l2c.overall_misses::cpu3.inst 2 # number of overall misses
+system.l2c.overall_misses::cpu3.inst 1 # number of overall misses
system.l2c.overall_misses::cpu3.data 13 # number of overall misses
system.l2c.overall_misses::total 559 # number of overall misses
system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst 0.008380 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses
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system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses
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system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses
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system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses
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system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses
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system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses
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system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.toL2Bus.throughput 1893577480 # Throughput (bytes/s)
-system.toL2Bus.data_through_bus 166080 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.toL2Bus.trans_dist::ReadReq 2179 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution
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+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes)
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+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 5733 # Packet count per connected master and slave (bytes)
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+system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes)
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+system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 22976 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 165888 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 0 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 2867 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
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+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 2867 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
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+system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 2867 # Request fanout histogram
system.cpu0.workload.num_syscalls 89 # Number of system calls
system.cpu0.numCycles 175415 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 175388 # Class of executed instruction
system.cpu0.icache.tags.replacements 215 # number of replacements
-system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use
+system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor
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system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 2 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use
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system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks.
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system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor
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system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id
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system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu0.dcache.writebacks::total 1 # number of writebacks
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 167398 # Number of instructions committed
-system.cpu1.committedOps 167398 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses
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system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 633 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 32743 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 109926 # number of integer instructions
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system.cpu1.num_fp_insts 0 # number of float instructions
-system.cpu1.num_int_register_reads 270038 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 100721 # number of times the integer registers were written
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+system.cpu1.num_int_register_writes 94218 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
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-system.cpu1.num_load_insts 40652 # Number of load instructions
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-system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles
-system.cpu1.Branches 34390 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 25177 15.04% 15.04% # Class of executed instruction
-system.cpu1.op_class::IntAlu 73170 43.70% 58.74% # Class of executed instruction
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system.cpu1.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction
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-system.cpu1.op_class::MemWrite 12742 7.61% 100.00% # Class of executed instruction
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system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 167430 # Class of executed instruction
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system.cpu1.icache.tags.replacements 278 # number of replacements
-system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks.
+system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use
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system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks.
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system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor
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system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id
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system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses
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system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses
system.cpu1.icache.cache_copies 0 # number of cache copies performed
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system.cpu1.dcache.tags.replacements 0 # number of replacements
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system.cpu2.dcache.fast_writes 0 # number of fast writes performed
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system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
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+system.cpu3.num_busy_cycles 165297.717505 # Number of busy cycles
+system.cpu3.not_idle_fraction 0.953841 # Percentage of non-idle cycles
+system.cpu3.idle_fraction 0.046159 # Percentage of idle cycles
+system.cpu3.Branches 32639 # Number of branches fetched
+system.cpu3.op_class::No_OpClass 23433 14.01% 14.01% # Class of executed instruction
+system.cpu3.op_class::IntAlu 74851 44.74% 58.75% # Class of executed instruction
system.cpu3.op_class::IntMult 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::IntDiv 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::FloatAdd 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdFloatMult 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.75% # Class of executed instruction
-system.cpu3.op_class::MemRead 54586 32.63% 91.37% # Class of executed instruction
-system.cpu3.op_class::MemWrite 14434 8.63% 100.00% # Class of executed instruction
+system.cpu3.op_class::MemRead 52854 31.59% 90.34% # Class of executed instruction
+system.cpu3.op_class::MemWrite 16166 9.66% 100.00% # Class of executed instruction
system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu3.op_class::total 167301 # Class of executed instruction
+system.cpu3.op_class::total 167304 # Class of executed instruction
system.cpu3.icache.tags.replacements 279 # number of replacements
-system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks.
+system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use
+system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks.
system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks.
+system.cpu3.icache.tags.avg_refs 465.027855 # Average number of references to valid blocks.
system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874953 # Average occupied blocks per requestor
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+system.cpu3.icache.tags.occ_percent::total 0.142334 # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id
system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses 167660 # Number of tag accesses
-system.cpu3.icache.tags.data_accesses 167660 # Number of data accesses
-system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total 166942 # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst 166942 # number of overall hits
-system.cpu3.icache.overall_hits::total 166942 # number of overall hits
+system.cpu3.icache.tags.tag_accesses 167663 # Number of tag accesses
+system.cpu3.icache.tags.data_accesses 167663 # Number of data accesses
+system.cpu3.icache.ReadReq_hits::cpu3.inst 166945 # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total 166945 # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst 166945 # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total 166945 # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst 166945 # number of overall hits
+system.cpu3.icache.overall_hits::total 166945 # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses
system.cpu3.icache.overall_misses::total 359 # number of overall misses
-system.cpu3.icache.ReadReq_accesses::cpu3.inst 167301 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total 167301 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst 167301 # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total 167301 # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst 167301 # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_accesses::cpu3.inst 167304 # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total 167304 # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst 167304 # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total 167304 # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst 167304 # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total 167304 # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses
system.cpu3.icache.cache_copies 0 # number of cache copies performed
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dcache.tags.replacements 0 # number of replacements
-system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks.
+system.cpu3.dcache.tags.tagsinuse 28.848199 # Cycle average of tags in use
+system.cpu3.dcache.tags.total_refs 33595 # Total number of references to valid blocks.
+system.cpu3.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
+system.cpu3.dcache.tags.avg_refs 1292.115385 # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
+system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.848199 # Average occupied blocks per requestor
+system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056344 # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_percent::total 0.056344 # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
-system.cpu3.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses 223805 # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses 223805 # Number of data accesses
-system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits
-system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data 55561 # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total 55561 # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data 55561 # number of overall hits
-system.cpu3.dcache.overall_hits::total 55561 # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data 102 # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total 102 # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses
-system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses
-system.cpu3.dcache.demand_misses::cpu3.data 259 # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total 259 # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data 259 # number of overall misses
-system.cpu3.dcache.overall_misses::total 259 # number of overall misses
-system.cpu3.dcache.ReadReq_accesses::cpu3.data 41458 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total 41458 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data 14362 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total 14362 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data 55820 # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003787 # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total 0.003787 # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total 0.007102 # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004640 # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total 0.004640 # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004640 # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total 0.004640 # miss rate for overall accesses
+system.cpu3.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id
+system.cpu3.dcache.tags.tag_accesses 234241 # Number of tag accesses
+system.cpu3.dcache.tags.data_accesses 234241 # Number of data accesses
+system.cpu3.dcache.ReadReq_hits::cpu3.data 42185 # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total 42185 # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits::cpu3.data 15991 # number of WriteReq hits
+system.cpu3.dcache.WriteReq_hits::total 15991 # number of WriteReq hits
+system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits
+system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits
+system.cpu3.dcache.demand_hits::cpu3.data 58176 # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total 58176 # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data 58176 # number of overall hits
+system.cpu3.dcache.overall_hits::total 58176 # number of overall hits
+system.cpu3.dcache.ReadReq_misses::cpu3.data 151 # number of ReadReq misses
+system.cpu3.dcache.ReadReq_misses::total 151 # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses
+system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses
+system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses
+system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses
+system.cpu3.dcache.demand_misses::cpu3.data 260 # number of demand (read+write) misses
+system.cpu3.dcache.demand_misses::total 260 # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses::cpu3.data 260 # number of overall misses
+system.cpu3.dcache.overall_misses::total 260 # number of overall misses
+system.cpu3.dcache.ReadReq_accesses::cpu3.data 42336 # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total 42336 # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::cpu3.data 16100 # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::total 16100 # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses::cpu3.data 58436 # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total 58436 # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data 58436 # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total 58436 # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003567 # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_miss_rate::total 0.003567 # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006770 # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::total 0.006770 # miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses
+system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004449 # miss rate for demand accesses
+system.cpu3.dcache.demand_miss_rate::total 0.004449 # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004449 # miss rate for overall accesses
+system.cpu3.dcache.overall_miss_rate::total 0.004449 # miss rate for overall accesses
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
---------- Begin Simulation Statistics ----------
sim_seconds 0.000263 # Number of seconds simulated
-sim_ticks 262794500 # Number of ticks simulated
-final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 262793500 # Number of ticks simulated
+final_tick 262793500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 985745 # Simulator instruction rate (inst/s)
-host_op_rate 985721 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 390370221 # Simulator tick rate (ticks/s)
-host_mem_usage 283880 # Number of bytes of host memory used
-host_seconds 0.67 # Real time elapsed on the host
+host_inst_rate 1021127 # Simulator instruction rate (inst/s)
+host_op_rate 1021105 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 404381057 # Simulator tick rate (ticks/s)
+host_mem_usage 299844 # Number of bytes of host memory used
+host_seconds 0.65 # Real time elapsed on the host
sim_insts 663567 # Number of instructions simulated
sim_ops 663567 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory
system.physmem.num_reads::total 572 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 69407845 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 40183489 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 14368642 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 5357799 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 487073 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 3653044 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 1948290 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 3896581 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 139302763 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 69407845 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 14368642 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 487073 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 1948290 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 86211850 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 69407845 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 40183489 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 14368642 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 5357799 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 487073 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 3653044 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 1948290 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 3896581 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 139302763 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 139302763 # Throughput (bytes/s)
+system.physmem.bw_read::cpu0.inst 69408109 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 40183642 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 14368696 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 5357819 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 487074 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 3653058 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 1948298 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 3896596 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 139303293 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 69408109 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 14368696 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 487074 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 1948298 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 86212178 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 69408109 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 40183642 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 14368696 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 5357819 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 487074 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 3653058 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 1948298 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 3896596 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 139303293 # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq 430 # Transaction distribution
system.membus.trans_dist::ReadResp 430 # Transaction distribution
system.membus.trans_dist::UpgradeReq 272 # Transaction distribution
system.membus.trans_dist::ReadExResp 142 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 36608 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 852296 # Layer occupancy (ticks)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 261 # Total snoops (count)
+system.membus.snoop_fanout::samples 915 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 915 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 915 # Request fanout histogram
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system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
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system.cpu1.dcache.tags.replacements 0 # number of replacements
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system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency
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system.cpu2.op_class::No_OpClass 22386 13.58% 13.58% # Class of executed instruction
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system.cpu2.op_class::total 164898 # Class of executed instruction
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system.cpu2.icache.ReadReq_accesses::cpu2.inst 164899 # number of ReadReq accesses(hits+misses)
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-system.cpu2.icache.ReadReq_avg_miss_latency::total 14351.060109 # average ReadReq miss latency
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system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for ReadReq accesses
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system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dcache.tags.replacements 0 # number of replacements
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system.cpu2.dcache.tags.total_refs 36347 # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
system.cpu2.dcache.tags.avg_refs 1253.344828 # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu3.committedInsts 176656 # Number of instructions committed
system.cpu3.num_mem_refs 46164 # number of memory refs
system.cpu3.num_load_insts 39753 # Number of load instructions
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system.cpu3.Branches 39890 # Number of branches fetched
system.cpu3.op_class::No_OpClass 30652 17.35% 17.35% # Class of executed instruction
system.cpu3.op_class::IntAlu 73353 41.52% 58.86% # Class of executed instruction
system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu3.op_class::total 176688 # Class of executed instruction
system.cpu3.icache.tags.replacements 281 # number of replacements
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system.cpu3.icache.tags.total_refs 176322 # Total number of references to valid blocks.
system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks.
system.cpu3.icache.tags.avg_refs 480.441417 # Average number of references to valid blocks.
system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu3.icache.tags.occ_percent::total 0.128122 # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
system.cpu3.icache.overall_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dcache.tags.replacements 0 # number of replacements
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system.cpu3.dcache.tags.total_refs 15020 # Total number of references to valid blocks.
system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
system.cpu3.dcache.tags.avg_refs 517.931034 # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
system.cpu3.dcache.overall_misses::total 288 # number of overall misses
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system.cpu3.dcache.ReadReq_miss_latency::total 3156473 # number of ReadReq miss cycles
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system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 280000 # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total 280000 # number of SwapReq miss cycles
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system.cpu3.dcache.ReadReq_accesses::cpu3.data 39746 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total 39746 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data 6321 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.overall_miss_rate::total 0.006252 # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17248.486339 # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total 17248.486339 # average ReadReq miss latency
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system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4057.971014 # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total 4057.971014 # average SwapReq miss latency
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system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.overall_mshr_misses::total 288 # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2772527 # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2772527 # number of ReadReq MSHR miss cycles
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system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 142000 # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total 142000 # number of SwapReq MSHR miss cycles
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system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004604 # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004604 # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.016611 # mshr miss rate for WriteReq accesses
system.cpu3.dcache.overall_mshr_miss_rate::total 0.006252 # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15150.420765 # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15150.420765 # average ReadReq mshr miss latency
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system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2057.971014 # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2057.971014 # average SwapReq mshr miss latency
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system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 7430292 # Number of ticks simulated
final_tick 7430292 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 111636 # Simulator tick rate (ticks/s)
-host_mem_usage 267664 # Number of bytes of host memory used
-host_seconds 66.56 # Real time elapsed on the host
+host_tick_rate 73095 # Simulator tick rate (ticks/s)
+host_mem_usage 318168 # Number of bytes of host memory used
+host_seconds 101.65 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.network.msg_byte.Response_Control 51426416
system.ruby.network.msg_byte.Writeback_Data 111484296
system.ruby.network.msg_byte.Writeback_Control 4869144
-system.funcbus.throughput 0 # Throughput (bytes/s)
-system.funcbus.data_through_bus 0 # Total data (bytes)
system.cpu0.num_reads 99258 # number of read accesses completed
system.cpu0.num_writes 54534 # number of write accesses completed
system.cpu0.num_copies 0 # number of copy accesses completed
sim_ticks 7645897 # Number of ticks simulated
final_tick 7645897 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 53519 # Simulator tick rate (ticks/s)
-host_mem_usage 294536 # Number of bytes of host memory used
-host_seconds 142.86 # Real time elapsed on the host
+host_tick_rate 46164 # Simulator tick rate (ticks/s)
+host_mem_usage 322852 # Number of bytes of host memory used
+host_seconds 165.63 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.cpu_clk_domain.clock 1 # Clock period in ticks
system.ruby.l1_cntrl5.L1Dcache.demand_hits 27 # Number of cache demand hits
system.ruby.l1_cntrl5.L1Dcache.demand_misses 78996 # Number of cache demand misses
system.ruby.l1_cntrl5.L1Dcache.demand_accesses 79023 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl1.L1Dcache.demand_hits 9 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses 78940 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78949 # Number of cache demand accesses
-system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl2.L1Dcache.demand_hits 26 # Number of cache demand hits
-system.ruby.l1_cntrl2.L1Dcache.demand_misses 79113 # Number of cache demand misses
-system.ruby.l1_cntrl2.L1Dcache.demand_accesses 79139 # Number of cache demand accesses
-system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl3.L1Dcache.demand_hits 24 # Number of cache demand hits
-system.ruby.l1_cntrl3.L1Dcache.demand_misses 78765 # Number of cache demand misses
-system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78789 # Number of cache demand accesses
-system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l2_cntrl0.L2cache.demand_hits 6149 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 625832 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 631981 # Number of cache demand accesses
system.ruby.network.routers00.percent_links_utilized 5.698442
system.ruby.network.routers00.msg_count.Request_Control::0 79077
system.ruby.network.routers00.msg_count.Response_Data::2 77245
system.ruby.network.routers00.msg_bytes.Forwarded_Control::0 8736
system.ruby.network.routers00.msg_bytes.Invalidate_Control::0 24
system.ruby.network.routers00.msg_bytes.Unblock_Control::2 640168
+system.ruby.l1_cntrl1.L1Dcache.demand_hits 9 # Number of cache demand hits
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system.ruby.network.routers01.percent_links_utilized 5.685628
system.ruby.network.routers01.msg_count.Request_Control::0 78939
system.ruby.network.routers01.msg_count.Response_Data::2 77083
system.ruby.network.routers01.msg_bytes.Forwarded_Control::0 8496
system.ruby.network.routers01.msg_bytes.Invalidate_Control::0 8
system.ruby.network.routers01.msg_bytes.Unblock_Control::2 639464
+system.ruby.l1_cntrl2.L1Dcache.demand_hits 26 # Number of cache demand hits
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system.ruby.network.routers02.percent_links_utilized 5.700427
system.ruby.network.routers02.msg_count.Request_Control::0 79113
system.ruby.network.routers02.msg_count.Response_Data::2 77289
system.ruby.network.routers02.msg_bytes.Forwarded_Control::0 8720
system.ruby.network.routers02.msg_bytes.Invalidate_Control::0 8
system.ruby.network.routers02.msg_bytes.Unblock_Control::2 640512
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system.ruby.network.routers03.percent_links_utilized 5.674514
system.ruby.network.routers03.msg_count.Request_Control::0 78765
system.ruby.network.routers03.msg_count.Response_Data::2 76945
system.ruby.network.routers07.msg_bytes.Writeback_Control::0 1259488
system.ruby.network.routers07.msg_bytes.Forwarded_Control::0 8512
system.ruby.network.routers07.msg_bytes.Unblock_Control::2 637968
+system.ruby.l2_cntrl0.L2cache.demand_hits 6149 # Number of cache demand hits
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system.ruby.network.routers08.percent_links_utilized 79.115289
system.ruby.network.routers08.msg_count.Request_Control::0 631981
system.ruby.network.routers08.msg_count.Request_Control::1 617280
system.ruby.network.msg_byte.Forwarded_Control 205248
system.ruby.network.msg_byte.Invalidate_Control 264
system.ruby.network.msg_byte.Unblock_Control 30168336
-system.funcbus.throughput 0 # Throughput (bytes/s)
-system.funcbus.data_through_bus 0 # Total data (bytes)
-system.cpu_clk_domain.clock 1 # Clock period in ticks
system.cpu0.num_reads 99316 # number of read accesses completed
system.cpu0.num_writes 55500 # number of write accesses completed
system.cpu0.num_copies 0 # number of copy accesses completed
sim_ticks 6284915 # Number of ticks simulated
final_tick 6284915 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 64396 # Simulator tick rate (ticks/s)
-host_mem_usage 293488 # Number of bytes of host memory used
-host_seconds 97.60 # Real time elapsed on the host
+host_tick_rate 51541 # Simulator tick rate (ticks/s)
+host_mem_usage 318988 # Number of bytes of host memory used
+host_seconds 121.94 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.cpu_clk_domain.clock 1 # Clock period in ticks
system.ruby.l1_cntrl5.L1Dcache.demand_hits 26 # Number of cache demand hits
system.ruby.l1_cntrl5.L1Dcache.demand_misses 78593 # Number of cache demand misses
system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78619 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses
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-system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses
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-system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses
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system.ruby.network.routers00.percent_links_utilized 9.881597
system.ruby.network.routers00.msg_count.Request_Control::1 78371
system.ruby.network.routers00.msg_count.Response_Data::4 78092
system.ruby.network.routers00.msg_bytes.Writeback_Data::4 6183216
system.ruby.network.routers00.msg_bytes.Broadcast_Control::1 5024408
system.ruby.network.routers00.msg_bytes.Persistent_Control::3 2375752
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system.ruby.network.routers01.percent_links_utilized 9.921833
system.ruby.network.routers01.msg_count.Request_Control::1 78895
system.ruby.network.routers01.msg_count.Response_Data::4 78610
system.ruby.network.routers01.msg_bytes.Writeback_Control::4 16
system.ruby.network.routers01.msg_bytes.Broadcast_Control::1 5024408
system.ruby.network.routers01.msg_bytes.Persistent_Control::3 2378952
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system.ruby.network.routers02.percent_links_utilized 9.878833
system.ruby.network.routers02.msg_count.Request_Control::1 78341
system.ruby.network.routers02.msg_count.Response_Data::4 77980
system.ruby.network.routers02.msg_bytes.Writeback_Data::4 6178320
system.ruby.network.routers02.msg_bytes.Broadcast_Control::1 5024408
system.ruby.network.routers02.msg_bytes.Persistent_Control::3 2378600
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system.ruby.network.routers03.percent_links_utilized 9.881140
system.ruby.network.routers03.msg_count.Request_Control::1 78389
system.ruby.network.routers03.msg_count.Response_Data::4 78013
system.ruby.network.routers07.msg_bytes.Writeback_Data::4 6183144
system.ruby.network.routers07.msg_bytes.Broadcast_Control::1 5024408
system.ruby.network.routers07.msg_bytes.Persistent_Control::3 2376760
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system.ruby.network.routers08.percent_links_utilized 38.794550
system.ruby.network.routers08.msg_count.Request_Control::1 628051
system.ruby.network.routers08.msg_count.Request_Control::2 626511
system.ruby.network.msg_byte.Writeback_Control 9144888
system.ruby.network.msg_byte.Broadcast_Control 75366120
system.ruby.network.msg_byte.Persistent_Control 42271680
-system.funcbus.throughput 0 # Throughput (bytes/s)
-system.funcbus.data_through_bus 0 # Total data (bytes)
-system.cpu_clk_domain.clock 1 # Clock period in ticks
system.cpu0.num_reads 100000 # number of read accesses completed
system.cpu0.num_writes 55570 # number of write accesses completed
system.cpu0.num_copies 0 # number of copy accesses completed
sim_ticks 5920895 # Number of ticks simulated
final_tick 5920895 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 58624 # Simulator tick rate (ticks/s)
-host_mem_usage 293400 # Number of bytes of host memory used
-host_seconds 101.00 # Real time elapsed on the host
+host_tick_rate 46540 # Simulator tick rate (ticks/s)
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system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.l1_cntrl4.L2cache.demand_hits 77 # Number of cache demand hits
system.ruby.l1_cntrl4.L2cache.demand_misses 78569 # Number of cache demand misses
system.ruby.l1_cntrl4.L2cache.demand_accesses 78646 # Number of cache demand accesses
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system.ruby.l1_cntrl5.L1Dcache.demand_hits 19 # Number of cache demand hits
system.ruby.l1_cntrl5.L1Dcache.demand_misses 78666 # Number of cache demand misses
system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78685 # Number of cache demand accesses
system.ruby.l1_cntrl0.L2cache.demand_hits 80 # Number of cache demand hits
system.ruby.l1_cntrl0.L2cache.demand_misses 78315 # Number of cache demand misses
system.ruby.l1_cntrl0.L2cache.demand_accesses 78395 # Number of cache demand accesses
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-system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses
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system.ruby.network.routers0.percent_links_utilized 12.539882
system.ruby.network.routers0.msg_count.Request_Control::2 78315
system.ruby.network.routers0.msg_count.Request_Control::3 59
system.ruby.network.routers0.msg_bytes.Writeback_Control::5 370520
system.ruby.network.routers0.msg_bytes.Broadcast_Control::3 4397184
system.ruby.network.routers0.msg_bytes.Unblock_Control::5 626624
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system.ruby.network.routers1.percent_links_utilized 12.590850
system.ruby.network.routers1.msg_count.Request_Control::2 78828
system.ruby.network.routers1.msg_count.Request_Control::3 53
system.ruby.network.routers1.msg_bytes.Writeback_Control::5 370728
system.ruby.network.routers1.msg_bytes.Broadcast_Control::3 4392992
system.ruby.network.routers1.msg_bytes.Unblock_Control::5 630808
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system.ruby.network.routers2.percent_links_utilized 12.557548
system.ruby.network.routers2.msg_count.Request_Control::2 78545
system.ruby.network.routers2.msg_count.Request_Control::3 51
system.ruby.network.routers2.msg_bytes.Writeback_Control::5 371048
system.ruby.network.routers2.msg_bytes.Broadcast_Control::3 4395248
system.ruby.network.routers2.msg_bytes.Unblock_Control::5 628504
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system.ruby.network.routers3.percent_links_utilized 12.569726
system.ruby.network.routers3.msg_count.Request_Control::2 78639
system.ruby.network.routers3.msg_count.Request_Control::3 54
system.ruby.network.msg_byte.Writeback_Control 37367352
system.ruby.network.msg_byte.Broadcast_Control 75348720
system.ruby.network.msg_byte.Unblock_Control 15084048
-system.funcbus.throughput 0 # Throughput (bytes/s)
-system.funcbus.data_through_bus 0 # Total data (bytes)
-system.cpu_clk_domain.clock 1 # Clock period in ticks
system.cpu0.num_reads 99506 # number of read accesses completed
system.cpu0.num_writes 55459 # number of write accesses completed
system.cpu0.num_copies 0 # number of copy accesses completed
sim_ticks 8851106 # Number of ticks simulated
final_tick 8851106 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 251677 # Simulator tick rate (ticks/s)
-host_mem_usage 263028 # Number of bytes of host memory used
-host_seconds 35.17 # Real time elapsed on the host
+host_tick_rate 185635 # Simulator tick rate (ticks/s)
+host_mem_usage 317472 # Number of bytes of host memory used
+host_seconds 47.68 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.l1_cntrl4.cacheMemory.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl4.cacheMemory.demand_misses 78801 # Number of cache demand misses
system.ruby.l1_cntrl4.cacheMemory.demand_accesses 78801 # Number of cache demand accesses
+system.cpu_clk_domain.clock 1 # Clock period in ticks
system.ruby.l1_cntrl5.cacheMemory.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl5.cacheMemory.demand_misses 78712 # Number of cache demand misses
system.ruby.l1_cntrl5.cacheMemory.demand_accesses 78712 # Number of cache demand accesses
system.ruby.l1_cntrl0.cacheMemory.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 78906 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 78906 # Number of cache demand accesses
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-system.ruby.l1_cntrl3.cacheMemory.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl3.cacheMemory.demand_misses 79057 # Number of cache demand misses
-system.ruby.l1_cntrl3.cacheMemory.demand_accesses 79057 # Number of cache demand accesses
system.ruby.network.routers0.percent_links_utilized 4.466411
system.ruby.network.routers0.msg_count.Control::2 78906
system.ruby.network.routers0.msg_count.Data::2 78209
system.ruby.network.routers0.msg_bytes.Data::2 5631048
system.ruby.network.routers0.msg_bytes.Response_Data::4 5754384
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 633776
+system.ruby.l1_cntrl1.cacheMemory.demand_hits 0 # Number of cache demand hits
+system.ruby.l1_cntrl1.cacheMemory.demand_misses 78862 # Number of cache demand misses
+system.ruby.l1_cntrl1.cacheMemory.demand_accesses 78862 # Number of cache demand accesses
system.ruby.network.routers1.percent_links_utilized 4.464072
system.ruby.network.routers1.msg_count.Control::2 78862
system.ruby.network.routers1.msg_count.Data::2 78116
system.ruby.network.routers1.msg_bytes.Data::2 5624352
system.ruby.network.routers1.msg_bytes.Response_Data::4 5755104
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 633480
+system.ruby.l1_cntrl2.cacheMemory.demand_hits 0 # Number of cache demand hits
+system.ruby.l1_cntrl2.cacheMemory.demand_misses 78717 # Number of cache demand misses
+system.ruby.l1_cntrl2.cacheMemory.demand_accesses 78717 # Number of cache demand accesses
system.ruby.network.routers2.percent_links_utilized 4.456923
system.ruby.network.routers2.msg_count.Control::2 78717
system.ruby.network.routers2.msg_count.Data::2 78011
system.ruby.network.routers2.msg_bytes.Data::2 5616792
system.ruby.network.routers2.msg_bytes.Response_Data::4 5744448
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 632608
+system.ruby.l1_cntrl3.cacheMemory.demand_hits 0 # Number of cache demand hits
+system.ruby.l1_cntrl3.cacheMemory.demand_misses 79057 # Number of cache demand misses
+system.ruby.l1_cntrl3.cacheMemory.demand_accesses 79057 # Number of cache demand accesses
system.ruby.network.routers3.percent_links_utilized 4.475147
system.ruby.network.routers3.msg_count.Control::2 79057
system.ruby.network.routers3.msg_count.Data::2 78335
system.ruby.network.msg_byte.Data 135010584
system.ruby.network.msg_byte.Response_Data 136263888
system.ruby.network.msg_byte.Writeback_Control 15204144
-system.funcbus.throughput 0 # Throughput (bytes/s)
-system.funcbus.data_through_bus 0 # Total data (bytes)
-system.cpu_clk_domain.clock 1 # Clock period in ticks
system.cpu0.num_reads 99672 # number of read accesses completed
system.cpu0.num_writes 55456 # number of write accesses completed
system.cpu0.num_copies 0 # number of copy accesses completed
---------- Begin Simulation Statistics ----------
-sim_seconds 0.001466 # Number of seconds simulated
-sim_ticks 1466014000 # Number of ticks simulated
-final_tick 1466014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.001487 # Number of seconds simulated
+sim_ticks 1486654500 # Number of ticks simulated
+final_tick 1486654500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 362824283 # Simulator tick rate (ticks/s)
-host_mem_usage 344492 # Number of bytes of host memory used
-host_seconds 4.04 # Real time elapsed on the host
+host_tick_rate 296727534 # Simulator tick rate (ticks/s)
+host_mem_usage 404724 # Number of bytes of host memory used
+host_seconds 5.01 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0 81024 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 82440 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 87271 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 81468 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 83154 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 83511 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 83243 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 81362 # Number of bytes read from this memory
-system.physmem.bytes_read::total 663473 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 418112 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5482 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5323 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5338 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5333 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5428 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5332 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5280 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5327 # Number of bytes written to this memory
-system.physmem.bytes_written::total 460955 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 11094 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 11124 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 11230 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 10971 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 11082 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 11061 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 11171 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 11117 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 88850 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 6533 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5482 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5323 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5338 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5333 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5428 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5332 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5280 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5327 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 49376 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 55268231 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 56234115 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 59529445 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 55571093 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 56721150 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 56964667 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 56781859 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 55498788 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 452569348 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 285203279 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 3739391 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 3630934 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 3641166 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 3637755 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 3702557 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 3637073 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 3601603 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 3633662 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 314427420 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 285203279 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 59007622 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 59865049 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 63170611 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 59208848 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 60423707 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 60601741 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 60383462 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 59132450 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 766996768 # Total bandwidth to/from this memory (bytes/s)
-system.membus.snoop_filter.tot_requests 121068 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 119020 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.physmem.bytes_read::cpu0 76776 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1 78761 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2 77348 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3 78011 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4 77583 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5 76150 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6 79121 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7 75007 # Number of bytes read from this memory
+system.physmem.bytes_read::total 618757 # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks 383744 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0 5329 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1 5414 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2 5336 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3 5424 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4 5535 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5 5438 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6 5327 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7 5496 # Number of bytes written to this memory
+system.physmem.bytes_written::total 427043 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0 11067 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1 10847 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2 10757 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3 10790 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4 11118 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5 10756 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6 10829 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7 10873 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 87037 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 5996 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0 5329 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1 5414 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2 5336 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3 5424 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4 5535 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5 5438 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6 5327 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7 5496 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 49295 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0 51643472 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1 52978685 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2 52028228 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3 52474196 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4 52186302 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5 51222392 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6 53220839 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7 50453552 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 416207666 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 258125879 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0 3584558 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1 3641734 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2 3589267 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3 3648460 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4 3723125 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5 3657877 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6 3583213 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7 3696891 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 287251006 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 258125879 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0 55228030 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1 56620419 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2 55617496 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3 56122657 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4 55909426 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5 54880270 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6 56804052 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7 54150443 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 703458672 # Total bandwidth to/from this memory (bytes/s)
+system.membus.snoop_filter.tot_requests 122188 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 120140 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.throughput 766995404 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 85646 # Transaction distribution
-system.membus.trans_dist::ReadResp 85644 # Transaction distribution
-system.membus.trans_dist::WriteReq 42843 # Transaction distribution
-system.membus.trans_dist::WriteResp 42842 # Transaction distribution
-system.membus.trans_dist::Writeback 6533 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 57248 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 46699 # Transaction distribution
-system.membus.trans_dist::ReadExReq 48957 # Transaction distribution
-system.membus.trans_dist::ReadExResp 3204 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 419616 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 419616 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 1124426 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 1124426 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 1124426 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.snoops_through_bus 56301 # Total snoops (count)
-system.membus.snoop_fanout::samples 121068 # Request fanout histogram
+system.membus.trans_dist::ReadReq 84101 # Transaction distribution
+system.membus.trans_dist::ReadResp 84098 # Transaction distribution
+system.membus.trans_dist::WriteReq 43299 # Transaction distribution
+system.membus.trans_dist::WriteResp 43298 # Transaction distribution
+system.membus.trans_dist::Writeback 5996 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 58155 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 47311 # Transaction distribution
+system.membus.trans_dist::ReadExReq 50200 # Transaction distribution
+system.membus.trans_dist::ReadExResp 2936 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 419394 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 419394 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1045797 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1045797 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 58108 # Total snoops (count)
+system.membus.snoop_fanout::samples 122188 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 121068 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 122188 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 121068 # Request fanout histogram
-system.membus.reqLayer0.occupancy 476149500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 32.5 # Layer utilization (%)
-system.membus.respLayer0.occupancy 322630500 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 22.0 # Layer utilization (%)
+system.membus.snoop_fanout::total 122188 # Request fanout histogram
+system.membus.reqLayer0.occupancy 471309000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 31.7 # Layer utilization (%)
+system.membus.respLayer0.occupancy 318465500 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 21.4 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 13552 # number of replacements
-system.l2c.tags.tagsinuse 786.290427 # Cycle average of tags in use
-system.l2c.tags.total_refs 149902 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 14350 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 10.446132 # Average number of references to valid blocks.
+system.l2c.tags.replacements 12651 # number of replacements
+system.l2c.tags.tagsinuse 779.272325 # Cycle average of tags in use
+system.l2c.tags.total_refs 149024 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 13435 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 11.092222 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 730.775276 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0 6.840177 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1 7.161871 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2 6.892698 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3 6.763865 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4 6.714219 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5 6.973391 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6 7.262671 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7 6.906259 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.713648 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0 0.006680 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1 0.006994 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2 0.006731 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3 0.006605 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu4 0.006557 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu5 0.006810 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu6 0.007092 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu7 0.006744 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.767862 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 368 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 428 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 1950254 # Number of tag accesses
-system.l2c.tags.data_accesses 1950254 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0 10780 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1 10796 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2 10830 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3 10794 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu4 10743 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu5 10804 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu6 10680 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu7 10909 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 86336 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 74514 # number of Writeback hits
-system.l2c.Writeback_hits::total 74514 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0 330 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1 332 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2 379 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3 363 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4 357 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5 362 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6 317 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7 363 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 2803 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0 1848 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1 1871 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2 1840 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3 1858 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu4 1858 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu5 1893 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu6 1894 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu7 1826 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 14888 # number of ReadExReq hits
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-system.l2c.demand_hits::cpu2 12670 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3 12652 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu4 12601 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu5 12697 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu6 12574 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu7 12735 # number of demand (read+write) hits
-system.l2c.demand_hits::total 101224 # number of demand (read+write) hits
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-system.l2c.overall_hits::cpu6 12574 # number of overall hits
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-system.l2c.ReadReq_misses::cpu5 753 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu6 747 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu7 720 # number of ReadReq misses
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-system.l2c.UpgradeReq_misses::cpu1 1885 # number of UpgradeReq misses
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-system.l2c.UpgradeReq_misses::cpu3 1905 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu4 1913 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu5 1875 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu6 1933 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu7 1894 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 15189 # number of UpgradeReq misses
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-system.l2c.Writeback_accesses::total 74514 # number of Writeback accesses(hits+misses)
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-system.l2c.overall_accesses::total 141890 # number of overall (read+write) accesses
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-system.l2c.UpgradeReq_miss_rate::cpu1 0.850248 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2 0.832152 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3 0.839947 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu4 0.842731 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu5 0.838176 # miss rate for UpgradeReq accesses
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-system.l2c.UpgradeReq_miss_rate::cpu7 0.839167 # miss rate for UpgradeReq accesses
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-system.l2c.UpgradeReq_avg_miss_latency::cpu3 29231.758530 # average UpgradeReq miss latency
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-system.l2c.UpgradeReq_avg_miss_latency::cpu5 29077.333333 # average UpgradeReq miss latency
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-system.l2c.UpgradeReq_avg_miss_latency::cpu7 29435.322070 # average UpgradeReq miss latency
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-system.l2c.ReadExReq_avg_miss_latency::cpu7 53490.951276 # average ReadExReq miss latency
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-system.l2c.overall_avg_miss_latency::total 54228.470959 # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs 6449 # number of cycles access was blocked
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+system.l2c.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id
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+system.l2c.UpgradeReq_hits::cpu7 353 # number of UpgradeReq hits
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+system.l2c.ReadReq_accesses::cpu7 11192 # number of ReadReq accesses(hits+misses)
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+system.l2c.UpgradeReq_accesses::cpu0 2288 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1 2264 # number of UpgradeReq accesses(hits+misses)
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+system.l2c.UpgradeReq_accesses::total 18320 # number of UpgradeReq accesses(hits+misses)
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+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41280.249090 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41318.512880 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41193.634757 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41207.717467 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41281.085847 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41208.584867 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41098.819188 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 41216.112269 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 41917.037378 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1 42071.248094 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2 41950.912108 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3 41974.667593 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu4 42032.092843 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu5 41958.847281 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu6 41985.195533 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu7 41870.388000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 41970.441418 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0 41917.037378 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 42071.248094 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2 41950.912108 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 41974.667593 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 42032.092843 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu5 41958.847281 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 41985.195533 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu7 41870.388000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 41970.441418 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.funcbus.throughput 0 # Throughput (bytes/s)
-system.funcbus.data_through_bus 0 # Total data (bytes)
-system.toL2Bus.snoop_filter.tot_requests 548567 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 252509 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 294010 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_requests 556652 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 259205 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 295399 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.throughput 22759385654 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 368934 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 368931 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 42843 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 42841 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 74514 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 28540 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 28540 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 155707 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 155704 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 118962 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 119173 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 119464 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 119154 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 118978 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 119360 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 119013 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 118881 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 952985 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1734762 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1749843 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1754305 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1751569 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1739334 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1759819 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1742411 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1740191 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 13972234 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 13972234 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 19393344 # Total snoop data (bytes)
-system.toL2Bus.snoops_through_bus 313569 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 548567 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.700997 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 1.184770 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 369106 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 369100 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 43299 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 43298 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 74943 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 29164 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 29164 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 161428 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 161427 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120001 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 119693 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 119622 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120026 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120574 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 119580 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 119572 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 119681 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 958749 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1736824 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1745103 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1743099 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1764010 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1727854 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1727156 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1741472 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1730998 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 13916516 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 322180 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 556652 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.686233 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 1.173674 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 51420 9.37% 9.37% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 243442 44.38% 53.75% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 138727 25.29% 79.04% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 68606 12.51% 91.55% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 30441 5.55% 97.10% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 11622 2.12% 99.21% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 3640 0.66% 99.88% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 669 0.12% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 52178 9.37% 9.37% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 250105 44.93% 54.30% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 140101 25.17% 79.47% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 69083 12.41% 91.88% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 29746 5.34% 97.23% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 11224 2.02% 99.24% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 3520 0.63% 99.88% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 695 0.12% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 548567 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 1466016000 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 100.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 156116317 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 10.6 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 156768205 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 556652 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 1484170768 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 99.8 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 158821901 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 10.7 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 158474081 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 10.7 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 156913339 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 158663989 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 10.7 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 156965244 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 158858134 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 10.7 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 156103724 # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization 10.6 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 156986709 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.occupancy 159553082 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization 10.7 # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy 158926155 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 10.7 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 156696078 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy 158642094 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 10.7 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 156271715 # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization 10.7 # Layer utilization (%)
-system.cpu0.num_reads 99418 # number of read accesses completed
-system.cpu0.num_writes 53245 # number of write accesses completed
+system.toL2Bus.respLayer7.occupancy 158326604 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization 10.6 # Layer utilization (%)
+system.cpu0.num_reads 99884 # number of read accesses completed
+system.cpu0.num_writes 54722 # number of write accesses completed
system.cpu0.num_copies 0 # number of copy accesses completed
-system.cpu0.l1c.tags.replacements 22099 # number of replacements
-system.cpu0.l1c.tags.tagsinuse 397.065512 # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs 13209 # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs 22488 # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs 0.587380 # Average number of references to valid blocks.
+system.cpu0.l1c.tags.replacements 22159 # number of replacements
+system.cpu0.l1c.tags.tagsinuse 396.508288 # Cycle average of tags in use
+system.cpu0.l1c.tags.total_refs 13572 # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs 22560 # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs 0.601596 # Average number of references to valid blocks.
system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0 397.065512 # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0 0.775519 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total 0.775519 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::0 259 # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id
-system.cpu0.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id
-system.cpu0.l1c.tags.tag_accesses 330123 # Number of tag accesses
-system.cpu0.l1c.tags.data_accesses 330123 # Number of data accesses
-system.cpu0.l1c.ReadReq_hits::cpu0 8700 # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total 8700 # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0 1042 # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total 1042 # number of WriteReq hits
-system.cpu0.l1c.demand_hits::cpu0 9742 # number of demand (read+write) hits
-system.cpu0.l1c.demand_hits::total 9742 # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0 9742 # number of overall hits
-system.cpu0.l1c.overall_hits::total 9742 # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0 35979 # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total 35979 # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0 22956 # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total 22956 # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0 58935 # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total 58935 # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0 58935 # number of overall misses
-system.cpu0.l1c.overall_misses::total 58935 # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0 2431275055 # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total 2431275055 # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0 1798190271 # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total 1798190271 # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency::cpu0 4229465326 # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_latency::total 4229465326 # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency::cpu0 4229465326 # number of overall miss cycles
-system.cpu0.l1c.overall_miss_latency::total 4229465326 # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0 44679 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total 44679 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0 23998 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total 23998 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses::cpu0 68677 # number of demand (read+write) accesses
-system.cpu0.l1c.demand_accesses::total 68677 # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses::cpu0 68677 # number of overall (read+write) accesses
-system.cpu0.l1c.overall_accesses::total 68677 # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805278 # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total 0.805278 # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956580 # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total 0.956580 # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0 0.858148 # miss rate for demand accesses
-system.cpu0.l1c.demand_miss_rate::total 0.858148 # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate::cpu0 0.858148 # miss rate for overall accesses
-system.cpu0.l1c.overall_miss_rate::total 0.858148 # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 67574.836849 # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 67574.836849 # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 78332.038291 # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 78332.038291 # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 71764.916026 # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 71764.916026 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 71764.916026 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 71764.916026 # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs 2152877 # number of cycles access was blocked
+system.cpu0.l1c.tags.occ_blocks::cpu0 396.508288 # Average occupied blocks per requestor
+system.cpu0.l1c.tags.occ_percent::cpu0 0.774430 # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_percent::total 0.774430 # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::0 266 # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id
+system.cpu0.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id
+system.cpu0.l1c.tags.tag_accesses 336605 # Number of tag accesses
+system.cpu0.l1c.tags.data_accesses 336605 # Number of data accesses
+system.cpu0.l1c.ReadReq_hits::cpu0 8851 # number of ReadReq hits
+system.cpu0.l1c.ReadReq_hits::total 8851 # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits::cpu0 1088 # number of WriteReq hits
+system.cpu0.l1c.WriteReq_hits::total 1088 # number of WriteReq hits
+system.cpu0.l1c.demand_hits::cpu0 9939 # number of demand (read+write) hits
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+system.cpu0.l1c.ReadReq_miss_rate::total 0.804190 # miss rate for ReadReq accesses
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+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 67770.226596 # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_miss_latency::total 67770.226596 # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 78333.765540 # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::total 78333.765540 # average WriteReq miss latency
+system.cpu0.l1c.demand_avg_miss_latency::cpu0 71945.769730 # average overall miss latency
+system.cpu0.l1c.demand_avg_miss_latency::total 71945.769730 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 71945.769730 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::total 71945.769730 # average overall miss latency
+system.cpu0.l1c.blocked_cycles::no_mshrs 2211784 # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs 58943 # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs 60234 # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs 36.524727 # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs 36.719859 # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks 9551 # number of writebacks
-system.cpu0.l1c.writebacks::total 9551 # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35979 # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total 35979 # number of ReadReq MSHR misses
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-system.cpu0.l1c.WriteReq_mshr_misses::total 22956 # number of WriteReq MSHR misses
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-system.cpu0.l1c.demand_mshr_misses::total 58935 # number of demand (read+write) MSHR misses
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-system.cpu0.l1c.overall_mshr_misses::total 58935 # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 2355407447 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total 2355407447 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1750135961 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1750135961 # number of WriteReq MSHR miss cycles
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-system.cpu0.l1c.demand_mshr_miss_latency::total 4105543408 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0 4105543408 # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total 4105543408 # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 1091154570 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 1091154570 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 4041529643 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 4041529643 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 5132684213 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total 5132684213 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805278 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805278 # mshr miss rate for ReadReq accesses
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-system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956580 # mshr miss rate for WriteReq accesses
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-system.cpu0.l1c.demand_mshr_miss_rate::total 0.858148 # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858148 # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total 0.858148 # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 65466.173240 # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 65466.173240 # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 76238.715848 # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 76238.715848 # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 69662.228014 # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 69662.228014 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 69662.228014 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 69662.228014 # average overall mshr miss latency
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+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 65657.241589 # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 76236.380413 # average WriteReq mshr miss latency
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+system.cpu0.l1c.overall_avg_mshr_miss_latency::total 69838.951025 # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.num_reads 99768 # number of read accesses completed
-system.cpu1.num_writes 53422 # number of write accesses completed
+system.cpu1.num_reads 99113 # number of read accesses completed
+system.cpu1.num_writes 54702 # number of write accesses completed
system.cpu1.num_copies 0 # number of copy accesses completed
-system.cpu1.l1c.tags.replacements 22481 # number of replacements
-system.cpu1.l1c.tags.tagsinuse 398.933743 # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs 13300 # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs 22873 # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs 0.581472 # Average number of references to valid blocks.
+system.cpu1.l1c.tags.replacements 22065 # number of replacements
+system.cpu1.l1c.tags.tagsinuse 395.289903 # Cycle average of tags in use
+system.cpu1.l1c.tags.total_refs 13538 # Total number of references to valid blocks.
+system.cpu1.l1c.tags.sampled_refs 22464 # Sample count of references to valid blocks.
+system.cpu1.l1c.tags.avg_refs 0.602653 # Average number of references to valid blocks.
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1 398.933743 # Average occupied blocks per requestor
-system.cpu1.l1c.tags.occ_percent::cpu1 0.779167 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_percent::total 0.779167 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_task_id_blocks::1024 392 # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::0 265 # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
-system.cpu1.l1c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id
-system.cpu1.l1c.tags.tag_accesses 331866 # Number of tag accesses
-system.cpu1.l1c.tags.data_accesses 331866 # Number of data accesses
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-system.cpu1.l1c.ReadReq_hits::total 8705 # number of ReadReq hits
-system.cpu1.l1c.WriteReq_hits::cpu1 1116 # number of WriteReq hits
-system.cpu1.l1c.WriteReq_hits::total 1116 # number of WriteReq hits
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-system.cpu1.l1c.overall_hits::total 9821 # number of overall hits
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-system.cpu1.l1c.ReadReq_misses::total 36262 # number of ReadReq misses
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-system.cpu1.l1c.WriteReq_misses::total 22965 # number of WriteReq misses
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-system.cpu1.l1c.overall_misses::total 59227 # number of overall misses
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-system.cpu1.l1c.ReadReq_miss_latency::total 2445520804 # number of ReadReq miss cycles
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-system.cpu1.l1c.overall_miss_latency::total 4245633844 # number of overall miss cycles
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-system.cpu1.l1c.WriteReq_accesses::total 24081 # number of WriteReq accesses(hits+misses)
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-system.cpu1.l1c.overall_accesses::total 69048 # number of overall (read+write) accesses
-system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.806414 # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_miss_rate::total 0.806414 # miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953656 # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::total 0.953656 # miss rate for WriteReq accesses
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-system.cpu1.l1c.demand_miss_rate::total 0.857766 # miss rate for demand accesses
-system.cpu1.l1c.overall_miss_rate::cpu1 0.857766 # miss rate for overall accesses
-system.cpu1.l1c.overall_miss_rate::total 0.857766 # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 67440.317798 # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 67440.317798 # average ReadReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 78385.065970 # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::total 78385.065970 # average WriteReq miss latency
-system.cpu1.l1c.demand_avg_miss_latency::cpu1 71684.094146 # average overall miss latency
-system.cpu1.l1c.demand_avg_miss_latency::total 71684.094146 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 71684.094146 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 71684.094146 # average overall miss latency
-system.cpu1.l1c.blocked_cycles::no_mshrs 2169051 # number of cycles access was blocked
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+system.cpu1.l1c.tags.occ_percent::total 0.772051 # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
+system.cpu1.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id
+system.cpu1.l1c.tags.tag_accesses 336364 # Number of tag accesses
+system.cpu1.l1c.tags.data_accesses 336364 # Number of data accesses
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+system.cpu1.l1c.ReadReq_hits::total 8820 # number of ReadReq hits
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+system.cpu1.l1c.WriteReq_hits::total 1137 # number of WriteReq hits
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+system.cpu1.l1c.ReadReq_misses::total 36159 # number of ReadReq misses
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+system.cpu1.l1c.WriteReq_misses::total 23877 # number of WriteReq misses
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+system.cpu1.l1c.demand_misses::total 60036 # number of demand (read+write) misses
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+system.cpu1.l1c.overall_misses::total 60036 # number of overall misses
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+system.cpu1.l1c.ReadReq_miss_latency::total 2464134844 # number of ReadReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::cpu1 1871949720 # number of WriteReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::total 1871949720 # number of WriteReq miss cycles
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+system.cpu1.l1c.demand_miss_latency::total 4336084564 # number of demand (read+write) miss cycles
+system.cpu1.l1c.overall_miss_latency::cpu1 4336084564 # number of overall miss cycles
+system.cpu1.l1c.overall_miss_latency::total 4336084564 # number of overall miss cycles
+system.cpu1.l1c.ReadReq_accesses::cpu1 44979 # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_accesses::total 44979 # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::cpu1 25014 # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::total 25014 # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.demand_accesses::cpu1 69993 # number of demand (read+write) accesses
+system.cpu1.l1c.demand_accesses::total 69993 # number of demand (read+write) accesses
+system.cpu1.l1c.overall_accesses::cpu1 69993 # number of overall (read+write) accesses
+system.cpu1.l1c.overall_accesses::total 69993 # number of overall (read+write) accesses
+system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.803908 # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_miss_rate::total 0.803908 # miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954545 # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::total 0.954545 # miss rate for WriteReq accesses
+system.cpu1.l1c.demand_miss_rate::cpu1 0.857743 # miss rate for demand accesses
+system.cpu1.l1c.demand_miss_rate::total 0.857743 # miss rate for demand accesses
+system.cpu1.l1c.overall_miss_rate::cpu1 0.857743 # miss rate for overall accesses
+system.cpu1.l1c.overall_miss_rate::total 0.857743 # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 68147.206615 # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 68147.206615 # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 78399.703480 # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::total 78399.703480 # average WriteReq miss latency
+system.cpu1.l1c.demand_avg_miss_latency::cpu1 72224.741222 # average overall miss latency
+system.cpu1.l1c.demand_avg_miss_latency::total 72224.741222 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 72224.741222 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 72224.741222 # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs 2199257 # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs 59314 # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs 59892 # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs 36.568955 # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs 36.720380 # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks 9774 # number of writebacks
-system.cpu1.l1c.writebacks::total 9774 # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36262 # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total 36262 # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22965 # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total 22965 # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1 59227 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total 59227 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1 59227 # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total 59227 # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 2368901584 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total 2368901584 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1752103572 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1752103572 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1 4121005156 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total 4121005156 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1 4121005156 # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total 4121005156 # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1095385986 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1095385986 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 3917382799 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 3917382799 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 5012768785 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total 5012768785 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.806414 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.806414 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953656 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953656 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857766 # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_miss_rate::total 0.857766 # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857766 # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total 0.857766 # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 65327.383597 # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 65327.383597 # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 76294.516525 # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 76294.516525 # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 69579.839533 # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 69579.839533 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 69579.839533 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 69579.839533 # average overall mshr miss latency
+system.cpu1.l1c.writebacks::writebacks 9710 # number of writebacks
+system.cpu1.l1c.writebacks::total 9710 # number of writebacks
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+system.cpu1.l1c.ReadReq_mshr_misses::total 36159 # number of ReadReq MSHR misses
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+system.cpu1.l1c.WriteReq_mshr_misses::total 23877 # number of WriteReq MSHR misses
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+system.cpu1.l1c.demand_mshr_misses::total 60036 # number of demand (read+write) MSHR misses
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+system.cpu1.l1c.ReadReq_mshr_miss_latency::total 2387770588 # number of ReadReq MSHR miss cycles
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+system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1821987516 # number of WriteReq MSHR miss cycles
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+system.cpu1.l1c.overall_mshr_miss_latency::total 4209758104 # number of overall MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1078285196 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1078285196 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 4031598145 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 4031598145 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 5109883341 # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::total 5109883341 # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.803908 # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.803908 # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954545 # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954545 # mshr miss rate for WriteReq accesses
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+system.cpu1.l1c.demand_mshr_miss_rate::total 0.857743 # mshr miss rate for demand accesses
+system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857743 # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_miss_rate::total 0.857743 # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 66035.304848 # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 66035.304848 # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 76307.221008 # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 76307.221008 # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 70120.562729 # average overall mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::total 70120.562729 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 70120.562729 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::total 70120.562729 # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.num_reads 100000 # number of read accesses completed
-system.cpu2.num_writes 53603 # number of write accesses completed
+system.cpu2.num_reads 98176 # number of read accesses completed
+system.cpu2.num_writes 54646 # number of write accesses completed
system.cpu2.num_copies 0 # number of copy accesses completed
-system.cpu2.l1c.tags.replacements 22539 # number of replacements
-system.cpu2.l1c.tags.tagsinuse 397.267456 # Cycle average of tags in use
-system.cpu2.l1c.tags.total_refs 13362 # Total number of references to valid blocks.
-system.cpu2.l1c.tags.sampled_refs 22949 # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs 0.582248 # Average number of references to valid blocks.
+system.cpu2.l1c.tags.replacements 22558 # number of replacements
+system.cpu2.l1c.tags.tagsinuse 395.943086 # Cycle average of tags in use
+system.cpu2.l1c.tags.total_refs 13415 # Total number of references to valid blocks.
+system.cpu2.l1c.tags.sampled_refs 22958 # Sample count of references to valid blocks.
+system.cpu2.l1c.tags.avg_refs 0.584328 # Average number of references to valid blocks.
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.tags.occ_blocks::cpu2 397.267456 # Average occupied blocks per requestor
-system.cpu2.l1c.tags.occ_percent::cpu2 0.775913 # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_percent::total 0.775913 # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::0 285 # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
-system.cpu2.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id
-system.cpu2.l1c.tags.tag_accesses 332293 # Number of tag accesses
-system.cpu2.l1c.tags.data_accesses 332293 # Number of data accesses
-system.cpu2.l1c.ReadReq_hits::cpu2 8761 # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total 8761 # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2 1062 # number of WriteReq hits
-system.cpu2.l1c.WriteReq_hits::total 1062 # number of WriteReq hits
-system.cpu2.l1c.demand_hits::cpu2 9823 # number of demand (read+write) hits
-system.cpu2.l1c.demand_hits::total 9823 # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits::cpu2 9823 # number of overall hits
-system.cpu2.l1c.overall_hits::total 9823 # number of overall hits
-system.cpu2.l1c.ReadReq_misses::cpu2 36321 # number of ReadReq misses
-system.cpu2.l1c.ReadReq_misses::total 36321 # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses::cpu2 22996 # number of WriteReq misses
-system.cpu2.l1c.WriteReq_misses::total 22996 # number of WriteReq misses
-system.cpu2.l1c.demand_misses::cpu2 59317 # number of demand (read+write) misses
-system.cpu2.l1c.demand_misses::total 59317 # number of demand (read+write) misses
-system.cpu2.l1c.overall_misses::cpu2 59317 # number of overall misses
-system.cpu2.l1c.overall_misses::total 59317 # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency::cpu2 2442264018 # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_latency::total 2442264018 # number of ReadReq miss cycles
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-system.cpu2.l1c.WriteReq_miss_latency::total 1799405026 # number of WriteReq miss cycles
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-system.cpu2.l1c.demand_miss_latency::total 4241669044 # number of demand (read+write) miss cycles
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-system.cpu2.l1c.overall_miss_latency::total 4241669044 # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2 45082 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_accesses::total 45082 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::cpu2 24058 # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::total 24058 # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.demand_accesses::cpu2 69140 # number of demand (read+write) accesses
-system.cpu2.l1c.demand_accesses::total 69140 # number of demand (read+write) accesses
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-system.cpu2.l1c.overall_accesses::total 69140 # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805665 # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_miss_rate::total 0.805665 # miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955857 # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::total 0.955857 # miss rate for WriteReq accesses
-system.cpu2.l1c.demand_miss_rate::cpu2 0.857926 # miss rate for demand accesses
-system.cpu2.l1c.demand_miss_rate::total 0.857926 # miss rate for demand accesses
-system.cpu2.l1c.overall_miss_rate::cpu2 0.857926 # miss rate for overall accesses
-system.cpu2.l1c.overall_miss_rate::total 0.857926 # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 67241.100686 # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 67241.100686 # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 78248.609584 # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 78248.609584 # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency::cpu2 71508.489033 # average overall miss latency
-system.cpu2.l1c.demand_avg_miss_latency::total 71508.489033 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 71508.489033 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 71508.489033 # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs 2171204 # number of cycles access was blocked
+system.cpu2.l1c.tags.occ_blocks::cpu2 395.943086 # Average occupied blocks per requestor
+system.cpu2.l1c.tags.occ_percent::cpu2 0.773326 # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_percent::total 0.773326 # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::0 274 # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id
+system.cpu2.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id
+system.cpu2.l1c.tags.tag_accesses 336254 # Number of tag accesses
+system.cpu2.l1c.tags.data_accesses 336254 # Number of data accesses
+system.cpu2.l1c.ReadReq_hits::cpu2 8574 # number of ReadReq hits
+system.cpu2.l1c.ReadReq_hits::total 8574 # number of ReadReq hits
+system.cpu2.l1c.WriteReq_hits::cpu2 1152 # number of WriteReq hits
+system.cpu2.l1c.WriteReq_hits::total 1152 # number of WriteReq hits
+system.cpu2.l1c.demand_hits::cpu2 9726 # number of demand (read+write) hits
+system.cpu2.l1c.demand_hits::total 9726 # number of demand (read+write) hits
+system.cpu2.l1c.overall_hits::cpu2 9726 # number of overall hits
+system.cpu2.l1c.overall_hits::total 9726 # number of overall hits
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+system.cpu2.l1c.ReadReq_misses::total 36359 # number of ReadReq misses
+system.cpu2.l1c.WriteReq_misses::cpu2 23860 # number of WriteReq misses
+system.cpu2.l1c.WriteReq_misses::total 23860 # number of WriteReq misses
+system.cpu2.l1c.demand_misses::cpu2 60219 # number of demand (read+write) misses
+system.cpu2.l1c.demand_misses::total 60219 # number of demand (read+write) misses
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+system.cpu2.l1c.overall_misses::total 60219 # number of overall misses
+system.cpu2.l1c.ReadReq_miss_latency::cpu2 2471651596 # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_latency::total 2471651596 # number of ReadReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::cpu2 1874289110 # number of WriteReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::total 1874289110 # number of WriteReq miss cycles
+system.cpu2.l1c.demand_miss_latency::cpu2 4345940706 # number of demand (read+write) miss cycles
+system.cpu2.l1c.demand_miss_latency::total 4345940706 # number of demand (read+write) miss cycles
+system.cpu2.l1c.overall_miss_latency::cpu2 4345940706 # number of overall miss cycles
+system.cpu2.l1c.overall_miss_latency::total 4345940706 # number of overall miss cycles
+system.cpu2.l1c.ReadReq_accesses::cpu2 44933 # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_accesses::total 44933 # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::cpu2 25012 # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::total 25012 # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.demand_accesses::cpu2 69945 # number of demand (read+write) accesses
+system.cpu2.l1c.demand_accesses::total 69945 # number of demand (read+write) accesses
+system.cpu2.l1c.overall_accesses::cpu2 69945 # number of overall (read+write) accesses
+system.cpu2.l1c.overall_accesses::total 69945 # number of overall (read+write) accesses
+system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.809183 # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_miss_rate::total 0.809183 # miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953942 # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::total 0.953942 # miss rate for WriteReq accesses
+system.cpu2.l1c.demand_miss_rate::cpu2 0.860948 # miss rate for demand accesses
+system.cpu2.l1c.demand_miss_rate::total 0.860948 # miss rate for demand accesses
+system.cpu2.l1c.overall_miss_rate::cpu2 0.860948 # miss rate for overall accesses
+system.cpu2.l1c.overall_miss_rate::total 0.860948 # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 67979.086223 # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_miss_latency::total 67979.086223 # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 78553.608969 # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::total 78553.608969 # average WriteReq miss latency
+system.cpu2.l1c.demand_avg_miss_latency::cpu2 72168.928511 # average overall miss latency
+system.cpu2.l1c.demand_avg_miss_latency::total 72168.928511 # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::cpu2 72168.928511 # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::total 72168.928511 # average overall miss latency
+system.cpu2.l1c.blocked_cycles::no_mshrs 2198300 # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs 59435 # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_mshrs 59965 # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs 36.530731 # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs 36.659718 # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks 9704 # number of writebacks
-system.cpu2.l1c.writebacks::total 9704 # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36321 # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total 36321 # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22996 # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total 22996 # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses::cpu2 59317 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.demand_mshr_misses::total 59317 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2 59317 # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total 59317 # number of overall MSHR misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 2365672458 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_latency::total 2365672458 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1751310602 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1751310602 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::cpu2 4116983060 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::total 4116983060 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2 4116983060 # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total 4116983060 # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1097675449 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1097675449 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 3894001300 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 3894001300 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 4991676749 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total 4991676749 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805665 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805665 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955857 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955857 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.857926 # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_miss_rate::total 0.857926 # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.857926 # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total 0.857926 # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 65132.360287 # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 65132.360287 # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 76157.183945 # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 76157.183945 # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 69406.461217 # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 69406.461217 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 69406.461217 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 69406.461217 # average overall mshr miss latency
+system.cpu2.l1c.writebacks::writebacks 9891 # number of writebacks
+system.cpu2.l1c.writebacks::total 9891 # number of writebacks
+system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36359 # number of ReadReq MSHR misses
+system.cpu2.l1c.ReadReq_mshr_misses::total 36359 # number of ReadReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23860 # number of WriteReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::total 23860 # number of WriteReq MSHR misses
+system.cpu2.l1c.demand_mshr_misses::cpu2 60219 # number of demand (read+write) MSHR misses
+system.cpu2.l1c.demand_mshr_misses::total 60219 # number of demand (read+write) MSHR misses
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+system.cpu2.l1c.overall_mshr_misses::total 60219 # number of overall MSHR misses
+system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 2394908316 # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_miss_latency::total 2394908316 # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1824229170 # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1824229170 # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::cpu2 4219137486 # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::total 4219137486 # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::cpu2 4219137486 # number of overall MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::total 4219137486 # number of overall MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1069659636 # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1069659636 # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 3964277301 # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 3964277301 # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 5033936937 # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::total 5033936937 # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.809183 # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.809183 # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953942 # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953942 # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.860948 # mshr miss rate for demand accesses
+system.cpu2.l1c.demand_mshr_miss_rate::total 0.860948 # mshr miss rate for demand accesses
+system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.860948 # mshr miss rate for overall accesses
+system.cpu2.l1c.overall_mshr_miss_rate::total 0.860948 # mshr miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 65868.376908 # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 65868.376908 # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 76455.539396 # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 76455.539396 # average WriteReq mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 70063.227320 # average overall mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::total 70063.227320 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 70063.227320 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 70063.227320 # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.num_reads 99664 # number of read accesses completed
-system.cpu3.num_writes 53618 # number of write accesses completed
+system.cpu3.num_reads 98913 # number of read accesses completed
+system.cpu3.num_writes 55212 # number of write accesses completed
system.cpu3.num_copies 0 # number of copy accesses completed
-system.cpu3.l1c.tags.replacements 22539 # number of replacements
-system.cpu3.l1c.tags.tagsinuse 397.521626 # Cycle average of tags in use
-system.cpu3.l1c.tags.total_refs 13272 # Total number of references to valid blocks.
-system.cpu3.l1c.tags.sampled_refs 22952 # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs 0.578250 # Average number of references to valid blocks.
+system.cpu3.l1c.tags.replacements 22225 # number of replacements
+system.cpu3.l1c.tags.tagsinuse 393.873430 # Cycle average of tags in use
+system.cpu3.l1c.tags.total_refs 13306 # Total number of references to valid blocks.
+system.cpu3.l1c.tags.sampled_refs 22621 # Sample count of references to valid blocks.
+system.cpu3.l1c.tags.avg_refs 0.588214 # Average number of references to valid blocks.
system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.tags.occ_blocks::cpu3 397.521626 # Average occupied blocks per requestor
-system.cpu3.l1c.tags.occ_percent::cpu3 0.776409 # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_percent::total 0.776409 # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_task_id_blocks::1024 413 # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::0 263 # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id
-system.cpu3.l1c.tags.occ_task_id_percent::1024 0.806641 # Percentage of cache occupancy per task id
-system.cpu3.l1c.tags.tag_accesses 332331 # Number of tag accesses
-system.cpu3.l1c.tags.data_accesses 332331 # Number of data accesses
-system.cpu3.l1c.ReadReq_hits::cpu3 8701 # number of ReadReq hits
-system.cpu3.l1c.ReadReq_hits::total 8701 # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits::cpu3 1040 # number of WriteReq hits
-system.cpu3.l1c.WriteReq_hits::total 1040 # number of WriteReq hits
-system.cpu3.l1c.demand_hits::cpu3 9741 # number of demand (read+write) hits
-system.cpu3.l1c.demand_hits::total 9741 # number of demand (read+write) hits
-system.cpu3.l1c.overall_hits::cpu3 9741 # number of overall hits
-system.cpu3.l1c.overall_hits::total 9741 # number of overall hits
-system.cpu3.l1c.ReadReq_misses::cpu3 36310 # number of ReadReq misses
-system.cpu3.l1c.ReadReq_misses::total 36310 # number of ReadReq misses
-system.cpu3.l1c.WriteReq_misses::cpu3 23079 # number of WriteReq misses
-system.cpu3.l1c.WriteReq_misses::total 23079 # number of WriteReq misses
-system.cpu3.l1c.demand_misses::cpu3 59389 # number of demand (read+write) misses
-system.cpu3.l1c.demand_misses::total 59389 # number of demand (read+write) misses
-system.cpu3.l1c.overall_misses::cpu3 59389 # number of overall misses
-system.cpu3.l1c.overall_misses::total 59389 # number of overall misses
-system.cpu3.l1c.ReadReq_miss_latency::cpu3 2444229866 # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_latency::total 2444229866 # number of ReadReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::cpu3 1811981579 # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::total 1811981579 # number of WriteReq miss cycles
-system.cpu3.l1c.demand_miss_latency::cpu3 4256211445 # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_latency::total 4256211445 # number of demand (read+write) miss cycles
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-system.cpu3.l1c.overall_miss_latency::total 4256211445 # number of overall miss cycles
-system.cpu3.l1c.ReadReq_accesses::cpu3 45011 # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_accesses::total 45011 # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::cpu3 24119 # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::total 24119 # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.demand_accesses::cpu3 69130 # number of demand (read+write) accesses
-system.cpu3.l1c.demand_accesses::total 69130 # number of demand (read+write) accesses
-system.cpu3.l1c.overall_accesses::cpu3 69130 # number of overall (read+write) accesses
-system.cpu3.l1c.overall_accesses::total 69130 # number of overall (read+write) accesses
-system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.806692 # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_miss_rate::total 0.806692 # miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.956880 # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::total 0.956880 # miss rate for WriteReq accesses
-system.cpu3.l1c.demand_miss_rate::cpu3 0.859092 # miss rate for demand accesses
-system.cpu3.l1c.demand_miss_rate::total 0.859092 # miss rate for demand accesses
-system.cpu3.l1c.overall_miss_rate::cpu3 0.859092 # miss rate for overall accesses
-system.cpu3.l1c.overall_miss_rate::total 0.859092 # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 67315.611842 # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_miss_latency::total 67315.611842 # average ReadReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 78512.135664 # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::total 78512.135664 # average WriteReq miss latency
-system.cpu3.l1c.demand_avg_miss_latency::cpu3 71666.662934 # average overall miss latency
-system.cpu3.l1c.demand_avg_miss_latency::total 71666.662934 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 71666.662934 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 71666.662934 # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs 2167444 # number of cycles access was blocked
+system.cpu3.l1c.tags.occ_blocks::cpu3 393.873430 # Average occupied blocks per requestor
+system.cpu3.l1c.tags.occ_percent::cpu3 0.769284 # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_percent::total 0.769284 # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::0 274 # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
+system.cpu3.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id
+system.cpu3.l1c.tags.tag_accesses 336364 # Number of tag accesses
+system.cpu3.l1c.tags.data_accesses 336364 # Number of data accesses
+system.cpu3.l1c.ReadReq_hits::cpu3 8580 # number of ReadReq hits
+system.cpu3.l1c.ReadReq_hits::total 8580 # number of ReadReq hits
+system.cpu3.l1c.WriteReq_hits::cpu3 1197 # number of WriteReq hits
+system.cpu3.l1c.WriteReq_hits::total 1197 # number of WriteReq hits
+system.cpu3.l1c.demand_hits::cpu3 9777 # number of demand (read+write) hits
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+system.cpu3.l1c.overall_hits::total 9777 # number of overall hits
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+system.cpu3.l1c.ReadReq_misses::total 36212 # number of ReadReq misses
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+system.cpu3.l1c.WriteReq_misses::total 23956 # number of WriteReq misses
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+system.cpu3.l1c.demand_misses::total 60168 # number of demand (read+write) misses
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+system.cpu3.l1c.overall_misses::total 60168 # number of overall misses
+system.cpu3.l1c.ReadReq_miss_latency::cpu3 2456007015 # number of ReadReq miss cycles
+system.cpu3.l1c.ReadReq_miss_latency::total 2456007015 # number of ReadReq miss cycles
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+system.cpu3.l1c.WriteReq_miss_latency::total 1878963119 # number of WriteReq miss cycles
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+system.cpu3.l1c.demand_miss_latency::total 4334970134 # number of demand (read+write) miss cycles
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+system.cpu3.l1c.overall_miss_latency::total 4334970134 # number of overall miss cycles
+system.cpu3.l1c.ReadReq_accesses::cpu3 44792 # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_accesses::total 44792 # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::cpu3 25153 # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::total 25153 # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.demand_accesses::cpu3 69945 # number of demand (read+write) accesses
+system.cpu3.l1c.demand_accesses::total 69945 # number of demand (read+write) accesses
+system.cpu3.l1c.overall_accesses::cpu3 69945 # number of overall (read+write) accesses
+system.cpu3.l1c.overall_accesses::total 69945 # number of overall (read+write) accesses
+system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.808448 # miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_miss_rate::total 0.808448 # miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.952411 # miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::total 0.952411 # miss rate for WriteReq accesses
+system.cpu3.l1c.demand_miss_rate::cpu3 0.860219 # miss rate for demand accesses
+system.cpu3.l1c.demand_miss_rate::total 0.860219 # miss rate for demand accesses
+system.cpu3.l1c.overall_miss_rate::cpu3 0.860219 # miss rate for overall accesses
+system.cpu3.l1c.overall_miss_rate::total 0.860219 # miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 67823.014885 # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_miss_latency::total 67823.014885 # average ReadReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 78433.925488 # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::total 78433.925488 # average WriteReq miss latency
+system.cpu3.l1c.demand_avg_miss_latency::cpu3 72047.768482 # average overall miss latency
+system.cpu3.l1c.demand_avg_miss_latency::total 72047.768482 # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::cpu3 72047.768482 # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::total 72047.768482 # average overall miss latency
+system.cpu3.l1c.blocked_cycles::no_mshrs 2191987 # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs 59346 # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_mshrs 59750 # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs 36.522158 # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_mshrs 36.685975 # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
-system.cpu3.l1c.writebacks::writebacks 9755 # number of writebacks
-system.cpu3.l1c.writebacks::total 9755 # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36310 # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_misses::total 36310 # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23079 # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::total 23079 # number of WriteReq MSHR misses
-system.cpu3.l1c.demand_mshr_misses::cpu3 59389 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.demand_mshr_misses::total 59389 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.overall_mshr_misses::cpu3 59389 # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_misses::total 59389 # number of overall MSHR misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 2367603538 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_latency::total 2367603538 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1763687167 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1763687167 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::cpu3 4131290705 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::total 4131290705 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3 4131290705 # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total 4131290705 # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 1080268673 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 1080268673 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 3893349735 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 3893349735 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 4973618408 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::total 4973618408 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.806692 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.806692 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.956880 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.956880 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859092 # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_miss_rate::total 0.859092 # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859092 # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total 0.859092 # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 65205.275076 # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 65205.275076 # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 76419.566142 # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 76419.566142 # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 69563.230649 # average overall mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 69563.230649 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 69563.230649 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 69563.230649 # average overall mshr miss latency
+system.cpu3.l1c.writebacks::writebacks 9841 # number of writebacks
+system.cpu3.l1c.writebacks::total 9841 # number of writebacks
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+system.cpu3.l1c.ReadReq_mshr_misses::total 36212 # number of ReadReq MSHR misses
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+system.cpu3.l1c.WriteReq_mshr_misses::total 23956 # number of WriteReq MSHR misses
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+system.cpu3.l1c.demand_mshr_misses::total 60168 # number of demand (read+write) MSHR misses
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+system.cpu3.l1c.ReadReq_mshr_miss_latency::total 2379648497 # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1828763107 # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1828763107 # number of WriteReq MSHR miss cycles
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+system.cpu3.l1c.demand_mshr_miss_latency::total 4208411604 # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::cpu3 4208411604 # number of overall MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::total 4208411604 # number of overall MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 1072329681 # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 1072329681 # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 3992913639 # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 3992913639 # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 5065243320 # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::total 5065243320 # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808448 # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808448 # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.952411 # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.952411 # mshr miss rate for WriteReq accesses
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+system.cpu3.l1c.demand_mshr_miss_rate::total 0.860219 # mshr miss rate for demand accesses
+system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860219 # mshr miss rate for overall accesses
+system.cpu3.l1c.overall_mshr_miss_rate::total 0.860219 # mshr miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 65714.362559 # average ReadReq mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 65714.362559 # average ReadReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 76338.416555 # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 76338.416555 # average WriteReq mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 69944.349222 # average overall mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::total 69944.349222 # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 69944.349222 # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::total 69944.349222 # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu4.num_reads 99015 # number of read accesses completed
-system.cpu4.num_writes 53820 # number of write accesses completed
+system.cpu4.num_reads 100000 # number of read accesses completed
+system.cpu4.num_writes 54692 # number of write accesses completed
system.cpu4.num_copies 0 # number of copy accesses completed
-system.cpu4.l1c.tags.replacements 22084 # number of replacements
-system.cpu4.l1c.tags.tagsinuse 396.195798 # Cycle average of tags in use
-system.cpu4.l1c.tags.total_refs 13300 # Total number of references to valid blocks.
-system.cpu4.l1c.tags.sampled_refs 22488 # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs 0.591427 # Average number of references to valid blocks.
+system.cpu4.l1c.tags.replacements 22289 # number of replacements
+system.cpu4.l1c.tags.tagsinuse 395.541537 # Cycle average of tags in use
+system.cpu4.l1c.tags.total_refs 13462 # Total number of references to valid blocks.
+system.cpu4.l1c.tags.sampled_refs 22679 # Sample count of references to valid blocks.
+system.cpu4.l1c.tags.avg_refs 0.593589 # Average number of references to valid blocks.
system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.tags.occ_blocks::cpu4 396.195798 # Average occupied blocks per requestor
-system.cpu4.l1c.tags.occ_percent::cpu4 0.773820 # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_percent::total 0.773820 # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::0 265 # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id
-system.cpu4.l1c.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id
-system.cpu4.l1c.tags.tag_accesses 330427 # Number of tag accesses
-system.cpu4.l1c.tags.data_accesses 330427 # Number of data accesses
-system.cpu4.l1c.ReadReq_hits::cpu4 8669 # number of ReadReq hits
-system.cpu4.l1c.ReadReq_hits::total 8669 # number of ReadReq hits
-system.cpu4.l1c.WriteReq_hits::cpu4 1045 # number of WriteReq hits
-system.cpu4.l1c.WriteReq_hits::total 1045 # number of WriteReq hits
-system.cpu4.l1c.demand_hits::cpu4 9714 # number of demand (read+write) hits
-system.cpu4.l1c.demand_hits::total 9714 # number of demand (read+write) hits
-system.cpu4.l1c.overall_hits::cpu4 9714 # number of overall hits
-system.cpu4.l1c.overall_hits::total 9714 # number of overall hits
-system.cpu4.l1c.ReadReq_misses::cpu4 35948 # number of ReadReq misses
-system.cpu4.l1c.ReadReq_misses::total 35948 # number of ReadReq misses
-system.cpu4.l1c.WriteReq_misses::cpu4 23093 # number of WriteReq misses
-system.cpu4.l1c.WriteReq_misses::total 23093 # number of WriteReq misses
-system.cpu4.l1c.demand_misses::cpu4 59041 # number of demand (read+write) misses
-system.cpu4.l1c.demand_misses::total 59041 # number of demand (read+write) misses
-system.cpu4.l1c.overall_misses::cpu4 59041 # number of overall misses
-system.cpu4.l1c.overall_misses::total 59041 # number of overall misses
-system.cpu4.l1c.ReadReq_miss_latency::cpu4 2417278257 # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_latency::total 2417278257 # number of ReadReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::cpu4 1822150466 # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::total 1822150466 # number of WriteReq miss cycles
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-system.cpu4.l1c.demand_miss_latency::total 4239428723 # number of demand (read+write) miss cycles
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-system.cpu4.l1c.overall_miss_latency::total 4239428723 # number of overall miss cycles
-system.cpu4.l1c.ReadReq_accesses::cpu4 44617 # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_accesses::total 44617 # number of ReadReq accesses(hits+misses)
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-system.cpu4.l1c.WriteReq_accesses::total 24138 # number of WriteReq accesses(hits+misses)
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-system.cpu4.l1c.demand_accesses::total 68755 # number of demand (read+write) accesses
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-system.cpu4.l1c.overall_accesses::total 68755 # number of overall (read+write) accesses
-system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805702 # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_miss_rate::total 0.805702 # miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.956707 # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::total 0.956707 # miss rate for WriteReq accesses
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-system.cpu4.l1c.demand_miss_rate::total 0.858716 # miss rate for demand accesses
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-system.cpu4.l1c.overall_miss_rate::total 0.858716 # miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 67243.748108 # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_miss_latency::total 67243.748108 # average ReadReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 78904.883125 # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::total 78904.883125 # average WriteReq miss latency
-system.cpu4.l1c.demand_avg_miss_latency::cpu4 71804.825850 # average overall miss latency
-system.cpu4.l1c.demand_avg_miss_latency::total 71804.825850 # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::cpu4 71804.825850 # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::total 71804.825850 # average overall miss latency
-system.cpu4.l1c.blocked_cycles::no_mshrs 2163506 # number of cycles access was blocked
+system.cpu4.l1c.tags.occ_blocks::cpu4 395.541537 # Average occupied blocks per requestor
+system.cpu4.l1c.tags.occ_percent::cpu4 0.772542 # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_percent::total 0.772542 # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_task_id_blocks::1024 390 # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::0 278 # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::1 112 # Occupied blocks per task id
+system.cpu4.l1c.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id
+system.cpu4.l1c.tags.tag_accesses 337633 # Number of tag accesses
+system.cpu4.l1c.tags.data_accesses 337633 # Number of data accesses
+system.cpu4.l1c.ReadReq_hits::cpu4 8739 # number of ReadReq hits
+system.cpu4.l1c.ReadReq_hits::total 8739 # number of ReadReq hits
+system.cpu4.l1c.WriteReq_hits::cpu4 1176 # number of WriteReq hits
+system.cpu4.l1c.WriteReq_hits::total 1176 # number of WriteReq hits
+system.cpu4.l1c.demand_hits::cpu4 9915 # number of demand (read+write) hits
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+system.cpu4.l1c.ReadReq_misses::total 36692 # number of ReadReq misses
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+system.cpu4.l1c.overall_misses::total 60321 # number of overall misses
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+system.cpu4.l1c.demand_miss_latency::total 4302557842 # number of demand (read+write) miss cycles
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+system.cpu4.l1c.overall_miss_latency::total 4302557842 # number of overall miss cycles
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+system.cpu4.l1c.ReadReq_accesses::total 45431 # number of ReadReq accesses(hits+misses)
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+system.cpu4.l1c.WriteReq_accesses::total 24805 # number of WriteReq accesses(hits+misses)
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+system.cpu4.l1c.overall_accesses::total 70236 # number of overall (read+write) accesses
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+system.cpu4.l1c.ReadReq_miss_rate::total 0.807642 # miss rate for ReadReq accesses
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+system.cpu4.l1c.overall_miss_rate::total 0.858833 # miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 67184.845825 # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_miss_latency::total 67184.845825 # average ReadReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 77760.864996 # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::total 77760.864996 # average WriteReq miss latency
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+system.cpu4.l1c.demand_avg_miss_latency::total 71327.694203 # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::cpu4 71327.694203 # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::total 71327.694203 # average overall miss latency
+system.cpu4.l1c.blocked_cycles::no_mshrs 2196199 # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs 58921 # number of cycles access was blocked
+system.cpu4.l1c.blocked::no_mshrs 60342 # number of cycles access was blocked
system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_mshrs 36.718759 # average number of cycles each access was blocked
+system.cpu4.l1c.avg_blocked_cycles::no_mshrs 36.395860 # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
-system.cpu4.l1c.writebacks::writebacks 9586 # number of writebacks
-system.cpu4.l1c.writebacks::total 9586 # number of writebacks
-system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35948 # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_misses::total 35948 # number of ReadReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23093 # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::total 23093 # number of WriteReq MSHR misses
-system.cpu4.l1c.demand_mshr_misses::cpu4 59041 # number of demand (read+write) MSHR misses
-system.cpu4.l1c.demand_mshr_misses::total 59041 # number of demand (read+write) MSHR misses
-system.cpu4.l1c.overall_mshr_misses::cpu4 59041 # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_misses::total 59041 # number of overall MSHR misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 2341432849 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_latency::total 2341432849 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1773798174 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1773798174 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::cpu4 4115231023 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::total 4115231023 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4 4115231023 # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total 4115231023 # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 1089200967 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 1089200967 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 3986639198 # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 3986639198 # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 5075840165 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::total 5075840165 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805702 # mshr miss rate for ReadReq accesses
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-system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.956707 # mshr miss rate for WriteReq accesses
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-system.cpu4.l1c.demand_mshr_miss_rate::total 0.858716 # mshr miss rate for demand accesses
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-system.cpu4.l1c.overall_mshr_miss_rate::total 0.858716 # mshr miss rate for overall accesses
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-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 65133.883637 # average ReadReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 76811.075824 # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 76811.075824 # average WriteReq mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 69701.241900 # average overall mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 69701.241900 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 69701.241900 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 69701.241900 # average overall mshr miss latency
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system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu5.num_reads 99463 # number of read accesses completed
-system.cpu5.num_writes 53761 # number of write accesses completed
+system.cpu5.num_reads 98940 # number of read accesses completed
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system.cpu5.num_copies 0 # number of copy accesses completed
-system.cpu5.l1c.tags.replacements 22236 # number of replacements
-system.cpu5.l1c.tags.tagsinuse 396.818591 # Cycle average of tags in use
-system.cpu5.l1c.tags.total_refs 13326 # Total number of references to valid blocks.
-system.cpu5.l1c.tags.sampled_refs 22643 # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs 0.588526 # Average number of references to valid blocks.
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+system.cpu5.l1c.tags.tagsinuse 395.048373 # Cycle average of tags in use
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system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu5.l1c.tags.occ_task_id_blocks::1024 407 # Occupied blocks per task id
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system.cpu5.l1c.tags.age_task_id_blocks_1024::0 275 # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id
-system.cpu5.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id
-system.cpu5.l1c.tags.tag_accesses 332464 # Number of tag accesses
-system.cpu5.l1c.tags.data_accesses 332464 # Number of data accesses
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-system.cpu5.l1c.overall_hits::total 9793 # number of overall hits
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-system.cpu5.l1c.ReadReq_misses::total 36190 # number of ReadReq misses
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-system.cpu5.l1c.overall_misses::total 59378 # number of overall misses
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-system.cpu5.l1c.ReadReq_avg_miss_latency::total 67443.699171 # average ReadReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 78417.021390 # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::total 78417.021390 # average WriteReq miss latency
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-system.cpu5.l1c.demand_avg_miss_latency::total 71728.946159 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 71728.946159 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 71728.946159 # average overall miss latency
-system.cpu5.l1c.blocked_cycles::no_mshrs 2173855 # number of cycles access was blocked
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+system.cpu5.l1c.tags.tag_accesses 337000 # Number of tag accesses
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+system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 78329.956044 # average WriteReq miss latency
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+system.cpu5.l1c.overall_avg_miss_latency::cpu5 71998.604807 # average overall miss latency
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system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs 59485 # number of cycles access was blocked
+system.cpu5.l1c.blocked::no_mshrs 59918 # number of cycles access was blocked
system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs 36.544591 # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_mshrs 36.609249 # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu5.l1c.writebacks::total 9794 # number of writebacks
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-system.cpu5.l1c.ReadReq_mshr_misses::total 36190 # number of ReadReq MSHR misses
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-system.cpu5.l1c.WriteReq_mshr_misses::total 23188 # number of WriteReq MSHR misses
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-system.cpu5.l1c.demand_mshr_misses::total 59378 # number of demand (read+write) MSHR misses
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-system.cpu5.l1c.overall_mshr_misses::total 59378 # number of overall MSHR misses
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-system.cpu5.l1c.demand_mshr_miss_latency::total 4134178659 # number of demand (read+write) MSHR miss cycles
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-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 1083354468 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 1083354468 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 3885222198 # number of WriteReq MSHR uncacheable cycles
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-system.cpu5.l1c.overall_mshr_uncacheable_latency::total 4968576666 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806229 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806229 # mshr miss rate for ReadReq accesses
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-system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954907 # mshr miss rate for WriteReq accesses
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-system.cpu5.l1c.overall_mshr_miss_rate::total 0.858423 # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 65333.270600 # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 65333.270600 # average ReadReq mshr miss latency
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-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 76322.563222 # average WriteReq mshr miss latency
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-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 69624.754269 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 69624.754269 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::total 69624.754269 # average overall mshr miss latency
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system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu6.num_writes 53258 # number of write accesses completed
+system.cpu6.num_reads 98989 # number of read accesses completed
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system.cpu6.num_copies 0 # number of copy accesses completed
-system.cpu6.l1c.tags.replacements 22399 # number of replacements
-system.cpu6.l1c.tags.tagsinuse 397.638402 # Cycle average of tags in use
-system.cpu6.l1c.tags.total_refs 13152 # Total number of references to valid blocks.
-system.cpu6.l1c.tags.sampled_refs 22779 # Sample count of references to valid blocks.
-system.cpu6.l1c.tags.avg_refs 0.577374 # Average number of references to valid blocks.
+system.cpu6.l1c.tags.replacements 22403 # number of replacements
+system.cpu6.l1c.tags.tagsinuse 396.761014 # Cycle average of tags in use
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system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953791 # miss rate for WriteReq accesses
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-system.cpu6.l1c.overall_miss_rate::total 0.859659 # miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 67573.961036 # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_miss_latency::total 67573.961036 # average ReadReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 78286.519431 # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::total 78286.519431 # average WriteReq miss latency
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-system.cpu6.l1c.demand_avg_miss_latency::total 71748.465757 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 71748.465757 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 71748.465757 # average overall miss latency
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system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_mshrs 59435 # number of cycles access was blocked
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system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu6.l1c.writebacks::total 9755 # number of writebacks
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-system.cpu6.l1c.demand_mshr_misses::total 59166 # number of demand (read+write) MSHR misses
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system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953791 # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953791 # mshr miss rate for WriteReq accesses
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-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 65459.972556 # average ReadReq mshr miss latency
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-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 76192.647554 # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 76192.647554 # average WriteReq mshr miss latency
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-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 69642.316381 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 69642.316381 # average overall mshr miss latency
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system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu7.num_writes 53734 # number of write accesses completed
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system.cpu7.num_copies 0 # number of copy accesses completed
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-system.cpu7.l1c.tags.avg_refs 0.591783 # Average number of references to valid blocks.
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system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu7.l1c.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
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system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu7.l1c.overall_mshr_uncacheable_latency::total 5138331217 # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807550 # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807550 # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953623 # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953623 # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859961 # mshr miss rate for demand accesses
+system.cpu7.l1c.demand_mshr_miss_rate::total 0.859961 # mshr miss rate for demand accesses
+system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859961 # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_miss_rate::total 0.859961 # mshr miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 65667.096185 # average ReadReq mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 65667.096185 # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 76325.138973 # average WriteReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 76325.138973 # average WriteReq mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 69907.679772 # average overall mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::total 69907.679772 # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 69907.679772 # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::total 69907.679772 # average overall mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
sim_ticks 666669000 # Number of ticks simulated
final_tick 666669000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 89799840 # Simulator tick rate (ticks/s)
-host_mem_usage 343700 # Number of bytes of host memory used
-host_seconds 7.42 # Real time elapsed on the host
+host_tick_rate 141005098 # Simulator tick rate (ticks/s)
+host_mem_usage 405228 # Number of bytes of host memory used
+host_seconds 4.73 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0 77587 # Number of bytes read from this memory
system.physmem.bw_total::cpu6 125875059 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7 125110062 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1591465930 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 1591365430 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 83865 # Transaction distribution
system.membus.trans_dist::ReadResp 83861 # Transaction distribution
system.membus.trans_dist::WriteReq 43929 # Transaction distribution
system.membus.trans_dist::ReadExResp 3073 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 420880 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 420880 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 1060914 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 1060914 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 1060914 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1060914 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1060914 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 57934 # Total snoops (count)
+system.membus.snoop_fanout::samples 123225 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 123225 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 123225 # Request fanout histogram
system.membus.reqLayer0.occupancy 288472152 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 43.3 # Layer utilization (%)
system.membus.respLayer0.occupancy 310892000 # Layer occupancy (ticks)
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.funcbus.throughput 0 # Throughput (bytes/s)
-system.funcbus.data_through_bus 0 # Total data (bytes)
-system.toL2Bus.throughput 51067763763 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 370706 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 370692 # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120880 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120421 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 963916 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1756245 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1754904 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1765350 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1754211 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1769359 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1771216 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1757581 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1758989 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 14087855 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 14087855 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 19957440 # Total snoop data (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1756245 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1754904 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1765350 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1754211 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1769359 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1771216 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1757581 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1758989 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 14087855 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 322583 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 561153 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 561153 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 561153 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 655042579 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 98.3 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 160407425 # Layer occupancy (ticks)
sim_ticks 100000000000 # Number of ticks simulated
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 10849136429 # Simulator tick rate (ticks/s)
-host_mem_usage 200176 # Number of bytes of host memory used
-host_seconds 9.22 # Real time elapsed on the host
+host_tick_rate 14153017614 # Simulator tick rate (ticks/s)
+host_mem_usage 261088 # Number of bytes of host memory used
+host_seconds 7.07 # Real time elapsed on the host
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu 106649408 # Number of bytes read from this memory
system.physmem.writeReqs 1666879 # Number of write requests accepted
system.physmem.readBursts 1666397 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1666879 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 106647616 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 1792 # Total number of bytes read from write queue
-system.physmem.bytesWritten 106676608 # Total number of bytes written to DRAM
+system.physmem.bytesReadDRAM 106647872 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 1536 # Total number of bytes read from write queue
+system.physmem.bytesWritten 106676864 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 106649408 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 106680256 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 28 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 33 # Number of DRAM write bursts merged with an existing one
+system.physmem.servicedByWrQ 24 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 30 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 104030 # Per bank write bursts
-system.physmem.perBankRdBursts::1 103995 # Per bank write bursts
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system.physmem.perBankRdBursts::2 104918 # Per bank write bursts
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system.physmem.perBankRdBursts::6 103649 # Per bank write bursts
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system.physmem.perBankRdBursts::8 103869 # Per bank write bursts
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system.physmem.perBankRdBursts::11 104272 # Per bank write bursts
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system.physmem.perBankRdBursts::13 104034 # Per bank write bursts
system.physmem.perBankRdBursts::14 104583 # Per bank write bursts
system.physmem.perBankRdBursts::15 104046 # Per bank write bursts
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system.physmem.perBankWrBursts::1 104090 # Per bank write bursts
system.physmem.perBankWrBursts::2 104175 # Per bank write bursts
system.physmem.perBankWrBursts::3 103885 # Per bank write bursts
system.physmem.perBankWrBursts::4 104730 # Per bank write bursts
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system.physmem.perBankWrBursts::9 104219 # Per bank write bursts
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system.physmem.perBankWrBursts::11 103701 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 99999956143 # Total gap between requests
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 1666879 # Write request sizes (log2)
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 3296334 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 64.715403 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 64.191581 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 23.992085 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 3288433 99.76% 99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 5746 0.17% 99.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples 3296263 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 64.716933 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 64.192638 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 23.994317 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 3288284 99.76% 99.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 5824 0.18% 99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 32 0.00% 99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 32 0.00% 99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 32 0.00% 99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 32 0.00% 99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 32 0.00% 99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 1963 0.06% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 3296334 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 97889 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 17.022975 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean 15.667690 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 106.738588 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 97888 100.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::total 3296263 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 99238 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 16.791612 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean 15.446176 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 106.010489 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 99237 100.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::32768-34815 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 97889 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 97889 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.027674 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.937663 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.829790 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 73237 74.82% 74.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 524 0.54% 75.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 736 0.75% 76.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 1545 1.58% 77.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 16291 16.64% 94.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 5161 5.27% 99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 155 0.16% 99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 78 0.08% 99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 59 0.06% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 41 0.04% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 31 0.03% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 13 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28 9 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29 6 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30 3 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 97889 # Writes before turning the bus around for reads
-system.physmem.totQLat 57937365003 # Total ticks spent queuing
-system.physmem.totMemAccLat 89181783753 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 8331845000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 34768.63 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 99238 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 99238 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.796247 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.714914 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.763911 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 78818 79.42% 79.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 3091 3.11% 82.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 3042 3.07% 85.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 1750 1.76% 87.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 1374 1.38% 88.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 8750 8.82% 97.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 1949 1.96% 99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 293 0.30% 99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 65 0.07% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 43 0.04% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 29 0.03% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27 17 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28 10 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29 2 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30 4 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 99238 # Writes before turning the bus around for reads
+system.physmem.totQLat 61644213329 # Total ticks spent queuing
+system.physmem.totMemAccLat 92888707079 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 8331865000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 36993.05 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 53518.63 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 55743.05 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1066.48 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1066.77 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1066.49 # Average system read bandwidth in MiByte/s
system.physmem.busUtil 16.67 # Data bus utilization in percentage
system.physmem.busUtilRead 8.33 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 8.33 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.19 # Average write queue length when enqueuing
-system.physmem.readRowHits 32168 # Number of row buffer hits during reads
-system.physmem.writeRowHits 4679 # Number of row buffer hits during writes
+system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.44 # Average write queue length when enqueuing
+system.physmem.readRowHits 32184 # Number of row buffer hits during reads
+system.physmem.writeRowHits 4741 # Number of row buffer hits during writes
system.physmem.readRowHitRate 1.93 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 0.28 # Row buffer hit rate for writes
system.physmem.avgGap 30000.50 # Average gap between requests
system.physmem.pageHitRate 1.11 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 5459951 # Time in different power states
+system.physmem.memoryStateTime::IDLE 5342990 # Time in different power states
system.physmem.memoryStateTime::REF 3339180000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 96654442549 # Time in different power states
+system.physmem.memoryStateTime::ACT 96654559510 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 2133296640 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 1666397 # Transaction distribution
system.membus.trans_dist::ReadResp 1666397 # Transaction distribution
system.membus.trans_dist::WriteReq 1666879 # Transaction distribution
system.membus.trans_dist::WriteResp 1666879 # Transaction distribution
system.membus.pkt_count_system.monitor-master::system.physmem.port 6666552 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 6666552 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.monitor-master::system.physmem.port 213329664 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 213329664 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 213329664 # Total data (bytes)
+system.membus.pkt_size_system.monitor-master::system.physmem.port 213329664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 213329664 # Cumulative packet size per connected master and slave (bytes)
system.membus.reqLayer0.occupancy 11679751447 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 11.7 # Layer utilization (%)
-system.membus.respLayer0.occupancy 11400175366 # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy 11427712781 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 11.4 # Layer utilization (%)
system.monitor.readBurstLengthHist::samples 1666397 # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::total 1666879 # Histogram of burst lengths of transmitted packets
system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::mean 1066494080 # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::gmean 1063154518.573643 # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::stdev 107916008.948195 # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::gmean 1063154546.015704 # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::stdev 107915737.892311 # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.averageWriteBandwidth 1066802560 0.00% 0.00% # Average write bandwidth (bytes/s)
system.monitor.totalWrittenBytes 106680256 # Number of bytes written
system.monitor.readLatencyHist::samples 1666397 # Read request-response latency
-system.monitor.readLatencyHist::mean 73557.268741 # Read request-response latency
-system.monitor.readLatencyHist::gmean 68501.179139 # Read request-response latency
-system.monitor.readLatencyHist::stdev 39156.791762 # Read request-response latency
-system.monitor.readLatencyHist::0-32767 28 0.00% 0.00% # Read request-response latency
-system.monitor.readLatencyHist::32768-65535 454399 27.27% 27.27% # Read request-response latency
-system.monitor.readLatencyHist::65536-98303 1040506 62.44% 89.71% # Read request-response latency
-system.monitor.readLatencyHist::98304-131071 73250 4.40% 94.11% # Read request-response latency
-system.monitor.readLatencyHist::131072-163839 47036 2.82% 96.93% # Read request-response latency
-system.monitor.readLatencyHist::163840-196607 12641 0.76% 97.69% # Read request-response latency
-system.monitor.readLatencyHist::196608-229375 7802 0.47% 98.16% # Read request-response latency
-system.monitor.readLatencyHist::229376-262143 7940 0.48% 98.63% # Read request-response latency
-system.monitor.readLatencyHist::262144-294911 8093 0.49% 99.12% # Read request-response latency
-system.monitor.readLatencyHist::294912-327679 7856 0.47% 99.59% # Read request-response latency
-system.monitor.readLatencyHist::327680-360447 4214 0.25% 99.84% # Read request-response latency
-system.monitor.readLatencyHist::360448-393215 1043 0.06% 99.90% # Read request-response latency
-system.monitor.readLatencyHist::393216-425983 827 0.05% 99.95% # Read request-response latency
-system.monitor.readLatencyHist::425984-458751 590 0.04% 99.99% # Read request-response latency
-system.monitor.readLatencyHist::458752-491519 166 0.01% 100.00% # Read request-response latency
-system.monitor.readLatencyHist::491520-524287 6 0.00% 100.00% # Read request-response latency
-system.monitor.readLatencyHist::524288-557055 0 0.00% 100.00% # Read request-response latency
-system.monitor.readLatencyHist::557056-589823 0 0.00% 100.00% # Read request-response latency
-system.monitor.readLatencyHist::589824-622591 0 0.00% 100.00% # Read request-response latency
+system.monitor.readLatencyHist::mean 75762.275031 # Read request-response latency
+system.monitor.readLatencyHist::gmean 69897.504803 # Read request-response latency
+system.monitor.readLatencyHist::stdev 42102.080811 # Read request-response latency
+system.monitor.readLatencyHist::0-32767 24 0.00% 0.00% # Read request-response latency
+system.monitor.readLatencyHist::32768-65535 443180 26.60% 26.60% # Read request-response latency
+system.monitor.readLatencyHist::65536-98303 1020210 61.22% 87.82% # Read request-response latency
+system.monitor.readLatencyHist::98304-131071 76869 4.61% 92.43% # Read request-response latency
+system.monitor.readLatencyHist::131072-163839 59066 3.54% 95.98% # Read request-response latency
+system.monitor.readLatencyHist::163840-196607 25573 1.53% 97.51% # Read request-response latency
+system.monitor.readLatencyHist::196608-229375 9468 0.57% 98.08% # Read request-response latency
+system.monitor.readLatencyHist::229376-262143 7856 0.47% 98.55% # Read request-response latency
+system.monitor.readLatencyHist::262144-294911 8007 0.48% 99.03% # Read request-response latency
+system.monitor.readLatencyHist::294912-327679 7912 0.47% 99.51% # Read request-response latency
+system.monitor.readLatencyHist::327680-360447 4865 0.29% 99.80% # Read request-response latency
+system.monitor.readLatencyHist::360448-393215 1179 0.07% 99.87% # Read request-response latency
+system.monitor.readLatencyHist::393216-425983 915 0.05% 99.92% # Read request-response latency
+system.monitor.readLatencyHist::425984-458751 775 0.05% 99.97% # Read request-response latency
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+system.monitor.readLatencyHist::524288-557055 5 0.00% 100.00% # Read request-response latency
+system.monitor.readLatencyHist::557056-589823 1 0.00% 100.00% # Read request-response latency
+system.monitor.readLatencyHist::589824-622591 2 0.00% 100.00% # Read request-response latency
system.monitor.readLatencyHist::622592-655359 0 0.00% 100.00% # Read request-response latency
system.monitor.readLatencyHist::total 1666397 # Read request-response latency
system.monitor.writeLatencyHist::samples 1666879 # Write request-response latency
-system.monitor.writeLatencyHist::mean 10569.121768 # Write request-response latency
-system.monitor.writeLatencyHist::gmean 10510.211461 # Write request-response latency
-system.monitor.writeLatencyHist::stdev 1197.318213 # Write request-response latency
+system.monitor.writeLatencyHist::mean 10554.999998 # Write request-response latency
+system.monitor.writeLatencyHist::gmean 10497.332887 # Write request-response latency
+system.monitor.writeLatencyHist::stdev 1184.671741 # Write request-response latency
system.monitor.writeLatencyHist::0-1023 0 0.00% 0.00% # Write request-response latency
system.monitor.writeLatencyHist::1024-2047 0 0.00% 0.00% # Write request-response latency
system.monitor.writeLatencyHist::2048-3071 0 0.00% 0.00% # Write request-response latency
system.monitor.writeLatencyHist::6144-7167 0 0.00% 0.00% # Write request-response latency
system.monitor.writeLatencyHist::7168-8191 0 0.00% 0.00% # Write request-response latency
system.monitor.writeLatencyHist::8192-9215 0 0.00% 0.00% # Write request-response latency
-system.monitor.writeLatencyHist::9216-10239 1268910 76.12% 76.12% # Write request-response latency
-system.monitor.writeLatencyHist::10240-11263 92420 5.54% 81.67% # Write request-response latency
-system.monitor.writeLatencyHist::11264-12287 113112 6.79% 88.46% # Write request-response latency
-system.monitor.writeLatencyHist::12288-13311 92715 5.56% 94.02% # Write request-response latency
-system.monitor.writeLatencyHist::13312-14335 62904 3.77% 97.79% # Write request-response latency
-system.monitor.writeLatencyHist::14336-15359 32645 1.96% 99.75% # Write request-response latency
-system.monitor.writeLatencyHist::15360-16383 4173 0.25% 100.00% # Write request-response latency
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+system.monitor.writeLatencyHist::10240-11263 91250 5.47% 82.12% # Write request-response latency
+system.monitor.writeLatencyHist::11264-12287 110692 6.64% 88.76% # Write request-response latency
+system.monitor.writeLatencyHist::12288-13311 90268 5.42% 94.18% # Write request-response latency
+system.monitor.writeLatencyHist::13312-14335 61253 3.67% 97.85% # Write request-response latency
+system.monitor.writeLatencyHist::14336-15359 31832 1.91% 99.76% # Write request-response latency
+system.monitor.writeLatencyHist::15360-16383 3983 0.24% 100.00% # Write request-response latency
system.monitor.writeLatencyHist::16384-17407 0 0.00% 100.00% # Write request-response latency
system.monitor.writeLatencyHist::17408-18431 0 0.00% 100.00% # Write request-response latency
system.monitor.writeLatencyHist::18432-19455 0 0.00% 100.00% # Write request-response latency
system.monitor.ittReqReq::max_value 1041309 # Request-to-request inter transaction time
system.monitor.ittReqReq::total 3333275 # Request-to-request inter transaction time
system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions
-system.monitor.outstandingReadsHist::mean 1.160000 # Outstanding read transactions
+system.monitor.outstandingReadsHist::mean 1.230000 # Outstanding read transactions
system.monitor.outstandingReadsHist::gmean 0 # Outstanding read transactions
-system.monitor.outstandingReadsHist::stdev 1.212061 # Outstanding read transactions
+system.monitor.outstandingReadsHist::stdev 1.309291 # Outstanding read transactions
system.monitor.outstandingReadsHist::0 28 28.00% 28.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::1 45 45.00% 73.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::2 19 19.00% 92.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::3 5 5.00% 97.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::4 0 0.00% 97.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::5 2 2.00% 99.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::1 44 44.00% 72.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::2 17 17.00% 89.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::3 6 6.00% 95.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::4 1 1.00% 96.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::5 3 3.00% 99.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::6 0 0.00% 99.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::7 0 0.00% 99.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::8 1 1.00% 100.00% # Outstanding read transactions
sim_ticks 100000000000 # Number of ticks simulated
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 14364594493 # Simulator tick rate (ticks/s)
-host_mem_usage 195500 # Number of bytes of host memory used
-host_seconds 6.96 # Real time elapsed on the host
+host_tick_rate 11160095249 # Simulator tick rate (ticks/s)
+host_mem_usage 262112 # Number of bytes of host memory used
+host_seconds 8.96 # Real time elapsed on the host
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory
system.physmem.bw_write::total 2133291520 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu 2133292160 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2133292160 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 2133292160 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 1 # Transaction distribution
system.membus.trans_dist::ReadResp 1 # Transaction distribution
system.membus.trans_dist::WriteReq 3333268 # Transaction distribution
system.membus.trans_dist::WriteResp 3333267 # Transaction distribution
system.membus.pkt_count_system.monitor-master::system.physmem.port 6666537 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 6666537 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.monitor-master::system.physmem.port 213329216 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 213329216 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 213329216 # Total data (bytes)
+system.membus.pkt_size_system.monitor-master::system.physmem.port 213329216 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 213329216 # Cumulative packet size per connected master and slave (bytes)
system.membus.reqLayer0.occupancy 16666342328 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 16.7 # Layer utilization (%)
system.membus.respLayer0.occupancy 3333272000 # Layer occupancy (ticks)
projects / gem5.git / commitdiff