Fix bug 450 comment 7

diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py
index d5cba5a2ff4fd00ad4c4e94588a0f218545173f1..e47799626180071a33f30366aee2b05c8bee97af 100644 (file)
--- a/src/soc/experiment/mmu.py
+++ b/src/soc/experiment/mmu.py
@@ -572,7 +572,7 @@ class AddrShifter(Elaboratable):
 #           -- rts == radix tree size, # address bits being translated
 #           rts := unsigned('0' & pgtbl(62 downto 61) & pgtbl(7 downto 5));
             # rts == radix tree size, number of address bits being translated
-            comb += rts.eq((0 & pgtbl[61:63] & pgtbl[5:8]).as_unsigned())
+            comb += rts.eq(((Cat(Const(0b0, 1) , Cat(pgtbl[61:63], pgtbl[5:8]))).as_unsigned())
 
 #           -- mbits == # address bits to index top level of tree
 #           mbits := unsigned('0' & pgtbl(4 downto 0));