(no commit message)

diff --git a/openpower/sv/rfc/ls010/trial_addi.mdwn b/openpower/sv/rfc/ls010/trial_addi.mdwn
index e5a19d8703eb44c641a2225ba9091267d5a35a2b..e76a79945a2dda937bf1dbc85eb4992e7a4976e9 100644 (file)
--- a/openpower/sv/rfc/ls010/trial_addi.mdwn
+++ b/openpower/sv/rfc/ls010/trial_addi.mdwn
@@ -4,6 +4,14 @@
 Background: <https://bugs.libre-soc.org/show_bug.cgi?id=1056#c56>
 <!-- show -->
 
+The idea here is to review a modified version of a Power ISA 3
+instruction definition, to add SVP64 in a completely non-disruptive
+fashion.
+
+
+
+# SVP64-annotated addi instruction (prototype)
+
 **Add Immediate** D-Form
 
 * addi RT,RA,SI
@@ -38,7 +46,7 @@ Background: <https://bugs.libre-soc.org/show_bug.cgi?id=1056#c56>
 
 **Vectorized Add Immediate** SVP64-RM-1S1D/EXTRA3/Normal:D-form
 
-* sv.addi RT,RA,SI 
+* sv.addi RT,RA,SI   (Vectorised on *RT and *RA)
 
 ```
     Prefix: