Merge branch 'master' of ssh://git.libre-riscv.org:922/ls2

diff --combined src/ls2.py
index d236ff280c60c46dcb95ba70c07c5bd95731f433,76c726bfc266066a66123ba6b889d759120405ac..4ea9699e910ce3795b030a8c051385fd0c4446bc
--- 1/src/ls2.py
--- 2/src/ls2.py
+++ b/src/ls2.py
@@@ -868,11 -868,11 +868,11 @@@ def build_platform(fpga, firmware)
          clk_freq = 50e6
          dram_clk_freq = 100e6
      if fpga == 'arty_a7':
-         clk_freq = 50e6
+         clk_freq = 24e6 # urrr "working" with the QSPI core (25 mhz does not)
      if fpga == 'ulx3s':
          clk_freq = 40.0e6
      if fpga == 'orangecrab':
 -        clk_freq = 50e6
 +        clk_freq = 40.0e6
  
      # merge dram_clk_freq with clk_freq if the same
      if clk_freq == dram_clk_freq:
@@@ -896,7 -896,7 +896,7 @@@
      if platform is not None:
          if fpga=="orangecrab":
              # assumes an FT232 USB-UART soldered onto these two pins.
 -            orangecrab_uart = UARTResource(0, rx="N17", tx="M18")
 +            orangecrab_uart = UARTResource(0, rx="M18", tx="N17")
              platform.add_resources([orangecrab_uart])
  
          uart_pins = platform.request("uart", 0)