update hyperram image and add links to datasheet and model

diff --git a/HDL_workflow/2022-03-22_15-56.png b/HDL_workflow/2022-03-22_15-56.png
index 80e32cda83587403a834714e405864d81c2a1821..9cd7153d566276241dd8d35bad9e611e43fdaf75 100644 (file)
Binary files a/HDL_workflow/2022-03-22_15-56.png and b/HDL_workflow/2022-03-22_15-56.png differ

diff --git a/HDL_workflow/HyperRAM.mdwn b/HDL_workflow/HyperRAM.mdwn
index 2e28269fda0de8e310e9a91e840dcb8309b89db2..d9fa06d7d7541eb6dfa0ed8095eb554272523b44 100644 (file)
--- a/HDL_workflow/HyperRAM.mdwn
+++ b/HDL_workflow/HyperRAM.mdwn
@@ -5,6 +5,10 @@
   be constructed and soldered
   <https://www.amazon.co.uk/HALJIA-2-54mm-Dupont-Jumper-Connectors/dp/B06WWB66WL/>
 * nmigen [hyperram.py](https://git.libre-soc.org/?p=lambdasoc.git;a=blob;f=lambdasoc/periph/hyperram.py;hb=HEAD) module
+* Winbond Datasheet for Quad 1bitsqared PMOD:
+  <https://ftp.libre-soc.org/W956x8MBYA_64Mb_HyperBus_pSRAM_TFBGA24_datasheet_A01-005_20211208.pdf>
+* Winbond Verilog Model for W956A8MBY:
+  <https://www.winbond.com/resource-files/W956x8MBY_verilog_p.zip>
 
 ```
 from nmigen.resources.memory import HyperRAMResources