(no commit message)

diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index d901a720a4515171dae38cd3c57432d8e4b48f85..d0c8084373c9aa98a01e4b694df7c5db7f924fbe 100644 (file)
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -212,7 +212,7 @@ Performance designs.
 For a comparative data point the VSR Registers may be expressed in the
 same fashion. The c code below is directly an expression of Figure 97 in
 Power ISA Public v3.1 Book I Section 6.3 page 258, *after compensating for
-MSB0 numbering in both bits abd elements, adapting in full to LSB0 numbering,
+MSB0 numbering in both bits and elements, adapting in full to LSB0 numbering,
 and obeying LE ordering*.
 
 **Crucial to understanding why the subtraction from 1,3,7,15 is present