Revert ""

This reverts commit c16477158b53e192e4232ab610706da245b48348.

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 64c58f8ac4e7a05f500b491f8ddbede3055eb0cf..54514b7c59d9cebce59675acaa1dec33656a900c 100644 (file)
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -72,8 +72,9 @@ SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations:
 | 6 | 7 | 19-20 |  21 | 22   23 |  description     |
 | - | - | ----- | --- |---------|----------------- |
 |sz |SNZ| 0 RG  |   0 | dz  /   | normal mode                      |
-|sz |SNZ| 0 RG  |   1 | 0   /   | scalar reduce mode (mapreduce) |
-|zz |SNZ| 0 RG  |   1 | 1   /   | parallel reduce mode (mapreduce) |
+|sz |SNZ| 0 RG  |   1 | 0   /   | scalar reduce mode (mapreduce), SUBVL=1 |
+|zz |SNZ| 0 RG  |   1 | 1   /   | parallel reduce mode (mapreduce), SUBVL=1 |
+|sz |SNZ| 0 RG  |   1 | SVM /   | subvector reduce mode, SUBVL>1   |
 |sz |SNZ| 1 VLI | inv |  CR-bit | Ffirst 3-bit mode      |
 |sz |SNZ| 1 VLI | inv |  dz /   | Ffirst 5-bit mode       |
 
@@ -86,6 +87,7 @@ Fields:
 * **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1)
 * **RG** inverts the Vector Loop order (VL-1 downto 0) rather
 than the normal 0..VL-1
+* **SVM** sets "subvector" reduce mode
 * **VLi** VL inclusive: in fail-first mode, the truncation of
   VL *includes* the current element at the failure point rather
   than excludes it from the count.