(no commit message)

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 67175b5be640cf807c2879c98fd010ed8dcf6ef3..cf2e618bfc0c1921746635de561cf07425d7b623 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -294,8 +294,7 @@ be suitably adapted to each category.
 It does have to be pointed out that there is huge pressure on the
 Mode bits.  There was therefore insufficient room, unlike the way that
 EXT001 was designed, to provide "identifying bits" *without first partially
-decoding the Suffix*.  This should in no way be conflated with the
-complexity of a *full* Suffix Decode.
+decoding the Suffix*.
 
 Some considerable care has been taken to ensure that Decoding may be
 performed in a strict forward-pipelined fashion that, aside from changes in
@@ -328,7 +327,9 @@ Boolean Logic rules on sets (treating the Vector of CR Fields to be tested by
 tests succeeding (or failing) or whether 'SOME' tests succeed (or fail).
 These options provide the ability to cover the majority of Parallel
 3D GPU Conditions, saving a not inconsiderable number of instructions
-especially given the close interaction with CTR in hot-loops. 
+especially given the close interaction with CTR in hot-loops.[^parity]
+
+[^parity]: adding a parity (XOR) option was too much. instead a parallel-reduction on `crxor` may be used in combination with a Scalar Branch.
 
 Also `SVLR` is introduced, which is a parallel twin of `LR`, and saving
 and restoring of LR and SVLR may be deferred until the final decision