update

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 93049574854225e970d985e11685dde85109adef..18ae7b4cdfc942e2a3577a768f3af67d2ba4f203 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -156,14 +156,15 @@
 \frame{\frametitle{Implementation Options}
 
  \begin{itemize}
-   \item Absolute minimum: Exceptions (if CSRs indicate "V", trap)
+   \item Absolute minimum: Exceptions: if CSRs indicate "V", trap.\\
+         (Requires as absolute minimum that CSRs be in H/W)
    \item Hardware loop, single-instruction issue\\
                 (Do / Don't send through predication to ALU)
    \item Hardware loop, parallel (multi-instruction) issue\\
                 (Do / Don't send through predication to ALU)
    \item Hardware loop, full parallel ALU (not recommended)
   \end{itemize}
-  Notes:\vspace{6pt}
+  Notes:\vspace{4pt}
   \begin{itemize}
    \item 4 (or more?) options above may be deployed on per-op basis
    \item SIMD always sends predication bits through to ALU