(no commit message)

diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index d43fbb1ea29e7cdb2b2c2220c9573d07a3e3fbfd..7c72f557197d26d04a1a30ed944e2808efc11577 100644 (file)
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -231,7 +231,7 @@ be confused with MAXVL when understanding this key aspect of SimpleV.
 
 ## Register Naming and size
 
-As indicated above SV Registers are simply the INT, FP and CR
+As indicated above SV Registers are simply the GPR, FPR and CR
 register files extended linearly to larger sizes; SV Vectorisation
 iterates sequentially through these registers (LSB0 sequential ordering
 from 0 to VL-1).