add unit test for slow SPRs (SPRG0/1)

add test mapping for slow SPR numbers

diff --git a/src/soc/fu/spr/test/test_pipe_caller.py b/src/soc/fu/spr/test/test_pipe_caller.py
index 9e04a458657d8ce600e9ec31a3ae8ce551e65e9c..4c5fb39cd4c43a03d22cc553ed499bc9c6a2f641 100644 (file)
--- a/src/soc/fu/spr/test/test_pipe_caller.py
+++ b/src/soc/fu/spr/test/test_pipe_caller.py
@@ -138,6 +138,27 @@ class SPRTestCase(TestAccumulatorBase):
         self.add_case(Program(lst, bigendian),
                       initial_regs, initial_sprs, initial_msr=msr)
 
+    def case_4_mfspr_slow(self):
+        lst = ["mfspr 1, 272",    # SPRG0
+               "mfspr 4, 273", ]  # SPRG1
+        initial_regs = [0] * 32
+        initial_sprs = {'SPRG0_priv': 0x12345678, 'SPRG1_priv': 0x5678,
+                        }
+        self.add_case(Program(lst, bigendian),
+                      initial_regs, initial_sprs)
+
+    def case_5_mtspr(self):
+        lst = ["mtspr 272, 1",  # SPRG0
+               "mtspr 273, 2",  # SPRG1
+               ]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x129518230011feed
+        initial_regs[2] = 0x123518230011fee0
+        initial_sprs = {'SPRG0_priv': 0x12345678, 'SPRG1_priv': 0x5678,
+                        }
+        self.add_case(Program(lst, bigendian),
+                      initial_regs, initial_sprs)
+
     def case_ilang(self):
         pspec = SPRPipeSpec(id_wid=2)
         alu = SPRBasePipe(pspec)

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index 0dd1d4f7b84058d5c38c2a9024ce3b22fb253951..c591795893c1e352ada112ce15c417ff6a8e7c18 100644 (file)
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -7,7 +7,7 @@ import inspect
 import functools
 import types
 from soc.decoder.power_enums import XER_bits, CryIn, spr_dict
-from soc.regfile.util import fast_reg_to_spr  # HACK!
+from soc.regfile.util import fast_reg_to_spr, slow_reg_to_spr  # HACK!
 from soc.regfile.regfiles import XERRegs, FastRegs
 
 
@@ -156,6 +156,7 @@ class ALUHelpers:
         spr1_en = yield dec2.e.read_spr1.ok
         if spr1_en:
             spr1_sel = yield dec2.e.read_spr1.data
+            spr1_sel = slow_reg_to_spr(spr1_sel)
             spr1_data = sim.spr[spr1_sel].value
             res['spr1'] = spr1_data
 
@@ -418,6 +419,7 @@ class ALUHelpers:
         ok = yield dec2.e.write_spr.ok
         if ok:
             spr_num = yield dec2.e.write_spr.data
+            spr_num = slow_reg_to_spr(spr_num)
             spr_name = spr_dict[spr_num].SPR
             res['spr1'] = sim.spr[spr_name].value
 

diff --git a/src/soc/regfile/util.py b/src/soc/regfile/util.py
index cc0170456fe6ed9a910e5d5f03ec4e100767f128..79effa7c251d589d045478a7f6e16ab095fafd21 100644 (file)
--- a/src/soc/regfile/util.py
+++ b/src/soc/regfile/util.py
@@ -25,3 +25,15 @@ def spr_to_fast_reg(spr_num):
     if not isinstance(spr_num, str):
         spr_num = spr_dict[spr_num].SPR
     return sprstr_to_fast[spr_num]
+
+
+def slow_reg_to_spr(slow_reg):
+    for i, x in enumerate(SPR):
+        if slow_reg == i:
+            return x.value
+
+
+def spr_to_slow_reg(spr_num):
+    for i, x in enumerate(SPR):
+        if spr_num == x.value:
+            return i