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diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 37229471bcbfcbe61a9373e05fd6aa6ec7a8eb0e..234b3f4b18c737d4379a0161015c5a693a15d198 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -389,7 +389,7 @@ is concerned, remains expressed as *Scalar assembler*.[^autovec]
 Whilst Mitch Alsup's
 VVM advocates auto-vectorisation and is limited in its ability to call
 functions, Simple-V's Vertical-First provides explicit control over the
-parallelism ("hphint") and also allows for full state to be stored/restored
+parallelism ("hphint")[^hphint] and also allows for full state to be stored/restored
 (SVLR combined with LR), permitting full function calls to be made.
 
 Simple-V Vertical-First Looping requires an explicit instruction to
@@ -852,3 +852,4 @@ operations.
 [^futurevsx]: A future version or other Stakeholder *may* wish to drop Simple-V onto VSX: this would be a separate RFC
 [^vsx256]: imagine a hypothetical future VSX-256 using the exact same instructions as VSX. the binary incompatibility introducrd would catastrophically **and retroactively** damage existing IBM POWER8,9,10 hardware's reputation and that of Power ISA overall.
 [^autovec]: Compiler auto-vectorisation for best exploitation of SIMD and Vector ISAs on Scalar programming languages (c, c++) is an Indusstry-wide known-hard decades-long problem. Cross-reference the number of hand-optimised assembler algorithms.
+[^hphint]: intended for use when the compiler has determined the extent of Memory or register aliases in loops: `a[i] += a[i+4]` would necessitate a Vertical-First hphint of 4