add example code

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 32b66a09467d4a761ee3e5d1ed445f075eecca01..0d4f43c3db7b770fdead00997d8d76bebbfb98d2 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -667,6 +667,8 @@ loop:
 
  \begin{itemize}
    \item Actually about parallelism, not Vectors (or SIMD) per se
+   \item Only actually needs 3 actual instructions plus CSRs\\
+         (RVV - and "standard" SIMD - require ISA duplication)
    \item Designed for flexibility (graded levels of complexity)
    \item Huge range of implementor freedom
    \item Fits RISC-V ethos: achieve more with less