add beginnings of Pi2LSUI

diff --git a/src/soc/experiment/pi2ls.py b/src/soc/experiment/pi2ls.py
index 7b2e6d0706e73171778b3040c6030ffe6e2fcee5..ac2936bb107035b5c9eccd31b9a2edfef059ecba 100644 (file)
--- a/src/soc/experiment/pi2ls.py
+++ b/src/soc/experiment/pi2ls.py
@@ -19,3 +19,17 @@
     st.data/64                   x_st_data_i
     st.ok/1                      probably kinda redundant, set to x_st_i
 """
+
+from soc.minerva.units.loadstore import LoadStoreUnitInterface
+from soc.experiment.pimem import PortInterface
+from nmigen import Elaboratable, Module, Signal
+
+class Pi2LSUI(Elaboratable):
+
+    def __init__(self, name, regwid=64, addrwid=48):
+        self.pi = PortInterface(name="%s_pi", regwid, addrwid)
+        self.lsui = LoadStoreUnitInterface(addrwid, 4, regwid)
+
+    def elaborate(self, platform):
+        m = Module()
+        return m