(no commit message)

diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index c93fb26be141a6f259d2eb9807dbd0677310ee3e..b1320a732da17a06605561503cd1274d15e93a90 100644 (file)
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -124,12 +124,18 @@ To be absolutely clear:
     element numbering are expressed or implied
 ```
 
-Whilst the bits within the GPRs and FPRs are expected to be MSB0-ordered
-and for numbering to be sequentially incremental the element offset
-numbering is naturally **LSB0-sequentially-incrementing from zero not
-MSB0-incrementing.**  When exclusively using MSB0-numbering, SVP64
+Element offset
+numbering is naturally **LSB0-sequentially-incrementing from zero, not
+MSB0-incrementing** including when element-width overrides are used,
+at which point the elements progress through each register
+sequentially from the LSB end
+(confusingly numbered the highest in MSB0 ordering) and progress
+incrementally to the MSB end (confusingly numbered the lowest in
+MSB0 ordering).
+
+When exclusively using MSB0-numbering, SVP64
 becomes unnecessarily complex to both express and subsequently understand:
-the required subtractions from 63,
+the required conditional subtractions from 63,
 31, 15 and 7 unfortunately become a hostile minefield, obscuring both
 intent and meaning. Therefore for the
 purposes of this section the more natural **LSB0 numbering is assumed**