rename milkymist-ng to MiSoC

diff --git a/README b/README
index 18b2a00f10eb67d96b6a2da3768600d55235b5fa..9e4eb12d417c7703f98f45f0c8d2efb41265a888 100644 (file)
--- a/README
+++ b/README
@@ -25,14 +25,12 @@ more traditional high-level synthesizer that compiles Python routines into
 state machines with datapaths, and a simulator that allows test benches to be
 written in Python.
 
-Migen is the foundation of the next-generation Milkymist SoC.
-
 See the doc/ folder for more technical information.
 
 Code repository:
 https://github.com/milkymist/migen
-New Milkymist SoC based on Migen:
-https://github.com/milkymist/milkymist-ng
+System-on-chip design based on Migen:
+https://github.com/milkymist/misoc
 
 Migen is designed for Python 3.3.
 

diff --git a/doc/bus.rst b/doc/bus.rst
index 03f864ce3980bfd526dd65f363d27fbae23ff4bd..94b88049c0d47a01f5594831eaabd01de67ad44b 100644 (file)
--- a/doc/bus.rst
+++ b/doc/bus.rst
@@ -107,11 +107,11 @@ The first two techniques are explained with more details in [drreorder]_.
 
 .. [drreorder] http://www.xilinx.com/txpatches/pub/documentation/misc/improving%20ddr%20sdram%20efficiency.pdf
 
-Migen and milkymist-ng implement their own bus, called LASMIbus, that features the last two techniques. Grouping by row had been previously explored with ASMI, but difficulties in achieving timing closure at reasonable latencies in FPGA combined with uncertain performance pay-off for some applications discouraged work in that direction.
+Migen and MiSoC implement their own bus, called LASMIbus, that features the last two techniques. Grouping by row had been previously explored with ASMI, but difficulties in achieving timing closure at reasonable latencies in FPGA combined with uncertain performance pay-off for some applications discouraged work in that direction.
 
 Topology and transactions
 =========================
-The LASMI consists of one or several memory controllers (e.g. LASMIcon from milkymist-ng), multiple masters, and crossbar interconnect.
+The LASMI consists of one or several memory controllers (e.g. LASMIcon from MiSoC), multiple masters, and crossbar interconnect.
 
 Each memory controller can expose several bank machines to the crossbar. This way, requests to different SDRAM banks can be processed in parallel.