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note that VSETVL and MXAVECTORDEPTH have to be 15 for RV32E and 31 for RV32 or RV64
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Fri, 18 May 2018 13:25:23 +0000
(14:25 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Fri, 18 May 2018 13:25:23 +0000
(14:25 +0100)
simple_v_extension.mdwn
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diff --git
a/simple_v_extension.mdwn
b/simple_v_extension.mdwn
index 13ab510062184a1d915d5df233d64eff5d78412b..8131a888d27076c2b315a4445e404da9e2f61b2f 100644
(file)
--- a/
simple_v_extension.mdwn
+++ b/
simple_v_extension.mdwn
@@
-608,6
+608,11
@@
XLEN bits.
The second minor change is that when VSETVL is requested to be stored
into x0, it is *ignored* silently.
+Unlike RVV, implementors *must* provide pseudo-parallelism (using sequential
+loops in hardware) if actual hardware-parallelism in the ALUs is not deployed.
+A hybrid is also permitted (as used in Broadcom's VideoCore-IV) however this
+must be *entirely* transparent to the ISA.
+
## Branch Instruction:
Branch operations use standard RV opcodes that are reinterpreted to be