confirmed (in prototype form that LHS Cat will cause conflict
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 21 Oct 2021 15:50:01 +0000 (16:50 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 21 Oct 2021 15:50:01 +0000 (16:50 +0100)
src/ieee754/part/test/minitest_partsig.py
src/ieee754/part_cat/cat.py

index e18e39f6b08e7ded64c67f1d944397d2cc960015..830afa5ab5f1e304b95ff461a6eb51359ed0ea7e 100644 (file)
@@ -22,12 +22,19 @@ if __name__ == "__main__":
     a = SimdSignal(mask, 16)
     b = SimdSignal(mask, 16)
     o = SimdSignal(mask, 32)
+    a1 = SimdSignal(mask, 16)
+    b1 = SimdSignal(mask, 16)
+    omask = (1<<len(o)) - 1
     a.set_module(m)
     b.set_module(m)
     o.set_module(m)
+    a1.set_module(m)
+    b1.set_module(m)
 
-    omask = (1<<len(o)) - 1
+    # RHS Cat
     m.d.comb += o.eq(Cat(a, b))
+    # LHS Cat
+    m.d.comb += Cat(a1, b1).eq(o)
 
     sim = create_simulator(m, [], "minitest")
 
index f663afdd3c93e890feb26fd12277fcb71bafbf8c..291575f4555d81563492ef59fc6e87e509104d12 100644 (file)
@@ -71,6 +71,7 @@ class PartitionedCat(Elaboratable):
         self.width = width
         mask = ctx.get_mask()
         self.output = SimdSignal(mask, self.width, reset_less=True)
+        self.output.set_module(ctx.psig.m)
         self.partition_points = self.output.partpoints
         self.mwidth = len(self.partition_points)+1