(no commit message)

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 3d4e37ebfe98ab1b0d297523ce4300902fb832e9..7f08c1b9a949e8c81ba72e2376b87dc6747188a1 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -205,6 +205,8 @@ on context after decoding of the Scalar suffix:
 | Field Name | Field bits | Description                            |
 |------------|------------|----------------------------------------|
 | ELWIDTH       | `4:5`      | Element Width                       |
+| PACK          | `4`        | Pack  subvectors                   |
+| UNPACK        | `5`        |  Unpack subvectoes                    |
 | ELWIDTH_SRC   | `6:7`      | Element Width for Source      |
 | EXTRA         | `10:18`    | Register Extra encoding                |                          
 | MODE          | `19:23`    | changes Vector behaviour               |
@@ -212,6 +214,7 @@ on context after decoding of the Scalar suffix:
 * MODE changes the behaviour of the SV operation (result saturation, mapreduce)
 * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D and Audio/Video DSP work
 * ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and source operand width
+* PACK and UNPACK apply to Subvector structure packing
 * MASK (and MASK_SRC) and MASKMODE provide predication (two types of sources: scalar INT and Vector CR).
 * Bits 10 to 18 (EXTRA) are further decoded depending on the RM category for the instruction, which is determined only by decoding the Scalar 32 bit suffix.
 
@@ -471,18 +474,6 @@ augmented to 7 bits in length.
 
 `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
 
-## RM-2P-1S1D-PU
-
-| Field Name | Field bits | Description                     |
-|------------|------------|----------------------------|
-| Rdest_EXTRA2 | `10:11`  | extends Rdest (R\*\_EXTRA2 Encoding)   |
-| Rsrc_EXTRA2  | `12:13`  | extends Rsrc  (R\*\_EXTRA2 Encoding)   |
-| PACK_en      | `14`     | Enable pack              |
-| UNPACK_en    | `15`     | Enable unpack             |
-| MASK_SRC     | `16:18`  | Execution Mask for Source     |
-
-for [[sv/mv.vec]], [[sv/mv.swizzle]] and also LD/ST (without index)
-
 ## RM-1P-2S1D
 
 single-predicate, three registers (2 read, 1 write)