clarity on reduce modes in appendix

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index a414bf2663288f0202eb5c1443af3967679e3285..8595dc83f17e095be5910596aa343497f50aad93 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -351,7 +351,8 @@ Scalar Reduction per se does not exist, instead is implemented in SVP64
 as a simple and natural relaxation of the usual restriction on the Vector
 Looping which would terminate if the destination was marked as a Scalar.
 Scalar Reduction by contrast *keeps issuing Vector Element Operations*
-even though the destination register is marked as scalar.  Thus it is
+even though the destination register is marked as scalar *and*
+the same register is used as a source register.  Thus it is
 up to the programmer to be aware of this, observe some conventions,
 and thus end up achieving the desired outcome of scalar reduction.
 
@@ -368,8 +369,8 @@ one register must be assigned, by convention by the programmer to be the
 * One of the sources is a Vector
 * the destination is a scalar
 * optionally but most usefully when one source scalar register is
-  also the scalar destination (which may be informally termed
-  the "accumulator")
+  also the scalar destination (which may be informally termed by
+  convention the "accumulator")
 * That the source register type is the same as the destination register
   type identified as the "accumulator".  Scalar reduction on `cmp`,
   `setb` or `isel` makes no sense for example because of the mixture