//--------------------------------------------------------------------------------
-// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 10:54:03
+// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 11:57:11
//--------------------------------------------------------------------------------
module litedram_core(
input wire clk,
output wire init_error,
input wire [13:0] csr_port0_adr,
input wire csr_port0_we,
- input wire [7:0] csr_port0_dat_w,
- output wire [7:0] csr_port0_dat_r,
+ input wire [31:0] csr_port0_dat_w,
+ output wire [31:0] csr_port0_dat_r,
output wire user_clk,
output wire user_rst,
input wire user_port_native_0_cmd_valid,
reg init_error_re = 1'd0;
wire [13:0] csr_port_adr;
wire csr_port_we;
-wire [7:0] csr_port_dat_w;
-wire [7:0] csr_port_dat_r;
+wire [31:0] csr_port_dat_w;
+wire [31:0] csr_port_dat_r;
wire user_port_cmd_valid;
wire user_port_cmd_ready;
wire user_port_cmd_payload_we;
reg new_master_rdata_valid8 = 1'd0;
wire [13:0] interface0_bank_bus_adr;
wire interface0_bank_bus_we;
-wire [7:0] interface0_bank_bus_dat_w;
-reg [7:0] interface0_bank_bus_dat_r = 8'd0;
+wire [31:0] interface0_bank_bus_dat_w;
+reg [31:0] interface0_bank_bus_dat_r = 32'd0;
wire csrbank0_init_done0_re;
wire csrbank0_init_done0_r;
wire csrbank0_init_done0_we;
reg csrbank0_sel = 1'd0;
wire [13:0] interface1_bank_bus_adr;
wire interface1_bank_bus_we;
-wire [7:0] interface1_bank_bus_dat_w;
-reg [7:0] interface1_bank_bus_dat_r = 8'd0;
+wire [31:0] interface1_bank_bus_dat_w;
+reg [31:0] interface1_bank_bus_dat_r = 32'd0;
wire csrbank1_half_sys8x_taps0_re;
wire [4:0] csrbank1_half_sys8x_taps0_r;
wire csrbank1_half_sys8x_taps0_we;
reg csrbank1_sel = 1'd0;
wire [13:0] interface2_bank_bus_adr;
wire interface2_bank_bus_we;
-wire [7:0] interface2_bank_bus_dat_w;
-reg [7:0] interface2_bank_bus_dat_r = 8'd0;
+wire [31:0] interface2_bank_bus_dat_w;
+reg [31:0] interface2_bank_bus_dat_r = 32'd0;
wire csrbank2_dfii_control0_re;
wire [3:0] csrbank2_dfii_control0_r;
wire csrbank2_dfii_control0_we;
wire [5:0] csrbank2_dfii_pi0_command0_r;
wire csrbank2_dfii_pi0_command0_we;
wire [5:0] csrbank2_dfii_pi0_command0_w;
-wire csrbank2_dfii_pi0_address1_re;
-wire [5:0] csrbank2_dfii_pi0_address1_r;
-wire csrbank2_dfii_pi0_address1_we;
-wire [5:0] csrbank2_dfii_pi0_address1_w;
wire csrbank2_dfii_pi0_address0_re;
-wire [7:0] csrbank2_dfii_pi0_address0_r;
+wire [13:0] csrbank2_dfii_pi0_address0_r;
wire csrbank2_dfii_pi0_address0_we;
-wire [7:0] csrbank2_dfii_pi0_address0_w;
+wire [13:0] csrbank2_dfii_pi0_address0_w;
wire csrbank2_dfii_pi0_baddress0_re;
wire [2:0] csrbank2_dfii_pi0_baddress0_r;
wire csrbank2_dfii_pi0_baddress0_we;
wire [2:0] csrbank2_dfii_pi0_baddress0_w;
-wire csrbank2_dfii_pi0_wrdata3_re;
-wire [7:0] csrbank2_dfii_pi0_wrdata3_r;
-wire csrbank2_dfii_pi0_wrdata3_we;
-wire [7:0] csrbank2_dfii_pi0_wrdata3_w;
-wire csrbank2_dfii_pi0_wrdata2_re;
-wire [7:0] csrbank2_dfii_pi0_wrdata2_r;
-wire csrbank2_dfii_pi0_wrdata2_we;
-wire [7:0] csrbank2_dfii_pi0_wrdata2_w;
-wire csrbank2_dfii_pi0_wrdata1_re;
-wire [7:0] csrbank2_dfii_pi0_wrdata1_r;
-wire csrbank2_dfii_pi0_wrdata1_we;
-wire [7:0] csrbank2_dfii_pi0_wrdata1_w;
wire csrbank2_dfii_pi0_wrdata0_re;
-wire [7:0] csrbank2_dfii_pi0_wrdata0_r;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
wire csrbank2_dfii_pi0_wrdata0_we;
-wire [7:0] csrbank2_dfii_pi0_wrdata0_w;
-wire csrbank2_dfii_pi0_rddata3_re;
-wire [7:0] csrbank2_dfii_pi0_rddata3_r;
-wire csrbank2_dfii_pi0_rddata3_we;
-wire [7:0] csrbank2_dfii_pi0_rddata3_w;
-wire csrbank2_dfii_pi0_rddata2_re;
-wire [7:0] csrbank2_dfii_pi0_rddata2_r;
-wire csrbank2_dfii_pi0_rddata2_we;
-wire [7:0] csrbank2_dfii_pi0_rddata2_w;
-wire csrbank2_dfii_pi0_rddata1_re;
-wire [7:0] csrbank2_dfii_pi0_rddata1_r;
-wire csrbank2_dfii_pi0_rddata1_we;
-wire [7:0] csrbank2_dfii_pi0_rddata1_w;
-wire csrbank2_dfii_pi0_rddata0_re;
-wire [7:0] csrbank2_dfii_pi0_rddata0_r;
-wire csrbank2_dfii_pi0_rddata0_we;
-wire [7:0] csrbank2_dfii_pi0_rddata0_w;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
+wire csrbank2_dfii_pi0_rddata_re;
+wire [31:0] csrbank2_dfii_pi0_rddata_r;
+wire csrbank2_dfii_pi0_rddata_we;
+wire [31:0] csrbank2_dfii_pi0_rddata_w;
wire csrbank2_dfii_pi1_command0_re;
wire [5:0] csrbank2_dfii_pi1_command0_r;
wire csrbank2_dfii_pi1_command0_we;
wire [5:0] csrbank2_dfii_pi1_command0_w;
-wire csrbank2_dfii_pi1_address1_re;
-wire [5:0] csrbank2_dfii_pi1_address1_r;
-wire csrbank2_dfii_pi1_address1_we;
-wire [5:0] csrbank2_dfii_pi1_address1_w;
wire csrbank2_dfii_pi1_address0_re;
-wire [7:0] csrbank2_dfii_pi1_address0_r;
+wire [13:0] csrbank2_dfii_pi1_address0_r;
wire csrbank2_dfii_pi1_address0_we;
-wire [7:0] csrbank2_dfii_pi1_address0_w;
+wire [13:0] csrbank2_dfii_pi1_address0_w;
wire csrbank2_dfii_pi1_baddress0_re;
wire [2:0] csrbank2_dfii_pi1_baddress0_r;
wire csrbank2_dfii_pi1_baddress0_we;
wire [2:0] csrbank2_dfii_pi1_baddress0_w;
-wire csrbank2_dfii_pi1_wrdata3_re;
-wire [7:0] csrbank2_dfii_pi1_wrdata3_r;
-wire csrbank2_dfii_pi1_wrdata3_we;
-wire [7:0] csrbank2_dfii_pi1_wrdata3_w;
-wire csrbank2_dfii_pi1_wrdata2_re;
-wire [7:0] csrbank2_dfii_pi1_wrdata2_r;
-wire csrbank2_dfii_pi1_wrdata2_we;
-wire [7:0] csrbank2_dfii_pi1_wrdata2_w;
-wire csrbank2_dfii_pi1_wrdata1_re;
-wire [7:0] csrbank2_dfii_pi1_wrdata1_r;
-wire csrbank2_dfii_pi1_wrdata1_we;
-wire [7:0] csrbank2_dfii_pi1_wrdata1_w;
wire csrbank2_dfii_pi1_wrdata0_re;
-wire [7:0] csrbank2_dfii_pi1_wrdata0_r;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
wire csrbank2_dfii_pi1_wrdata0_we;
-wire [7:0] csrbank2_dfii_pi1_wrdata0_w;
-wire csrbank2_dfii_pi1_rddata3_re;
-wire [7:0] csrbank2_dfii_pi1_rddata3_r;
-wire csrbank2_dfii_pi1_rddata3_we;
-wire [7:0] csrbank2_dfii_pi1_rddata3_w;
-wire csrbank2_dfii_pi1_rddata2_re;
-wire [7:0] csrbank2_dfii_pi1_rddata2_r;
-wire csrbank2_dfii_pi1_rddata2_we;
-wire [7:0] csrbank2_dfii_pi1_rddata2_w;
-wire csrbank2_dfii_pi1_rddata1_re;
-wire [7:0] csrbank2_dfii_pi1_rddata1_r;
-wire csrbank2_dfii_pi1_rddata1_we;
-wire [7:0] csrbank2_dfii_pi1_rddata1_w;
-wire csrbank2_dfii_pi1_rddata0_re;
-wire [7:0] csrbank2_dfii_pi1_rddata0_r;
-wire csrbank2_dfii_pi1_rddata0_we;
-wire [7:0] csrbank2_dfii_pi1_rddata0_w;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
+wire csrbank2_dfii_pi1_rddata_re;
+wire [31:0] csrbank2_dfii_pi1_rddata_r;
+wire csrbank2_dfii_pi1_rddata_we;
+wire [31:0] csrbank2_dfii_pi1_rddata_w;
wire csrbank2_dfii_pi2_command0_re;
wire [5:0] csrbank2_dfii_pi2_command0_r;
wire csrbank2_dfii_pi2_command0_we;
wire [5:0] csrbank2_dfii_pi2_command0_w;
-wire csrbank2_dfii_pi2_address1_re;
-wire [5:0] csrbank2_dfii_pi2_address1_r;
-wire csrbank2_dfii_pi2_address1_we;
-wire [5:0] csrbank2_dfii_pi2_address1_w;
wire csrbank2_dfii_pi2_address0_re;
-wire [7:0] csrbank2_dfii_pi2_address0_r;
+wire [13:0] csrbank2_dfii_pi2_address0_r;
wire csrbank2_dfii_pi2_address0_we;
-wire [7:0] csrbank2_dfii_pi2_address0_w;
+wire [13:0] csrbank2_dfii_pi2_address0_w;
wire csrbank2_dfii_pi2_baddress0_re;
wire [2:0] csrbank2_dfii_pi2_baddress0_r;
wire csrbank2_dfii_pi2_baddress0_we;
wire [2:0] csrbank2_dfii_pi2_baddress0_w;
-wire csrbank2_dfii_pi2_wrdata3_re;
-wire [7:0] csrbank2_dfii_pi2_wrdata3_r;
-wire csrbank2_dfii_pi2_wrdata3_we;
-wire [7:0] csrbank2_dfii_pi2_wrdata3_w;
-wire csrbank2_dfii_pi2_wrdata2_re;
-wire [7:0] csrbank2_dfii_pi2_wrdata2_r;
-wire csrbank2_dfii_pi2_wrdata2_we;
-wire [7:0] csrbank2_dfii_pi2_wrdata2_w;
-wire csrbank2_dfii_pi2_wrdata1_re;
-wire [7:0] csrbank2_dfii_pi2_wrdata1_r;
-wire csrbank2_dfii_pi2_wrdata1_we;
-wire [7:0] csrbank2_dfii_pi2_wrdata1_w;
wire csrbank2_dfii_pi2_wrdata0_re;
-wire [7:0] csrbank2_dfii_pi2_wrdata0_r;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_r;
wire csrbank2_dfii_pi2_wrdata0_we;
-wire [7:0] csrbank2_dfii_pi2_wrdata0_w;
-wire csrbank2_dfii_pi2_rddata3_re;
-wire [7:0] csrbank2_dfii_pi2_rddata3_r;
-wire csrbank2_dfii_pi2_rddata3_we;
-wire [7:0] csrbank2_dfii_pi2_rddata3_w;
-wire csrbank2_dfii_pi2_rddata2_re;
-wire [7:0] csrbank2_dfii_pi2_rddata2_r;
-wire csrbank2_dfii_pi2_rddata2_we;
-wire [7:0] csrbank2_dfii_pi2_rddata2_w;
-wire csrbank2_dfii_pi2_rddata1_re;
-wire [7:0] csrbank2_dfii_pi2_rddata1_r;
-wire csrbank2_dfii_pi2_rddata1_we;
-wire [7:0] csrbank2_dfii_pi2_rddata1_w;
-wire csrbank2_dfii_pi2_rddata0_re;
-wire [7:0] csrbank2_dfii_pi2_rddata0_r;
-wire csrbank2_dfii_pi2_rddata0_we;
-wire [7:0] csrbank2_dfii_pi2_rddata0_w;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_w;
+wire csrbank2_dfii_pi2_rddata_re;
+wire [31:0] csrbank2_dfii_pi2_rddata_r;
+wire csrbank2_dfii_pi2_rddata_we;
+wire [31:0] csrbank2_dfii_pi2_rddata_w;
wire csrbank2_dfii_pi3_command0_re;
wire [5:0] csrbank2_dfii_pi3_command0_r;
wire csrbank2_dfii_pi3_command0_we;
wire [5:0] csrbank2_dfii_pi3_command0_w;
-wire csrbank2_dfii_pi3_address1_re;
-wire [5:0] csrbank2_dfii_pi3_address1_r;
-wire csrbank2_dfii_pi3_address1_we;
-wire [5:0] csrbank2_dfii_pi3_address1_w;
wire csrbank2_dfii_pi3_address0_re;
-wire [7:0] csrbank2_dfii_pi3_address0_r;
+wire [13:0] csrbank2_dfii_pi3_address0_r;
wire csrbank2_dfii_pi3_address0_we;
-wire [7:0] csrbank2_dfii_pi3_address0_w;
+wire [13:0] csrbank2_dfii_pi3_address0_w;
wire csrbank2_dfii_pi3_baddress0_re;
wire [2:0] csrbank2_dfii_pi3_baddress0_r;
wire csrbank2_dfii_pi3_baddress0_we;
wire [2:0] csrbank2_dfii_pi3_baddress0_w;
-wire csrbank2_dfii_pi3_wrdata3_re;
-wire [7:0] csrbank2_dfii_pi3_wrdata3_r;
-wire csrbank2_dfii_pi3_wrdata3_we;
-wire [7:0] csrbank2_dfii_pi3_wrdata3_w;
-wire csrbank2_dfii_pi3_wrdata2_re;
-wire [7:0] csrbank2_dfii_pi3_wrdata2_r;
-wire csrbank2_dfii_pi3_wrdata2_we;
-wire [7:0] csrbank2_dfii_pi3_wrdata2_w;
-wire csrbank2_dfii_pi3_wrdata1_re;
-wire [7:0] csrbank2_dfii_pi3_wrdata1_r;
-wire csrbank2_dfii_pi3_wrdata1_we;
-wire [7:0] csrbank2_dfii_pi3_wrdata1_w;
wire csrbank2_dfii_pi3_wrdata0_re;
-wire [7:0] csrbank2_dfii_pi3_wrdata0_r;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_r;
wire csrbank2_dfii_pi3_wrdata0_we;
-wire [7:0] csrbank2_dfii_pi3_wrdata0_w;
-wire csrbank2_dfii_pi3_rddata3_re;
-wire [7:0] csrbank2_dfii_pi3_rddata3_r;
-wire csrbank2_dfii_pi3_rddata3_we;
-wire [7:0] csrbank2_dfii_pi3_rddata3_w;
-wire csrbank2_dfii_pi3_rddata2_re;
-wire [7:0] csrbank2_dfii_pi3_rddata2_r;
-wire csrbank2_dfii_pi3_rddata2_we;
-wire [7:0] csrbank2_dfii_pi3_rddata2_w;
-wire csrbank2_dfii_pi3_rddata1_re;
-wire [7:0] csrbank2_dfii_pi3_rddata1_r;
-wire csrbank2_dfii_pi3_rddata1_we;
-wire [7:0] csrbank2_dfii_pi3_rddata1_w;
-wire csrbank2_dfii_pi3_rddata0_re;
-wire [7:0] csrbank2_dfii_pi3_rddata0_r;
-wire csrbank2_dfii_pi3_rddata0_we;
-wire [7:0] csrbank2_dfii_pi3_rddata0_w;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_w;
+wire csrbank2_dfii_pi3_rddata_re;
+wire [31:0] csrbank2_dfii_pi3_rddata_r;
+wire csrbank2_dfii_pi3_rddata_we;
+wire [31:0] csrbank2_dfii_pi3_rddata_w;
reg csrbank2_sel = 1'd0;
wire [13:0] adr;
wire we;
-wire [7:0] dat_w;
-wire [7:0] dat_r;
+wire [31:0] dat_w;
+wire [31:0] dat_r;
reg rhs_array_muxed0 = 1'd0;
reg [13:0] rhs_array_muxed1 = 14'd0;
reg [2:0] rhs_array_muxed2 = 3'd0;
// synthesis translate_on
always @(*) begin
csrbank0_sel <= 1'd0;
- csrbank0_sel <= (interface0_bank_bus_adr[13:11] == 2'd2);
+ csrbank0_sel <= (interface0_bank_bus_adr[13:9] == 2'd2);
if (interface0_bank_bus_adr[0]) begin
csrbank0_sel <= 1'd0;
end
// synthesis translate_on
end
assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
-assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd0));
-assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd0));
+assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd0));
+assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd0));
assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
-assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd1));
-assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd1));
+assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd1));
+assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd1));
assign csrbank0_init_done0_w = init_done_storage;
assign csrbank0_init_error0_w = init_error_storage;
// synthesis translate_on
always @(*) begin
csrbank1_sel <= 1'd0;
- csrbank1_sel <= (interface1_bank_bus_adr[13:11] == 1'd0);
+ csrbank1_sel <= (interface1_bank_bus_adr[13:9] == 1'd0);
if (interface1_bank_bus_adr[0]) begin
csrbank1_sel <= 1'd0;
end
// synthesis translate_on
end
assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
-assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd0));
-assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd0));
+assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd0));
+assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd0));
assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
-assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd1));
-assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd1));
+assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd1));
+assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd1));
assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd2));
-assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd2));
+assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd2));
+assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd2));
assign a7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd3));
-assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd3));
+assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd3));
+assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd3));
assign a7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd4));
-assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd4));
+assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd4));
+assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd4));
assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
-assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd5));
-assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd5));
+assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd5));
+assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd5));
assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd6));
-assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd6));
+assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd6));
+assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd6));
assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd7));
-assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd7));
+assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd7));
+assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd7));
assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd8));
-assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd8));
+assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd8));
+assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd8));
assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd9));
-assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd9));
+assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd9));
+assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd9));
assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0];
assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage;
assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];
// synthesis translate_on
always @(*) begin
csrbank2_sel <= 1'd0;
- csrbank2_sel <= (interface2_bank_bus_adr[13:11] == 1'd1);
+ csrbank2_sel <= (interface2_bank_bus_adr[13:9] == 1'd1);
if (interface2_bank_bus_adr[0]) begin
csrbank2_sel <= 1'd0;
end
// synthesis translate_on
end
assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
-assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd0));
-assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd0));
+assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd0));
+assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd0));
assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd1));
-assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd1));
+assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd1));
+assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd1));
assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd2));
-assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd2));
-assign csrbank2_dfii_pi0_address1_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi0_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd3));
-assign csrbank2_dfii_pi0_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd3));
-assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd4));
-assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd4));
+assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd2));
+assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd2));
+assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[13:0];
+assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd3));
+assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd3));
assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd5));
-assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd5));
-assign csrbank2_dfii_pi0_wrdata3_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi0_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd6));
-assign csrbank2_dfii_pi0_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd6));
-assign csrbank2_dfii_pi0_wrdata2_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi0_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd7));
-assign csrbank2_dfii_pi0_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd7));
-assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi0_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd8));
-assign csrbank2_dfii_pi0_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd8));
-assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd9));
-assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd9));
-assign csrbank2_dfii_pi0_rddata3_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi0_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd10));
-assign csrbank2_dfii_pi0_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd10));
-assign csrbank2_dfii_pi0_rddata2_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi0_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd11));
-assign csrbank2_dfii_pi0_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd11));
-assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi0_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd12));
-assign csrbank2_dfii_pi0_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd12));
-assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi0_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd13));
-assign csrbank2_dfii_pi0_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd13));
+assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd4));
+assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd4));
+assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd5));
+assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd5));
+assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd6));
+assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd6));
assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd14));
-assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd14));
+assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd7));
+assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd7));
assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd15));
-assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd15));
-assign csrbank2_dfii_pi1_address1_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi1_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd16));
-assign csrbank2_dfii_pi1_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd16));
-assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd17));
-assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd17));
+assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd8));
+assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd8));
+assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[13:0];
+assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd9));
+assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd9));
assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd18));
-assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd18));
-assign csrbank2_dfii_pi1_wrdata3_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi1_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd19));
-assign csrbank2_dfii_pi1_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd19));
-assign csrbank2_dfii_pi1_wrdata2_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi1_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd20));
-assign csrbank2_dfii_pi1_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd20));
-assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi1_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd21));
-assign csrbank2_dfii_pi1_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd21));
-assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd22));
-assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd22));
-assign csrbank2_dfii_pi1_rddata3_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi1_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd23));
-assign csrbank2_dfii_pi1_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd23));
-assign csrbank2_dfii_pi1_rddata2_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi1_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd24));
-assign csrbank2_dfii_pi1_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd24));
-assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi1_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd25));
-assign csrbank2_dfii_pi1_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd25));
-assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi1_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd26));
-assign csrbank2_dfii_pi1_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd26));
+assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd10));
+assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd10));
+assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd11));
+assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd11));
+assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd12));
+assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd12));
assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd27));
-assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd27));
+assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd13));
+assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd13));
assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd28));
-assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd28));
-assign csrbank2_dfii_pi2_address1_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi2_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd29));
-assign csrbank2_dfii_pi2_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd29));
-assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd30));
-assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd30));
+assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd14));
+assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd14));
+assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[13:0];
+assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd15));
+assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd15));
assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd31));
-assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd31));
-assign csrbank2_dfii_pi2_wrdata3_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi2_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd32));
-assign csrbank2_dfii_pi2_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd32));
-assign csrbank2_dfii_pi2_wrdata2_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi2_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd33));
-assign csrbank2_dfii_pi2_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd33));
-assign csrbank2_dfii_pi2_wrdata1_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi2_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd34));
-assign csrbank2_dfii_pi2_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd34));
-assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd35));
-assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd35));
-assign csrbank2_dfii_pi2_rddata3_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi2_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd36));
-assign csrbank2_dfii_pi2_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd36));
-assign csrbank2_dfii_pi2_rddata2_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi2_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd37));
-assign csrbank2_dfii_pi2_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd37));
-assign csrbank2_dfii_pi2_rddata1_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi2_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd38));
-assign csrbank2_dfii_pi2_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd38));
-assign csrbank2_dfii_pi2_rddata0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi2_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd39));
-assign csrbank2_dfii_pi2_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd39));
+assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd16));
+assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd16));
+assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd17));
+assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd17));
+assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd18));
+assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd18));
assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd40));
-assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd40));
+assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd19));
+assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd19));
assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd41));
-assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd41));
-assign csrbank2_dfii_pi3_address1_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi3_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd42));
-assign csrbank2_dfii_pi3_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd42));
-assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd43));
-assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd43));
+assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd20));
+assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd20));
+assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[13:0];
+assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd21));
+assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd21));
assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd44));
-assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd44));
-assign csrbank2_dfii_pi3_wrdata3_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi3_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd45));
-assign csrbank2_dfii_pi3_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd45));
-assign csrbank2_dfii_pi3_wrdata2_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi3_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd46));
-assign csrbank2_dfii_pi3_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd46));
-assign csrbank2_dfii_pi3_wrdata1_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi3_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd47));
-assign csrbank2_dfii_pi3_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd47));
-assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd48));
-assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd48));
-assign csrbank2_dfii_pi3_rddata3_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi3_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd49));
-assign csrbank2_dfii_pi3_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd49));
-assign csrbank2_dfii_pi3_rddata2_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi3_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd50));
-assign csrbank2_dfii_pi3_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd50));
-assign csrbank2_dfii_pi3_rddata1_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi3_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd51));
-assign csrbank2_dfii_pi3_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd51));
-assign csrbank2_dfii_pi3_rddata0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi3_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd52));
-assign csrbank2_dfii_pi3_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd52));
+assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd22));
+assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd22));
+assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd23));
+assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd23));
+assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd24));
+assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd24));
assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
-assign csrbank2_dfii_pi0_address1_w = litedramcore_phaseinjector0_address_storage[13:8];
-assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[7:0];
+assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0];
assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
-assign csrbank2_dfii_pi0_wrdata3_w = litedramcore_phaseinjector0_wrdata_storage[31:24];
-assign csrbank2_dfii_pi0_wrdata2_w = litedramcore_phaseinjector0_wrdata_storage[23:16];
-assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[15:8];
-assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[7:0];
-assign csrbank2_dfii_pi0_rddata3_w = litedramcore_phaseinjector0_status[31:24];
-assign csrbank2_dfii_pi0_rddata2_w = litedramcore_phaseinjector0_status[23:16];
-assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_status[15:8];
-assign csrbank2_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_status[7:0];
-assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata0_we;
+assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
+assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_status[31:0];
+assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata_we;
assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
-assign csrbank2_dfii_pi1_address1_w = litedramcore_phaseinjector1_address_storage[13:8];
-assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[7:0];
+assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[13:0];
assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
-assign csrbank2_dfii_pi1_wrdata3_w = litedramcore_phaseinjector1_wrdata_storage[31:24];
-assign csrbank2_dfii_pi1_wrdata2_w = litedramcore_phaseinjector1_wrdata_storage[23:16];
-assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[15:8];
-assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[7:0];
-assign csrbank2_dfii_pi1_rddata3_w = litedramcore_phaseinjector1_status[31:24];
-assign csrbank2_dfii_pi1_rddata2_w = litedramcore_phaseinjector1_status[23:16];
-assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_status[15:8];
-assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_status[7:0];
-assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata0_we;
+assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
+assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_status[31:0];
+assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata_we;
assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
-assign csrbank2_dfii_pi2_address1_w = litedramcore_phaseinjector2_address_storage[13:8];
-assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[7:0];
+assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[13:0];
assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
-assign csrbank2_dfii_pi2_wrdata3_w = litedramcore_phaseinjector2_wrdata_storage[31:24];
-assign csrbank2_dfii_pi2_wrdata2_w = litedramcore_phaseinjector2_wrdata_storage[23:16];
-assign csrbank2_dfii_pi2_wrdata1_w = litedramcore_phaseinjector2_wrdata_storage[15:8];
-assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[7:0];
-assign csrbank2_dfii_pi2_rddata3_w = litedramcore_phaseinjector2_status[31:24];
-assign csrbank2_dfii_pi2_rddata2_w = litedramcore_phaseinjector2_status[23:16];
-assign csrbank2_dfii_pi2_rddata1_w = litedramcore_phaseinjector2_status[15:8];
-assign csrbank2_dfii_pi2_rddata0_w = litedramcore_phaseinjector2_status[7:0];
-assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata0_we;
+assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0];
+assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_status[31:0];
+assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata_we;
assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
-assign csrbank2_dfii_pi3_address1_w = litedramcore_phaseinjector3_address_storage[13:8];
-assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[7:0];
+assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[13:0];
assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
-assign csrbank2_dfii_pi3_wrdata3_w = litedramcore_phaseinjector3_wrdata_storage[31:24];
-assign csrbank2_dfii_pi3_wrdata2_w = litedramcore_phaseinjector3_wrdata_storage[23:16];
-assign csrbank2_dfii_pi3_wrdata1_w = litedramcore_phaseinjector3_wrdata_storage[15:8];
-assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[7:0];
-assign csrbank2_dfii_pi3_rddata3_w = litedramcore_phaseinjector3_status[31:24];
-assign csrbank2_dfii_pi3_rddata2_w = litedramcore_phaseinjector3_status[23:16];
-assign csrbank2_dfii_pi3_rddata1_w = litedramcore_phaseinjector3_status[15:8];
-assign csrbank2_dfii_pi3_rddata0_w = litedramcore_phaseinjector3_status[7:0];
-assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata0_we;
+assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
+assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0];
+assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata_we;
assign adr = csr_port_adr;
assign we = csr_port_we;
assign dat_w = csr_port_dat_w;
new_master_rdata_valid8 <= new_master_rdata_valid7;
interface0_bank_bus_dat_r <= 1'd0;
if (csrbank0_sel) begin
- case (interface0_bank_bus_adr[3])
+ case (interface0_bank_bus_adr[1])
1'd0: begin
interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
end
init_error_re <= csrbank0_init_error0_re;
interface1_bank_bus_dat_r <= 1'd0;
if (csrbank1_sel) begin
- case (interface1_bank_bus_adr[6:3])
+ case (interface1_bank_bus_adr[4:1])
1'd0: begin
interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
end
a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
interface2_bank_bus_dat_r <= 1'd0;
if (csrbank2_sel) begin
- case (interface2_bank_bus_adr[8:3])
+ case (interface2_bank_bus_adr[5:1])
1'd0: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
end
interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
end
2'd3: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address1_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
end
3'd4: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
end
3'd5: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
end
3'd6: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata3_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w;
end
3'd7: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata2_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
end
4'd8: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w;
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
end
4'd9: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
end
4'd10: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata3_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
end
4'd11: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata2_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
end
4'd12: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w;
end
4'd13: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
end
4'd14: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
end
4'd15: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
end
5'd16: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address1_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
end
5'd17: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
end
5'd18: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w;
end
5'd19: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata3_w;
- end
- 5'd20: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata2_w;
- end
- 5'd21: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w;
- end
- 5'd22: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
- end
- 5'd23: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata3_w;
- end
- 5'd24: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata2_w;
- end
- 5'd25: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w;
- end
- 5'd26: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w;
- end
- 5'd27: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
- end
- 5'd28: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
- end
- 5'd29: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address1_w;
- end
- 5'd30: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
- end
- 5'd31: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
- end
- 6'd32: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata3_w;
- end
- 6'd33: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata2_w;
- end
- 6'd34: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata1_w;
- end
- 6'd35: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
- end
- 6'd36: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata3_w;
- end
- 6'd37: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata2_w;
- end
- 6'd38: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata1_w;
- end
- 6'd39: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata0_w;
- end
- 6'd40: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
end
- 6'd41: begin
+ 5'd20: begin
interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
end
- 6'd42: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address1_w;
- end
- 6'd43: begin
+ 5'd21: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
end
- 6'd44: begin
+ 5'd22: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
end
- 6'd45: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata3_w;
- end
- 6'd46: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata2_w;
- end
- 6'd47: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata1_w;
- end
- 6'd48: begin
+ 5'd23: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
end
- 6'd49: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata3_w;
- end
- 6'd50: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata2_w;
- end
- 6'd51: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata1_w;
- end
- 6'd52: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata0_w;
+ 5'd24: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w;
end
endcase
end
litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
end
litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
- if (csrbank2_dfii_pi0_address1_re) begin
- litedramcore_phaseinjector0_address_storage[13:8] <= csrbank2_dfii_pi0_address1_r;
- end
if (csrbank2_dfii_pi0_address0_re) begin
- litedramcore_phaseinjector0_address_storage[7:0] <= csrbank2_dfii_pi0_address0_r;
+ litedramcore_phaseinjector0_address_storage[13:0] <= csrbank2_dfii_pi0_address0_r;
end
litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
if (csrbank2_dfii_pi0_baddress0_re) begin
litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
end
litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
- if (csrbank2_dfii_pi0_wrdata3_re) begin
- litedramcore_phaseinjector0_wrdata_storage[31:24] <= csrbank2_dfii_pi0_wrdata3_r;
- end
- if (csrbank2_dfii_pi0_wrdata2_re) begin
- litedramcore_phaseinjector0_wrdata_storage[23:16] <= csrbank2_dfii_pi0_wrdata2_r;
- end
- if (csrbank2_dfii_pi0_wrdata1_re) begin
- litedramcore_phaseinjector0_wrdata_storage[15:8] <= csrbank2_dfii_pi0_wrdata1_r;
- end
if (csrbank2_dfii_pi0_wrdata0_re) begin
- litedramcore_phaseinjector0_wrdata_storage[7:0] <= csrbank2_dfii_pi0_wrdata0_r;
+ litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
end
litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
if (csrbank2_dfii_pi1_command0_re) begin
litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
end
litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
- if (csrbank2_dfii_pi1_address1_re) begin
- litedramcore_phaseinjector1_address_storage[13:8] <= csrbank2_dfii_pi1_address1_r;
- end
if (csrbank2_dfii_pi1_address0_re) begin
- litedramcore_phaseinjector1_address_storage[7:0] <= csrbank2_dfii_pi1_address0_r;
+ litedramcore_phaseinjector1_address_storage[13:0] <= csrbank2_dfii_pi1_address0_r;
end
litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
if (csrbank2_dfii_pi1_baddress0_re) begin
litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
end
litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
- if (csrbank2_dfii_pi1_wrdata3_re) begin
- litedramcore_phaseinjector1_wrdata_storage[31:24] <= csrbank2_dfii_pi1_wrdata3_r;
- end
- if (csrbank2_dfii_pi1_wrdata2_re) begin
- litedramcore_phaseinjector1_wrdata_storage[23:16] <= csrbank2_dfii_pi1_wrdata2_r;
- end
- if (csrbank2_dfii_pi1_wrdata1_re) begin
- litedramcore_phaseinjector1_wrdata_storage[15:8] <= csrbank2_dfii_pi1_wrdata1_r;
- end
if (csrbank2_dfii_pi1_wrdata0_re) begin
- litedramcore_phaseinjector1_wrdata_storage[7:0] <= csrbank2_dfii_pi1_wrdata0_r;
+ litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
end
litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
if (csrbank2_dfii_pi2_command0_re) begin
litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
end
litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
- if (csrbank2_dfii_pi2_address1_re) begin
- litedramcore_phaseinjector2_address_storage[13:8] <= csrbank2_dfii_pi2_address1_r;
- end
if (csrbank2_dfii_pi2_address0_re) begin
- litedramcore_phaseinjector2_address_storage[7:0] <= csrbank2_dfii_pi2_address0_r;
+ litedramcore_phaseinjector2_address_storage[13:0] <= csrbank2_dfii_pi2_address0_r;
end
litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
if (csrbank2_dfii_pi2_baddress0_re) begin
litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
end
litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
- if (csrbank2_dfii_pi2_wrdata3_re) begin
- litedramcore_phaseinjector2_wrdata_storage[31:24] <= csrbank2_dfii_pi2_wrdata3_r;
- end
- if (csrbank2_dfii_pi2_wrdata2_re) begin
- litedramcore_phaseinjector2_wrdata_storage[23:16] <= csrbank2_dfii_pi2_wrdata2_r;
- end
- if (csrbank2_dfii_pi2_wrdata1_re) begin
- litedramcore_phaseinjector2_wrdata_storage[15:8] <= csrbank2_dfii_pi2_wrdata1_r;
- end
if (csrbank2_dfii_pi2_wrdata0_re) begin
- litedramcore_phaseinjector2_wrdata_storage[7:0] <= csrbank2_dfii_pi2_wrdata0_r;
+ litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
end
litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
if (csrbank2_dfii_pi3_command0_re) begin
litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
end
litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
- if (csrbank2_dfii_pi3_address1_re) begin
- litedramcore_phaseinjector3_address_storage[13:8] <= csrbank2_dfii_pi3_address1_r;
- end
if (csrbank2_dfii_pi3_address0_re) begin
- litedramcore_phaseinjector3_address_storage[7:0] <= csrbank2_dfii_pi3_address0_r;
+ litedramcore_phaseinjector3_address_storage[13:0] <= csrbank2_dfii_pi3_address0_r;
end
litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
if (csrbank2_dfii_pi3_baddress0_re) begin
litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
end
litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
- if (csrbank2_dfii_pi3_wrdata3_re) begin
- litedramcore_phaseinjector3_wrdata_storage[31:24] <= csrbank2_dfii_pi3_wrdata3_r;
- end
- if (csrbank2_dfii_pi3_wrdata2_re) begin
- litedramcore_phaseinjector3_wrdata_storage[23:16] <= csrbank2_dfii_pi3_wrdata2_r;
- end
- if (csrbank2_dfii_pi3_wrdata1_re) begin
- litedramcore_phaseinjector3_wrdata_storage[15:8] <= csrbank2_dfii_pi3_wrdata1_r;
- end
if (csrbank2_dfii_pi3_wrdata0_re) begin
- litedramcore_phaseinjector3_wrdata_storage[7:0] <= csrbank2_dfii_pi3_wrdata0_r;
+ litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
end
litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
if (sys_rst) begin
//--------------------------------------------------------------------------------
-// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 10:54:05
+// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 11:57:13
//--------------------------------------------------------------------------------
module litedram_core(
input wire clk,
output wire init_error,
input wire [13:0] csr_port0_adr,
input wire csr_port0_we,
- input wire [7:0] csr_port0_dat_w,
- output wire [7:0] csr_port0_dat_r,
+ input wire [31:0] csr_port0_dat_w,
+ output wire [31:0] csr_port0_dat_r,
output wire user_clk,
output wire user_rst,
input wire user_port_native_0_cmd_valid,
reg init_error_re = 1'd0;
wire [13:0] csr_port_adr;
wire csr_port_we;
-wire [7:0] csr_port_dat_w;
-wire [7:0] csr_port_dat_r;
+wire [31:0] csr_port_dat_w;
+wire [31:0] csr_port_dat_r;
wire user_port_cmd_valid;
wire user_port_cmd_ready;
wire user_port_cmd_payload_we;
reg new_master_rdata_valid8 = 1'd0;
wire [13:0] interface0_bank_bus_adr;
wire interface0_bank_bus_we;
-wire [7:0] interface0_bank_bus_dat_w;
-reg [7:0] interface0_bank_bus_dat_r = 8'd0;
+wire [31:0] interface0_bank_bus_dat_w;
+reg [31:0] interface0_bank_bus_dat_r = 32'd0;
wire csrbank0_init_done0_re;
wire csrbank0_init_done0_r;
wire csrbank0_init_done0_we;
reg csrbank0_sel = 1'd0;
wire [13:0] interface1_bank_bus_adr;
wire interface1_bank_bus_we;
-wire [7:0] interface1_bank_bus_dat_w;
-reg [7:0] interface1_bank_bus_dat_r = 8'd0;
+wire [31:0] interface1_bank_bus_dat_w;
+reg [31:0] interface1_bank_bus_dat_r = 32'd0;
wire csrbank1_half_sys8x_taps0_re;
wire [4:0] csrbank1_half_sys8x_taps0_r;
wire csrbank1_half_sys8x_taps0_we;
reg csrbank1_sel = 1'd0;
wire [13:0] interface2_bank_bus_adr;
wire interface2_bank_bus_we;
-wire [7:0] interface2_bank_bus_dat_w;
-reg [7:0] interface2_bank_bus_dat_r = 8'd0;
+wire [31:0] interface2_bank_bus_dat_w;
+reg [31:0] interface2_bank_bus_dat_r = 32'd0;
wire csrbank2_dfii_control0_re;
wire [3:0] csrbank2_dfii_control0_r;
wire csrbank2_dfii_control0_we;
wire [5:0] csrbank2_dfii_pi0_command0_r;
wire csrbank2_dfii_pi0_command0_we;
wire [5:0] csrbank2_dfii_pi0_command0_w;
-wire csrbank2_dfii_pi0_address1_re;
-wire [6:0] csrbank2_dfii_pi0_address1_r;
-wire csrbank2_dfii_pi0_address1_we;
-wire [6:0] csrbank2_dfii_pi0_address1_w;
wire csrbank2_dfii_pi0_address0_re;
-wire [7:0] csrbank2_dfii_pi0_address0_r;
+wire [14:0] csrbank2_dfii_pi0_address0_r;
wire csrbank2_dfii_pi0_address0_we;
-wire [7:0] csrbank2_dfii_pi0_address0_w;
+wire [14:0] csrbank2_dfii_pi0_address0_w;
wire csrbank2_dfii_pi0_baddress0_re;
wire [2:0] csrbank2_dfii_pi0_baddress0_r;
wire csrbank2_dfii_pi0_baddress0_we;
wire [2:0] csrbank2_dfii_pi0_baddress0_w;
-wire csrbank2_dfii_pi0_wrdata3_re;
-wire [7:0] csrbank2_dfii_pi0_wrdata3_r;
-wire csrbank2_dfii_pi0_wrdata3_we;
-wire [7:0] csrbank2_dfii_pi0_wrdata3_w;
-wire csrbank2_dfii_pi0_wrdata2_re;
-wire [7:0] csrbank2_dfii_pi0_wrdata2_r;
-wire csrbank2_dfii_pi0_wrdata2_we;
-wire [7:0] csrbank2_dfii_pi0_wrdata2_w;
-wire csrbank2_dfii_pi0_wrdata1_re;
-wire [7:0] csrbank2_dfii_pi0_wrdata1_r;
-wire csrbank2_dfii_pi0_wrdata1_we;
-wire [7:0] csrbank2_dfii_pi0_wrdata1_w;
wire csrbank2_dfii_pi0_wrdata0_re;
-wire [7:0] csrbank2_dfii_pi0_wrdata0_r;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
wire csrbank2_dfii_pi0_wrdata0_we;
-wire [7:0] csrbank2_dfii_pi0_wrdata0_w;
-wire csrbank2_dfii_pi0_rddata3_re;
-wire [7:0] csrbank2_dfii_pi0_rddata3_r;
-wire csrbank2_dfii_pi0_rddata3_we;
-wire [7:0] csrbank2_dfii_pi0_rddata3_w;
-wire csrbank2_dfii_pi0_rddata2_re;
-wire [7:0] csrbank2_dfii_pi0_rddata2_r;
-wire csrbank2_dfii_pi0_rddata2_we;
-wire [7:0] csrbank2_dfii_pi0_rddata2_w;
-wire csrbank2_dfii_pi0_rddata1_re;
-wire [7:0] csrbank2_dfii_pi0_rddata1_r;
-wire csrbank2_dfii_pi0_rddata1_we;
-wire [7:0] csrbank2_dfii_pi0_rddata1_w;
-wire csrbank2_dfii_pi0_rddata0_re;
-wire [7:0] csrbank2_dfii_pi0_rddata0_r;
-wire csrbank2_dfii_pi0_rddata0_we;
-wire [7:0] csrbank2_dfii_pi0_rddata0_w;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
+wire csrbank2_dfii_pi0_rddata_re;
+wire [31:0] csrbank2_dfii_pi0_rddata_r;
+wire csrbank2_dfii_pi0_rddata_we;
+wire [31:0] csrbank2_dfii_pi0_rddata_w;
wire csrbank2_dfii_pi1_command0_re;
wire [5:0] csrbank2_dfii_pi1_command0_r;
wire csrbank2_dfii_pi1_command0_we;
wire [5:0] csrbank2_dfii_pi1_command0_w;
-wire csrbank2_dfii_pi1_address1_re;
-wire [6:0] csrbank2_dfii_pi1_address1_r;
-wire csrbank2_dfii_pi1_address1_we;
-wire [6:0] csrbank2_dfii_pi1_address1_w;
wire csrbank2_dfii_pi1_address0_re;
-wire [7:0] csrbank2_dfii_pi1_address0_r;
+wire [14:0] csrbank2_dfii_pi1_address0_r;
wire csrbank2_dfii_pi1_address0_we;
-wire [7:0] csrbank2_dfii_pi1_address0_w;
+wire [14:0] csrbank2_dfii_pi1_address0_w;
wire csrbank2_dfii_pi1_baddress0_re;
wire [2:0] csrbank2_dfii_pi1_baddress0_r;
wire csrbank2_dfii_pi1_baddress0_we;
wire [2:0] csrbank2_dfii_pi1_baddress0_w;
-wire csrbank2_dfii_pi1_wrdata3_re;
-wire [7:0] csrbank2_dfii_pi1_wrdata3_r;
-wire csrbank2_dfii_pi1_wrdata3_we;
-wire [7:0] csrbank2_dfii_pi1_wrdata3_w;
-wire csrbank2_dfii_pi1_wrdata2_re;
-wire [7:0] csrbank2_dfii_pi1_wrdata2_r;
-wire csrbank2_dfii_pi1_wrdata2_we;
-wire [7:0] csrbank2_dfii_pi1_wrdata2_w;
-wire csrbank2_dfii_pi1_wrdata1_re;
-wire [7:0] csrbank2_dfii_pi1_wrdata1_r;
-wire csrbank2_dfii_pi1_wrdata1_we;
-wire [7:0] csrbank2_dfii_pi1_wrdata1_w;
wire csrbank2_dfii_pi1_wrdata0_re;
-wire [7:0] csrbank2_dfii_pi1_wrdata0_r;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
wire csrbank2_dfii_pi1_wrdata0_we;
-wire [7:0] csrbank2_dfii_pi1_wrdata0_w;
-wire csrbank2_dfii_pi1_rddata3_re;
-wire [7:0] csrbank2_dfii_pi1_rddata3_r;
-wire csrbank2_dfii_pi1_rddata3_we;
-wire [7:0] csrbank2_dfii_pi1_rddata3_w;
-wire csrbank2_dfii_pi1_rddata2_re;
-wire [7:0] csrbank2_dfii_pi1_rddata2_r;
-wire csrbank2_dfii_pi1_rddata2_we;
-wire [7:0] csrbank2_dfii_pi1_rddata2_w;
-wire csrbank2_dfii_pi1_rddata1_re;
-wire [7:0] csrbank2_dfii_pi1_rddata1_r;
-wire csrbank2_dfii_pi1_rddata1_we;
-wire [7:0] csrbank2_dfii_pi1_rddata1_w;
-wire csrbank2_dfii_pi1_rddata0_re;
-wire [7:0] csrbank2_dfii_pi1_rddata0_r;
-wire csrbank2_dfii_pi1_rddata0_we;
-wire [7:0] csrbank2_dfii_pi1_rddata0_w;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
+wire csrbank2_dfii_pi1_rddata_re;
+wire [31:0] csrbank2_dfii_pi1_rddata_r;
+wire csrbank2_dfii_pi1_rddata_we;
+wire [31:0] csrbank2_dfii_pi1_rddata_w;
wire csrbank2_dfii_pi2_command0_re;
wire [5:0] csrbank2_dfii_pi2_command0_r;
wire csrbank2_dfii_pi2_command0_we;
wire [5:0] csrbank2_dfii_pi2_command0_w;
-wire csrbank2_dfii_pi2_address1_re;
-wire [6:0] csrbank2_dfii_pi2_address1_r;
-wire csrbank2_dfii_pi2_address1_we;
-wire [6:0] csrbank2_dfii_pi2_address1_w;
wire csrbank2_dfii_pi2_address0_re;
-wire [7:0] csrbank2_dfii_pi2_address0_r;
+wire [14:0] csrbank2_dfii_pi2_address0_r;
wire csrbank2_dfii_pi2_address0_we;
-wire [7:0] csrbank2_dfii_pi2_address0_w;
+wire [14:0] csrbank2_dfii_pi2_address0_w;
wire csrbank2_dfii_pi2_baddress0_re;
wire [2:0] csrbank2_dfii_pi2_baddress0_r;
wire csrbank2_dfii_pi2_baddress0_we;
wire [2:0] csrbank2_dfii_pi2_baddress0_w;
-wire csrbank2_dfii_pi2_wrdata3_re;
-wire [7:0] csrbank2_dfii_pi2_wrdata3_r;
-wire csrbank2_dfii_pi2_wrdata3_we;
-wire [7:0] csrbank2_dfii_pi2_wrdata3_w;
-wire csrbank2_dfii_pi2_wrdata2_re;
-wire [7:0] csrbank2_dfii_pi2_wrdata2_r;
-wire csrbank2_dfii_pi2_wrdata2_we;
-wire [7:0] csrbank2_dfii_pi2_wrdata2_w;
-wire csrbank2_dfii_pi2_wrdata1_re;
-wire [7:0] csrbank2_dfii_pi2_wrdata1_r;
-wire csrbank2_dfii_pi2_wrdata1_we;
-wire [7:0] csrbank2_dfii_pi2_wrdata1_w;
wire csrbank2_dfii_pi2_wrdata0_re;
-wire [7:0] csrbank2_dfii_pi2_wrdata0_r;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_r;
wire csrbank2_dfii_pi2_wrdata0_we;
-wire [7:0] csrbank2_dfii_pi2_wrdata0_w;
-wire csrbank2_dfii_pi2_rddata3_re;
-wire [7:0] csrbank2_dfii_pi2_rddata3_r;
-wire csrbank2_dfii_pi2_rddata3_we;
-wire [7:0] csrbank2_dfii_pi2_rddata3_w;
-wire csrbank2_dfii_pi2_rddata2_re;
-wire [7:0] csrbank2_dfii_pi2_rddata2_r;
-wire csrbank2_dfii_pi2_rddata2_we;
-wire [7:0] csrbank2_dfii_pi2_rddata2_w;
-wire csrbank2_dfii_pi2_rddata1_re;
-wire [7:0] csrbank2_dfii_pi2_rddata1_r;
-wire csrbank2_dfii_pi2_rddata1_we;
-wire [7:0] csrbank2_dfii_pi2_rddata1_w;
-wire csrbank2_dfii_pi2_rddata0_re;
-wire [7:0] csrbank2_dfii_pi2_rddata0_r;
-wire csrbank2_dfii_pi2_rddata0_we;
-wire [7:0] csrbank2_dfii_pi2_rddata0_w;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_w;
+wire csrbank2_dfii_pi2_rddata_re;
+wire [31:0] csrbank2_dfii_pi2_rddata_r;
+wire csrbank2_dfii_pi2_rddata_we;
+wire [31:0] csrbank2_dfii_pi2_rddata_w;
wire csrbank2_dfii_pi3_command0_re;
wire [5:0] csrbank2_dfii_pi3_command0_r;
wire csrbank2_dfii_pi3_command0_we;
wire [5:0] csrbank2_dfii_pi3_command0_w;
-wire csrbank2_dfii_pi3_address1_re;
-wire [6:0] csrbank2_dfii_pi3_address1_r;
-wire csrbank2_dfii_pi3_address1_we;
-wire [6:0] csrbank2_dfii_pi3_address1_w;
wire csrbank2_dfii_pi3_address0_re;
-wire [7:0] csrbank2_dfii_pi3_address0_r;
+wire [14:0] csrbank2_dfii_pi3_address0_r;
wire csrbank2_dfii_pi3_address0_we;
-wire [7:0] csrbank2_dfii_pi3_address0_w;
+wire [14:0] csrbank2_dfii_pi3_address0_w;
wire csrbank2_dfii_pi3_baddress0_re;
wire [2:0] csrbank2_dfii_pi3_baddress0_r;
wire csrbank2_dfii_pi3_baddress0_we;
wire [2:0] csrbank2_dfii_pi3_baddress0_w;
-wire csrbank2_dfii_pi3_wrdata3_re;
-wire [7:0] csrbank2_dfii_pi3_wrdata3_r;
-wire csrbank2_dfii_pi3_wrdata3_we;
-wire [7:0] csrbank2_dfii_pi3_wrdata3_w;
-wire csrbank2_dfii_pi3_wrdata2_re;
-wire [7:0] csrbank2_dfii_pi3_wrdata2_r;
-wire csrbank2_dfii_pi3_wrdata2_we;
-wire [7:0] csrbank2_dfii_pi3_wrdata2_w;
-wire csrbank2_dfii_pi3_wrdata1_re;
-wire [7:0] csrbank2_dfii_pi3_wrdata1_r;
-wire csrbank2_dfii_pi3_wrdata1_we;
-wire [7:0] csrbank2_dfii_pi3_wrdata1_w;
wire csrbank2_dfii_pi3_wrdata0_re;
-wire [7:0] csrbank2_dfii_pi3_wrdata0_r;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_r;
wire csrbank2_dfii_pi3_wrdata0_we;
-wire [7:0] csrbank2_dfii_pi3_wrdata0_w;
-wire csrbank2_dfii_pi3_rddata3_re;
-wire [7:0] csrbank2_dfii_pi3_rddata3_r;
-wire csrbank2_dfii_pi3_rddata3_we;
-wire [7:0] csrbank2_dfii_pi3_rddata3_w;
-wire csrbank2_dfii_pi3_rddata2_re;
-wire [7:0] csrbank2_dfii_pi3_rddata2_r;
-wire csrbank2_dfii_pi3_rddata2_we;
-wire [7:0] csrbank2_dfii_pi3_rddata2_w;
-wire csrbank2_dfii_pi3_rddata1_re;
-wire [7:0] csrbank2_dfii_pi3_rddata1_r;
-wire csrbank2_dfii_pi3_rddata1_we;
-wire [7:0] csrbank2_dfii_pi3_rddata1_w;
-wire csrbank2_dfii_pi3_rddata0_re;
-wire [7:0] csrbank2_dfii_pi3_rddata0_r;
-wire csrbank2_dfii_pi3_rddata0_we;
-wire [7:0] csrbank2_dfii_pi3_rddata0_w;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_w;
+wire csrbank2_dfii_pi3_rddata_re;
+wire [31:0] csrbank2_dfii_pi3_rddata_r;
+wire csrbank2_dfii_pi3_rddata_we;
+wire [31:0] csrbank2_dfii_pi3_rddata_w;
reg csrbank2_sel = 1'd0;
wire [13:0] adr;
wire we;
-wire [7:0] dat_w;
-wire [7:0] dat_r;
+wire [31:0] dat_w;
+wire [31:0] dat_r;
reg rhs_array_muxed0 = 1'd0;
reg [14:0] rhs_array_muxed1 = 15'd0;
reg [2:0] rhs_array_muxed2 = 3'd0;
reg dummy_d_22;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_ras_n <= 1'd1;
+ litedramcore_master_p1_ras_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
+ litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
end else begin
- litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n;
+ litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n;
end
// synthesis translate_off
dummy_d_22 = dummy_s;
reg dummy_d_23;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p2_rddata <= 32'd0;
+ litedramcore_slave_p1_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
+ litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
end else begin
end
// synthesis translate_off
reg dummy_d_24;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_we_n <= 1'd1;
+ litedramcore_master_p1_we_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
+ litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
end else begin
- litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n;
+ litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n;
end
// synthesis translate_off
dummy_d_24 = dummy_s;
reg dummy_d_25;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p2_rddata_valid <= 1'd0;
+ litedramcore_slave_p1_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
end else begin
end
// synthesis translate_off
reg dummy_d_26;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_cke <= 1'd0;
+ litedramcore_master_p1_cke <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
+ litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
end else begin
- litedramcore_master_p2_cke <= litedramcore_inti_p2_cke;
+ litedramcore_master_p1_cke <= litedramcore_inti_p1_cke;
end
// synthesis translate_off
dummy_d_26 = dummy_s;
reg dummy_d_27;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_odt <= 1'd0;
+ litedramcore_master_p1_odt <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
+ litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
end else begin
- litedramcore_master_p2_odt <= litedramcore_inti_p2_odt;
+ litedramcore_master_p1_odt <= litedramcore_inti_p1_odt;
end
// synthesis translate_off
dummy_d_27 = dummy_s;
reg dummy_d_28;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_reset_n <= 1'd0;
+ litedramcore_master_p1_reset_n <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
+ litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
end else begin
- litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n;
+ litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n;
end
// synthesis translate_off
dummy_d_28 = dummy_s;
reg dummy_d_29;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_act_n <= 1'd1;
+ litedramcore_master_p1_act_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
+ litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
end else begin
- litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n;
+ litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n;
end
// synthesis translate_off
dummy_d_29 = dummy_s;
reg dummy_d_30;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_wrdata <= 32'd0;
+ litedramcore_master_p1_wrdata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
+ litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
end else begin
- litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata;
+ litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata;
end
// synthesis translate_off
dummy_d_30 = dummy_s;
reg dummy_d_31;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_rddata <= 32'd0;
+ litedramcore_inti_p2_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
end else begin
- litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata;
+ litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata;
end
// synthesis translate_off
dummy_d_31 = dummy_s;
reg dummy_d_32;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_wrdata_en <= 1'd0;
+ litedramcore_master_p1_wrdata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
+ litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
end else begin
- litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en;
+ litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en;
end
// synthesis translate_off
dummy_d_32 = dummy_s;
reg dummy_d_33;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_rddata_valid <= 1'd0;
+ litedramcore_inti_p2_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
end else begin
- litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
end
// synthesis translate_off
dummy_d_33 = dummy_s;
reg dummy_d_34;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_wrdata_mask <= 4'd0;
+ litedramcore_master_p1_wrdata_mask <= 4'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
+ litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
end else begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask;
+ litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask;
end
// synthesis translate_off
dummy_d_34 = dummy_s;
reg dummy_d_35;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_rddata_en <= 1'd0;
+ litedramcore_master_p1_rddata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
+ litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
end else begin
- litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en;
+ litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en;
end
// synthesis translate_off
dummy_d_35 = dummy_s;
reg dummy_d_36;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_address <= 15'd0;
+ litedramcore_master_p2_address <= 15'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_address <= litedramcore_slave_p3_address;
+ litedramcore_master_p2_address <= litedramcore_slave_p2_address;
end else begin
- litedramcore_master_p3_address <= litedramcore_inti_p3_address;
+ litedramcore_master_p2_address <= litedramcore_inti_p2_address;
end
// synthesis translate_off
dummy_d_36 = dummy_s;
reg dummy_d_37;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_bank <= 3'd0;
+ litedramcore_master_p2_bank <= 3'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
+ litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
end else begin
- litedramcore_master_p3_bank <= litedramcore_inti_p3_bank;
+ litedramcore_master_p2_bank <= litedramcore_inti_p2_bank;
end
// synthesis translate_off
dummy_d_37 = dummy_s;
reg dummy_d_38;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_cas_n <= 1'd1;
+ litedramcore_master_p2_cas_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
+ litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
end else begin
- litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n;
+ litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n;
end
// synthesis translate_off
dummy_d_38 = dummy_s;
reg dummy_d_39;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_cs_n <= 1'd1;
+ litedramcore_master_p2_cs_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
+ litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
end else begin
- litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n;
+ litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n;
end
// synthesis translate_off
dummy_d_39 = dummy_s;
reg dummy_d_40;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_ras_n <= 1'd1;
+ litedramcore_master_p2_ras_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
+ litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
end else begin
- litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n;
+ litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n;
end
// synthesis translate_off
dummy_d_40 = dummy_s;
reg dummy_d_41;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p3_rddata <= 32'd0;
+ litedramcore_slave_p2_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
+ litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
end else begin
end
// synthesis translate_off
reg dummy_d_42;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_we_n <= 1'd1;
+ litedramcore_master_p2_we_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
+ litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
end else begin
- litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n;
+ litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n;
end
// synthesis translate_off
dummy_d_42 = dummy_s;
reg dummy_d_43;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p3_rddata_valid <= 1'd0;
+ litedramcore_slave_p2_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
end else begin
end
// synthesis translate_off
reg dummy_d_44;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_cke <= 1'd0;
+ litedramcore_master_p2_cke <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
+ litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
end else begin
- litedramcore_master_p3_cke <= litedramcore_inti_p3_cke;
+ litedramcore_master_p2_cke <= litedramcore_inti_p2_cke;
end
// synthesis translate_off
dummy_d_44 = dummy_s;
reg dummy_d_45;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_odt <= 1'd0;
+ litedramcore_master_p2_odt <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
+ litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
end else begin
- litedramcore_master_p3_odt <= litedramcore_inti_p3_odt;
+ litedramcore_master_p2_odt <= litedramcore_inti_p2_odt;
end
// synthesis translate_off
dummy_d_45 = dummy_s;
reg dummy_d_46;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_reset_n <= 1'd0;
+ litedramcore_master_p2_reset_n <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
+ litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
end else begin
- litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n;
+ litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n;
end
// synthesis translate_off
dummy_d_46 = dummy_s;
reg dummy_d_47;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_act_n <= 1'd1;
+ litedramcore_master_p2_act_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
+ litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
end else begin
- litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n;
+ litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n;
end
// synthesis translate_off
dummy_d_47 = dummy_s;
reg dummy_d_48;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_wrdata <= 32'd0;
+ litedramcore_master_p2_wrdata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
+ litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
end else begin
- litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata;
+ litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata;
end
// synthesis translate_off
dummy_d_48 = dummy_s;
reg dummy_d_49;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_rddata <= 32'd0;
+ litedramcore_inti_p3_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
end else begin
- litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata;
+ litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata;
end
// synthesis translate_off
dummy_d_49 = dummy_s;
reg dummy_d_50;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_wrdata_en <= 1'd0;
+ litedramcore_master_p2_wrdata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
+ litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
end else begin
- litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en;
+ litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en;
end
// synthesis translate_off
dummy_d_50 = dummy_s;
reg dummy_d_51;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_rddata_valid <= 1'd0;
+ litedramcore_inti_p3_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
end else begin
- litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
end
// synthesis translate_off
dummy_d_51 = dummy_s;
reg dummy_d_52;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_wrdata_mask <= 4'd0;
+ litedramcore_master_p2_wrdata_mask <= 4'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
+ litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
end else begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask;
+ litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask;
end
// synthesis translate_off
dummy_d_52 = dummy_s;
reg dummy_d_53;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_rddata_en <= 1'd0;
+ litedramcore_master_p2_rddata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
+ litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
end else begin
- litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en;
+ litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en;
end
// synthesis translate_off
dummy_d_53 = dummy_s;
reg dummy_d_54;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_address <= 15'd0;
+ litedramcore_master_p3_address <= 15'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+ litedramcore_master_p3_address <= litedramcore_slave_p3_address;
end else begin
- litedramcore_master_p0_address <= litedramcore_inti_p0_address;
+ litedramcore_master_p3_address <= litedramcore_inti_p3_address;
end
// synthesis translate_off
dummy_d_54 = dummy_s;
reg dummy_d_55;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_bank <= 3'd0;
+ litedramcore_master_p3_bank <= 3'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+ litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
end else begin
- litedramcore_master_p0_bank <= litedramcore_inti_p0_bank;
+ litedramcore_master_p3_bank <= litedramcore_inti_p3_bank;
end
// synthesis translate_off
dummy_d_55 = dummy_s;
reg dummy_d_56;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_cas_n <= 1'd1;
+ litedramcore_master_p3_cas_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+ litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
end else begin
- litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n;
+ litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n;
end
// synthesis translate_off
dummy_d_56 = dummy_s;
reg dummy_d_57;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_cs_n <= 1'd1;
+ litedramcore_master_p3_cs_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+ litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
end else begin
- litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n;
+ litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n;
end
// synthesis translate_off
dummy_d_57 = dummy_s;
reg dummy_d_58;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_ras_n <= 1'd1;
+ litedramcore_master_p3_ras_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+ litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
end else begin
- litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n;
+ litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n;
end
// synthesis translate_off
dummy_d_58 = dummy_s;
reg dummy_d_59;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p0_rddata <= 32'd0;
+ litedramcore_slave_p3_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
+ litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
end else begin
end
// synthesis translate_off
reg dummy_d_60;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_we_n <= 1'd1;
+ litedramcore_master_p3_we_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+ litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
end else begin
- litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n;
+ litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n;
end
// synthesis translate_off
dummy_d_60 = dummy_s;
reg dummy_d_61;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p0_rddata_valid <= 1'd0;
+ litedramcore_slave_p3_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
end else begin
end
// synthesis translate_off
reg dummy_d_62;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_cke <= 1'd0;
+ litedramcore_master_p3_cke <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+ litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
end else begin
- litedramcore_master_p0_cke <= litedramcore_inti_p0_cke;
+ litedramcore_master_p3_cke <= litedramcore_inti_p3_cke;
end
// synthesis translate_off
dummy_d_62 = dummy_s;
reg dummy_d_63;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_odt <= 1'd0;
+ litedramcore_master_p3_odt <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+ litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
end else begin
- litedramcore_master_p0_odt <= litedramcore_inti_p0_odt;
+ litedramcore_master_p3_odt <= litedramcore_inti_p3_odt;
end
// synthesis translate_off
dummy_d_63 = dummy_s;
reg dummy_d_64;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_reset_n <= 1'd0;
+ litedramcore_master_p3_reset_n <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+ litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
end else begin
- litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n;
+ litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n;
end
// synthesis translate_off
dummy_d_64 = dummy_s;
reg dummy_d_65;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_act_n <= 1'd1;
+ litedramcore_master_p3_act_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+ litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
end else begin
- litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n;
+ litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n;
end
// synthesis translate_off
dummy_d_65 = dummy_s;
reg dummy_d_66;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_wrdata <= 32'd0;
+ litedramcore_master_p3_wrdata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+ litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
end else begin
- litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata;
+ litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata;
end
// synthesis translate_off
dummy_d_66 = dummy_s;
reg dummy_d_67;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_rddata <= 32'd0;
+ litedramcore_inti_p0_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
end else begin
- litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata;
+ litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata;
end
// synthesis translate_off
dummy_d_67 = dummy_s;
reg dummy_d_68;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_wrdata_en <= 1'd0;
+ litedramcore_master_p3_wrdata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+ litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
end else begin
- litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en;
+ litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en;
end
// synthesis translate_off
dummy_d_68 = dummy_s;
reg dummy_d_69;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_rddata_valid <= 1'd0;
+ litedramcore_inti_p0_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
end else begin
- litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
end
// synthesis translate_off
dummy_d_69 = dummy_s;
reg dummy_d_70;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_wrdata_mask <= 4'd0;
+ litedramcore_master_p3_wrdata_mask <= 4'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+ litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
end else begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask;
+ litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask;
end
// synthesis translate_off
dummy_d_70 = dummy_s;
reg dummy_d_71;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_rddata_en <= 1'd0;
+ litedramcore_master_p3_rddata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
+ litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
end else begin
- litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en;
+ litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en;
end
// synthesis translate_off
dummy_d_71 = dummy_s;
reg dummy_d_72;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_address <= 15'd0;
+ litedramcore_master_p0_address <= 15'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+ litedramcore_master_p0_address <= litedramcore_slave_p0_address;
end else begin
- litedramcore_master_p1_address <= litedramcore_inti_p1_address;
+ litedramcore_master_p0_address <= litedramcore_inti_p0_address;
end
// synthesis translate_off
dummy_d_72 = dummy_s;
reg dummy_d_73;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_bank <= 3'd0;
+ litedramcore_master_p0_bank <= 3'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
+ litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
end else begin
- litedramcore_master_p1_bank <= litedramcore_inti_p1_bank;
+ litedramcore_master_p0_bank <= litedramcore_inti_p0_bank;
end
// synthesis translate_off
dummy_d_73 = dummy_s;
reg dummy_d_74;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_cas_n <= 1'd1;
+ litedramcore_master_p0_cas_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+ litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
end else begin
- litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n;
+ litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n;
end
// synthesis translate_off
dummy_d_74 = dummy_s;
reg dummy_d_75;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_cs_n <= 1'd1;
+ litedramcore_master_p0_cs_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+ litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
end else begin
- litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n;
+ litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n;
end
// synthesis translate_off
dummy_d_75 = dummy_s;
reg dummy_d_76;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_ras_n <= 1'd1;
+ litedramcore_master_p0_ras_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
+ litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
end else begin
- litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n;
+ litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n;
end
// synthesis translate_off
dummy_d_76 = dummy_s;
reg dummy_d_77;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p1_rddata <= 32'd0;
+ litedramcore_slave_p0_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
+ litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
end else begin
end
// synthesis translate_off
reg dummy_d_78;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_we_n <= 1'd1;
+ litedramcore_master_p0_we_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
+ litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
end else begin
- litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n;
+ litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n;
end
// synthesis translate_off
dummy_d_78 = dummy_s;
reg dummy_d_79;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p1_rddata_valid <= 1'd0;
+ litedramcore_slave_p0_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
end else begin
end
// synthesis translate_off
reg dummy_d_80;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_cke <= 1'd0;
+ litedramcore_master_p0_cke <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+ litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
end else begin
- litedramcore_master_p1_cke <= litedramcore_inti_p1_cke;
+ litedramcore_master_p0_cke <= litedramcore_inti_p0_cke;
end
// synthesis translate_off
dummy_d_80 = dummy_s;
reg dummy_d_81;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_odt <= 1'd0;
+ litedramcore_master_p0_odt <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+ litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
end else begin
- litedramcore_master_p1_odt <= litedramcore_inti_p1_odt;
+ litedramcore_master_p0_odt <= litedramcore_inti_p0_odt;
end
// synthesis translate_off
dummy_d_81 = dummy_s;
reg dummy_d_82;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_reset_n <= 1'd0;
+ litedramcore_master_p0_reset_n <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+ litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
end else begin
- litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n;
+ litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n;
end
// synthesis translate_off
dummy_d_82 = dummy_s;
reg dummy_d_83;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_act_n <= 1'd1;
+ litedramcore_master_p0_act_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+ litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
end else begin
- litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n;
+ litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n;
end
// synthesis translate_off
dummy_d_83 = dummy_s;
reg dummy_d_84;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_wrdata <= 32'd0;
+ litedramcore_master_p0_wrdata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+ litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
end else begin
- litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata;
+ litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata;
end
// synthesis translate_off
dummy_d_84 = dummy_s;
reg dummy_d_85;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_rddata <= 32'd0;
+ litedramcore_inti_p1_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
end else begin
- litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata;
+ litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata;
end
// synthesis translate_off
dummy_d_85 = dummy_s;
reg dummy_d_86;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_wrdata_en <= 1'd0;
+ litedramcore_master_p0_wrdata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+ litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
end else begin
- litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en;
+ litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en;
end
// synthesis translate_off
dummy_d_86 = dummy_s;
reg dummy_d_87;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_rddata_valid <= 1'd0;
+ litedramcore_inti_p1_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
end else begin
- litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
end
// synthesis translate_off
dummy_d_87 = dummy_s;
reg dummy_d_88;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_wrdata_mask <= 4'd0;
+ litedramcore_master_p0_wrdata_mask <= 4'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+ litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
end else begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask;
+ litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask;
end
// synthesis translate_off
dummy_d_88 = dummy_s;
reg dummy_d_89;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_rddata_en <= 1'd0;
+ litedramcore_master_p0_rddata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+ litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
end else begin
- litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en;
+ litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en;
end
// synthesis translate_off
dummy_d_89 = dummy_s;
reg dummy_d_90;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_address <= 15'd0;
+ litedramcore_master_p1_address <= 15'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_address <= litedramcore_slave_p2_address;
+ litedramcore_master_p1_address <= litedramcore_slave_p1_address;
end else begin
- litedramcore_master_p2_address <= litedramcore_inti_p2_address;
+ litedramcore_master_p1_address <= litedramcore_inti_p1_address;
end
// synthesis translate_off
dummy_d_90 = dummy_s;
reg dummy_d_91;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_bank <= 3'd0;
+ litedramcore_master_p1_bank <= 3'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
+ litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
end else begin
- litedramcore_master_p2_bank <= litedramcore_inti_p2_bank;
+ litedramcore_master_p1_bank <= litedramcore_inti_p1_bank;
end
// synthesis translate_off
dummy_d_91 = dummy_s;
reg dummy_d_92;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_cas_n <= 1'd1;
+ litedramcore_master_p1_cas_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
+ litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
end else begin
- litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n;
+ litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n;
end
// synthesis translate_off
dummy_d_92 = dummy_s;
reg dummy_d_93;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_cs_n <= 1'd1;
+ litedramcore_master_p1_cs_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
+ litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
end else begin
- litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n;
+ litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n;
end
// synthesis translate_off
dummy_d_93 = dummy_s;
// synthesis translate_off
reg dummy_d_122;
// synthesis translate_on
+always @(*) begin
+ litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+ case (bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_122 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_123;
+// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_refresh_gnt <= 1'd0;
case (bankmachine0_state)
end
endcase
// synthesis translate_off
- dummy_d_122 = dummy_s;
+ dummy_d_123 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_123;
+reg dummy_d_124;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_cmd_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_123 = dummy_s;
+ dummy_d_124 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_124;
+reg dummy_d_125;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_row_open <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_124 = dummy_s;
+ dummy_d_125 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_125;
+reg dummy_d_126;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_row_close <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_125 = dummy_s;
+ dummy_d_126 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_126;
+reg dummy_d_127;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
end
end
endcase
-// synthesis translate_off
- dummy_d_126 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_127;
-// synthesis translate_on
-always @(*) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
- case (bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
// synthesis translate_off
dummy_d_127 = dummy_s;
// synthesis translate_on
reg dummy_d_138;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+ litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
case (bankmachine1_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_139;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+ litedramcore_bankmachine1_refresh_gnt <= 1'd0;
case (bankmachine1_state)
1'd1: begin
end
2'd3: begin
end
3'd4: begin
+ if (litedramcore_bankmachine1_twtpcon_ready) begin
+ litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_140;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+ litedramcore_bankmachine1_cmd_valid <= 1'd0;
case (bankmachine1_state)
1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine1_twtpcon_ready) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
end
end
+ 3'd4: begin
+ end
3'd5: begin
end
3'd6: begin
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_141;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd0;
+ litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
case (bankmachine1_state)
1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_158;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+ litedramcore_bankmachine2_row_open <= 1'd0;
case (bankmachine2_state)
1'd1: begin
end
end
2'd3: begin
if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+ litedramcore_bankmachine2_row_open <= 1'd1;
end
end
3'd4: begin
reg dummy_d_159;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_row_open <= 1'd0;
+ litedramcore_bankmachine2_row_close <= 1'd0;
case (bankmachine2_state)
1'd1: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
end
2'd2: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
end
2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_open <= 1'd1;
- end
end
3'd4: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
end
3'd5: begin
end
reg dummy_d_160;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_row_close <= 1'd0;
+ litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
case (bankmachine2_state)
1'd1: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_161;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+ litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
case (bankmachine2_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
// synthesis translate_off
reg dummy_d_172;
// synthesis translate_on
+always @(*) begin
+ litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+ case (bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_172 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_173;
+// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
case (bankmachine3_state)
end
endcase
// synthesis translate_off
- dummy_d_172 = dummy_s;
+ dummy_d_173 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_173;
+reg dummy_d_174;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_refresh_gnt <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_173 = dummy_s;
+ dummy_d_174 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_174;
+reg dummy_d_175;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_cmd_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_174 = dummy_s;
+ dummy_d_175 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_175;
+reg dummy_d_176;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_row_open <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_175 = dummy_s;
+ dummy_d_176 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_176;
+reg dummy_d_177;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_row_close <= 1'd0;
default: begin
end
endcase
-// synthesis translate_off
- dummy_d_176 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_177;
-// synthesis translate_on
-always @(*) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
- case (bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
// synthesis translate_off
dummy_d_177 = dummy_s;
// synthesis translate_on
reg dummy_d_191;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd0;
+ litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
case (bankmachine4_state)
1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_192;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+ litedramcore_bankmachine4_cmd_valid <= 1'd0;
case (bankmachine4_state)
1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_207;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+ litedramcore_bankmachine5_refresh_gnt <= 1'd0;
case (bankmachine5_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
- end
end
3'd4: begin
+ if (litedramcore_bankmachine5_twtpcon_ready) begin
+ litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
reg dummy_d_208;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+ litedramcore_bankmachine5_cmd_valid <= 1'd0;
case (bankmachine5_state)
1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
- if (litedramcore_bankmachine5_twtpcon_ready) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd1;
- end
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_209;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd0;
+ litedramcore_bankmachine5_row_open <= 1'd0;
case (bankmachine5_state)
1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ litedramcore_bankmachine5_row_open <= 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
endcase
// synthesis translate_off
dummy_d_209 = dummy_s;
reg dummy_d_210;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_row_open <= 1'd0;
+ litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
case (bankmachine5_state)
1'd1: begin
end
end
2'd3: begin
if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_open <= 1'd1;
+ litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
end
end
3'd4: begin
// synthesis translate_off
reg dummy_d_226;
// synthesis translate_on
-always @(*) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
- case (bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-// synthesis translate_off
- dummy_d_226 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_227;
-// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_row_open <= 1'd0;
case (bankmachine6_state)
end
endcase
// synthesis translate_off
- dummy_d_227 = dummy_s;
+ dummy_d_226 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_228;
+reg dummy_d_227;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_row_close <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_228 = dummy_s;
+ dummy_d_227 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_229;
+reg dummy_d_228;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_229 = dummy_s;
+ dummy_d_228 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_230;
+reg dummy_d_229;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_230 = dummy_s;
+ dummy_d_229 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_231;
+reg dummy_d_230;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
end
end
endcase
+// synthesis translate_off
+ dummy_d_230 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_231;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+ case (bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
// synthesis translate_off
dummy_d_231 = dummy_s;
// synthesis translate_on
// synthesis translate_off
reg dummy_d_241;
// synthesis translate_on
+always @(*) begin
+ litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+ case (bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_241 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_242;
+// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_refresh_gnt <= 1'd0;
case (bankmachine7_state)
end
endcase
// synthesis translate_off
- dummy_d_241 = dummy_s;
+ dummy_d_242 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_242;
+reg dummy_d_243;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_cmd_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_242 = dummy_s;
+ dummy_d_243 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_243;
+reg dummy_d_244;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_row_open <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_243 = dummy_s;
+ dummy_d_244 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_244;
+reg dummy_d_245;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_row_close <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_244 = dummy_s;
+ dummy_d_245 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_245;
+reg dummy_d_246;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
end
end
endcase
-// synthesis translate_off
- dummy_d_245 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_246;
-// synthesis translate_on
-always @(*) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
- case (bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
// synthesis translate_off
dummy_d_246 = dummy_s;
// synthesis translate_on
// synthesis translate_on
always @(*) begin
csrbank0_sel <= 1'd0;
- csrbank0_sel <= (interface0_bank_bus_adr[13:11] == 2'd2);
+ csrbank0_sel <= (interface0_bank_bus_adr[13:9] == 2'd2);
if (interface0_bank_bus_adr[0]) begin
csrbank0_sel <= 1'd0;
end
// synthesis translate_on
end
assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
-assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd0));
-assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd0));
+assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd0));
+assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd0));
assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
-assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd1));
-assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd1));
+assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd1));
+assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd1));
assign csrbank0_init_done0_w = init_done_storage;
assign csrbank0_init_error0_w = init_error_storage;
// synthesis translate_on
always @(*) begin
csrbank1_sel <= 1'd0;
- csrbank1_sel <= (interface1_bank_bus_adr[13:11] == 1'd0);
+ csrbank1_sel <= (interface1_bank_bus_adr[13:9] == 1'd0);
if (interface1_bank_bus_adr[0]) begin
csrbank1_sel <= 1'd0;
end
// synthesis translate_on
end
assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
-assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd0));
-assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd0));
+assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd0));
+assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd0));
assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
-assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd1));
-assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd1));
+assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd1));
+assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd1));
assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd2));
-assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd2));
+assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd2));
+assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd2));
assign a7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd3));
-assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd3));
+assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd3));
+assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd3));
assign a7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd4));
-assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd4));
+assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd4));
+assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd4));
assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
-assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd5));
-assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd5));
+assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd5));
+assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd5));
assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd6));
-assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd6));
+assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd6));
+assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd6));
assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd7));
-assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd7));
+assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd7));
+assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd7));
assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd8));
-assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd8));
+assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd8));
+assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd8));
assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd9));
-assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd9));
+assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd9));
+assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd9));
assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0];
assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage;
assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];
// synthesis translate_on
always @(*) begin
csrbank2_sel <= 1'd0;
- csrbank2_sel <= (interface2_bank_bus_adr[13:11] == 1'd1);
+ csrbank2_sel <= (interface2_bank_bus_adr[13:9] == 1'd1);
if (interface2_bank_bus_adr[0]) begin
csrbank2_sel <= 1'd0;
end
// synthesis translate_on
end
assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
-assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd0));
-assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd0));
+assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd0));
+assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd0));
assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd1));
-assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd1));
+assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd1));
+assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd1));
assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd2));
-assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd2));
-assign csrbank2_dfii_pi0_address1_r = interface2_bank_bus_dat_w[6:0];
-assign csrbank2_dfii_pi0_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd3));
-assign csrbank2_dfii_pi0_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd3));
-assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd4));
-assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd4));
+assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd2));
+assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd2));
+assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0];
+assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd3));
+assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd3));
assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd5));
-assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd5));
-assign csrbank2_dfii_pi0_wrdata3_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi0_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd6));
-assign csrbank2_dfii_pi0_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd6));
-assign csrbank2_dfii_pi0_wrdata2_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi0_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd7));
-assign csrbank2_dfii_pi0_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd7));
-assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi0_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd8));
-assign csrbank2_dfii_pi0_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd8));
-assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd9));
-assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd9));
-assign csrbank2_dfii_pi0_rddata3_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi0_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd10));
-assign csrbank2_dfii_pi0_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd10));
-assign csrbank2_dfii_pi0_rddata2_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi0_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd11));
-assign csrbank2_dfii_pi0_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd11));
-assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi0_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd12));
-assign csrbank2_dfii_pi0_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd12));
-assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi0_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd13));
-assign csrbank2_dfii_pi0_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd13));
+assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd4));
+assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd4));
+assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd5));
+assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd5));
+assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd6));
+assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd6));
assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd14));
-assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd14));
+assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd7));
+assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd7));
assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd15));
-assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd15));
-assign csrbank2_dfii_pi1_address1_r = interface2_bank_bus_dat_w[6:0];
-assign csrbank2_dfii_pi1_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd16));
-assign csrbank2_dfii_pi1_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd16));
-assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd17));
-assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd17));
+assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd8));
+assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd8));
+assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0];
+assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd9));
+assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd9));
assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd18));
-assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd18));
-assign csrbank2_dfii_pi1_wrdata3_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi1_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd19));
-assign csrbank2_dfii_pi1_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd19));
-assign csrbank2_dfii_pi1_wrdata2_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi1_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd20));
-assign csrbank2_dfii_pi1_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd20));
-assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi1_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd21));
-assign csrbank2_dfii_pi1_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd21));
-assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd22));
-assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd22));
-assign csrbank2_dfii_pi1_rddata3_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi1_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd23));
-assign csrbank2_dfii_pi1_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd23));
-assign csrbank2_dfii_pi1_rddata2_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi1_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd24));
-assign csrbank2_dfii_pi1_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd24));
-assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi1_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd25));
-assign csrbank2_dfii_pi1_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd25));
-assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi1_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd26));
-assign csrbank2_dfii_pi1_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd26));
+assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd10));
+assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd10));
+assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd11));
+assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd11));
+assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd12));
+assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd12));
assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd27));
-assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd27));
+assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd13));
+assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd13));
assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd28));
-assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd28));
-assign csrbank2_dfii_pi2_address1_r = interface2_bank_bus_dat_w[6:0];
-assign csrbank2_dfii_pi2_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd29));
-assign csrbank2_dfii_pi2_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd29));
-assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd30));
-assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd30));
+assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd14));
+assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd14));
+assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[14:0];
+assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd15));
+assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd15));
assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd31));
-assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd31));
-assign csrbank2_dfii_pi2_wrdata3_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi2_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd32));
-assign csrbank2_dfii_pi2_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd32));
-assign csrbank2_dfii_pi2_wrdata2_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi2_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd33));
-assign csrbank2_dfii_pi2_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd33));
-assign csrbank2_dfii_pi2_wrdata1_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi2_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd34));
-assign csrbank2_dfii_pi2_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd34));
-assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd35));
-assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd35));
-assign csrbank2_dfii_pi2_rddata3_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi2_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd36));
-assign csrbank2_dfii_pi2_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd36));
-assign csrbank2_dfii_pi2_rddata2_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi2_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd37));
-assign csrbank2_dfii_pi2_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd37));
-assign csrbank2_dfii_pi2_rddata1_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi2_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd38));
-assign csrbank2_dfii_pi2_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd38));
-assign csrbank2_dfii_pi2_rddata0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi2_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd39));
-assign csrbank2_dfii_pi2_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd39));
+assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd16));
+assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd16));
+assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd17));
+assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd17));
+assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd18));
+assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd18));
assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd40));
-assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd40));
+assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd19));
+assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd19));
assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd41));
-assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd41));
-assign csrbank2_dfii_pi3_address1_r = interface2_bank_bus_dat_w[6:0];
-assign csrbank2_dfii_pi3_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd42));
-assign csrbank2_dfii_pi3_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd42));
-assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd43));
-assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd43));
+assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd20));
+assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd20));
+assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[14:0];
+assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd21));
+assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd21));
assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd44));
-assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd44));
-assign csrbank2_dfii_pi3_wrdata3_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi3_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd45));
-assign csrbank2_dfii_pi3_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd45));
-assign csrbank2_dfii_pi3_wrdata2_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi3_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd46));
-assign csrbank2_dfii_pi3_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd46));
-assign csrbank2_dfii_pi3_wrdata1_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi3_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd47));
-assign csrbank2_dfii_pi3_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd47));
-assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd48));
-assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd48));
-assign csrbank2_dfii_pi3_rddata3_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi3_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd49));
-assign csrbank2_dfii_pi3_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd49));
-assign csrbank2_dfii_pi3_rddata2_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi3_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd50));
-assign csrbank2_dfii_pi3_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd50));
-assign csrbank2_dfii_pi3_rddata1_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi3_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd51));
-assign csrbank2_dfii_pi3_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd51));
-assign csrbank2_dfii_pi3_rddata0_r = interface2_bank_bus_dat_w[7:0];
-assign csrbank2_dfii_pi3_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd52));
-assign csrbank2_dfii_pi3_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd52));
+assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd22));
+assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd22));
+assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd23));
+assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd23));
+assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd24));
+assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd24));
assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
-assign csrbank2_dfii_pi0_address1_w = litedramcore_phaseinjector0_address_storage[14:8];
-assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[7:0];
+assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0];
assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
-assign csrbank2_dfii_pi0_wrdata3_w = litedramcore_phaseinjector0_wrdata_storage[31:24];
-assign csrbank2_dfii_pi0_wrdata2_w = litedramcore_phaseinjector0_wrdata_storage[23:16];
-assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[15:8];
-assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[7:0];
-assign csrbank2_dfii_pi0_rddata3_w = litedramcore_phaseinjector0_status[31:24];
-assign csrbank2_dfii_pi0_rddata2_w = litedramcore_phaseinjector0_status[23:16];
-assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_status[15:8];
-assign csrbank2_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_status[7:0];
-assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata0_we;
+assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
+assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_status[31:0];
+assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata_we;
assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
-assign csrbank2_dfii_pi1_address1_w = litedramcore_phaseinjector1_address_storage[14:8];
-assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[7:0];
+assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[14:0];
assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
-assign csrbank2_dfii_pi1_wrdata3_w = litedramcore_phaseinjector1_wrdata_storage[31:24];
-assign csrbank2_dfii_pi1_wrdata2_w = litedramcore_phaseinjector1_wrdata_storage[23:16];
-assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[15:8];
-assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[7:0];
-assign csrbank2_dfii_pi1_rddata3_w = litedramcore_phaseinjector1_status[31:24];
-assign csrbank2_dfii_pi1_rddata2_w = litedramcore_phaseinjector1_status[23:16];
-assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_status[15:8];
-assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_status[7:0];
-assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata0_we;
+assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
+assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_status[31:0];
+assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata_we;
assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
-assign csrbank2_dfii_pi2_address1_w = litedramcore_phaseinjector2_address_storage[14:8];
-assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[7:0];
+assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[14:0];
assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
-assign csrbank2_dfii_pi2_wrdata3_w = litedramcore_phaseinjector2_wrdata_storage[31:24];
-assign csrbank2_dfii_pi2_wrdata2_w = litedramcore_phaseinjector2_wrdata_storage[23:16];
-assign csrbank2_dfii_pi2_wrdata1_w = litedramcore_phaseinjector2_wrdata_storage[15:8];
-assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[7:0];
-assign csrbank2_dfii_pi2_rddata3_w = litedramcore_phaseinjector2_status[31:24];
-assign csrbank2_dfii_pi2_rddata2_w = litedramcore_phaseinjector2_status[23:16];
-assign csrbank2_dfii_pi2_rddata1_w = litedramcore_phaseinjector2_status[15:8];
-assign csrbank2_dfii_pi2_rddata0_w = litedramcore_phaseinjector2_status[7:0];
-assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata0_we;
+assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0];
+assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_status[31:0];
+assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata_we;
assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
-assign csrbank2_dfii_pi3_address1_w = litedramcore_phaseinjector3_address_storage[14:8];
-assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[7:0];
+assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[14:0];
assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
-assign csrbank2_dfii_pi3_wrdata3_w = litedramcore_phaseinjector3_wrdata_storage[31:24];
-assign csrbank2_dfii_pi3_wrdata2_w = litedramcore_phaseinjector3_wrdata_storage[23:16];
-assign csrbank2_dfii_pi3_wrdata1_w = litedramcore_phaseinjector3_wrdata_storage[15:8];
-assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[7:0];
-assign csrbank2_dfii_pi3_rddata3_w = litedramcore_phaseinjector3_status[31:24];
-assign csrbank2_dfii_pi3_rddata2_w = litedramcore_phaseinjector3_status[23:16];
-assign csrbank2_dfii_pi3_rddata1_w = litedramcore_phaseinjector3_status[15:8];
-assign csrbank2_dfii_pi3_rddata0_w = litedramcore_phaseinjector3_status[7:0];
-assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata0_we;
+assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
+assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0];
+assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata_we;
assign adr = csr_port_adr;
assign we = csr_port_we;
assign dat_w = csr_port_dat_w;
new_master_rdata_valid8 <= new_master_rdata_valid7;
interface0_bank_bus_dat_r <= 1'd0;
if (csrbank0_sel) begin
- case (interface0_bank_bus_adr[3])
+ case (interface0_bank_bus_adr[1])
1'd0: begin
interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
end
init_error_re <= csrbank0_init_error0_re;
interface1_bank_bus_dat_r <= 1'd0;
if (csrbank1_sel) begin
- case (interface1_bank_bus_adr[6:3])
+ case (interface1_bank_bus_adr[4:1])
1'd0: begin
interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
end
a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
interface2_bank_bus_dat_r <= 1'd0;
if (csrbank2_sel) begin
- case (interface2_bank_bus_adr[8:3])
+ case (interface2_bank_bus_adr[5:1])
1'd0: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
end
interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
end
2'd3: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address1_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
end
3'd4: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
end
3'd5: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
end
3'd6: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata3_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w;
end
3'd7: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata2_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
end
4'd8: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w;
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
end
4'd9: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
end
4'd10: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata3_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
end
4'd11: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata2_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
end
4'd12: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w;
end
4'd13: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
end
4'd14: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
end
4'd15: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
end
5'd16: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address1_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
end
5'd17: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
end
5'd18: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w;
end
5'd19: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata3_w;
- end
- 5'd20: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata2_w;
- end
- 5'd21: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w;
- end
- 5'd22: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
- end
- 5'd23: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata3_w;
- end
- 5'd24: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata2_w;
- end
- 5'd25: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w;
- end
- 5'd26: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w;
- end
- 5'd27: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
- end
- 5'd28: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
- end
- 5'd29: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address1_w;
- end
- 5'd30: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
- end
- 5'd31: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
- end
- 6'd32: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata3_w;
- end
- 6'd33: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata2_w;
- end
- 6'd34: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata1_w;
- end
- 6'd35: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
- end
- 6'd36: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata3_w;
- end
- 6'd37: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata2_w;
- end
- 6'd38: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata1_w;
- end
- 6'd39: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata0_w;
- end
- 6'd40: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
end
- 6'd41: begin
+ 5'd20: begin
interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
end
- 6'd42: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address1_w;
- end
- 6'd43: begin
+ 5'd21: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
end
- 6'd44: begin
+ 5'd22: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
end
- 6'd45: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata3_w;
- end
- 6'd46: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata2_w;
- end
- 6'd47: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata1_w;
- end
- 6'd48: begin
+ 5'd23: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
end
- 6'd49: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata3_w;
- end
- 6'd50: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata2_w;
- end
- 6'd51: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata1_w;
- end
- 6'd52: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata0_w;
+ 5'd24: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w;
end
endcase
end
litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
end
litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
- if (csrbank2_dfii_pi0_address1_re) begin
- litedramcore_phaseinjector0_address_storage[14:8] <= csrbank2_dfii_pi0_address1_r;
- end
if (csrbank2_dfii_pi0_address0_re) begin
- litedramcore_phaseinjector0_address_storage[7:0] <= csrbank2_dfii_pi0_address0_r;
+ litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r;
end
litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
if (csrbank2_dfii_pi0_baddress0_re) begin
litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
end
litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
- if (csrbank2_dfii_pi0_wrdata3_re) begin
- litedramcore_phaseinjector0_wrdata_storage[31:24] <= csrbank2_dfii_pi0_wrdata3_r;
- end
- if (csrbank2_dfii_pi0_wrdata2_re) begin
- litedramcore_phaseinjector0_wrdata_storage[23:16] <= csrbank2_dfii_pi0_wrdata2_r;
- end
- if (csrbank2_dfii_pi0_wrdata1_re) begin
- litedramcore_phaseinjector0_wrdata_storage[15:8] <= csrbank2_dfii_pi0_wrdata1_r;
- end
if (csrbank2_dfii_pi0_wrdata0_re) begin
- litedramcore_phaseinjector0_wrdata_storage[7:0] <= csrbank2_dfii_pi0_wrdata0_r;
+ litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
end
litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
if (csrbank2_dfii_pi1_command0_re) begin
litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
end
litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
- if (csrbank2_dfii_pi1_address1_re) begin
- litedramcore_phaseinjector1_address_storage[14:8] <= csrbank2_dfii_pi1_address1_r;
- end
if (csrbank2_dfii_pi1_address0_re) begin
- litedramcore_phaseinjector1_address_storage[7:0] <= csrbank2_dfii_pi1_address0_r;
+ litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r;
end
litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
if (csrbank2_dfii_pi1_baddress0_re) begin
litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
end
litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
- if (csrbank2_dfii_pi1_wrdata3_re) begin
- litedramcore_phaseinjector1_wrdata_storage[31:24] <= csrbank2_dfii_pi1_wrdata3_r;
- end
- if (csrbank2_dfii_pi1_wrdata2_re) begin
- litedramcore_phaseinjector1_wrdata_storage[23:16] <= csrbank2_dfii_pi1_wrdata2_r;
- end
- if (csrbank2_dfii_pi1_wrdata1_re) begin
- litedramcore_phaseinjector1_wrdata_storage[15:8] <= csrbank2_dfii_pi1_wrdata1_r;
- end
if (csrbank2_dfii_pi1_wrdata0_re) begin
- litedramcore_phaseinjector1_wrdata_storage[7:0] <= csrbank2_dfii_pi1_wrdata0_r;
+ litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
end
litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
if (csrbank2_dfii_pi2_command0_re) begin
litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
end
litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
- if (csrbank2_dfii_pi2_address1_re) begin
- litedramcore_phaseinjector2_address_storage[14:8] <= csrbank2_dfii_pi2_address1_r;
- end
if (csrbank2_dfii_pi2_address0_re) begin
- litedramcore_phaseinjector2_address_storage[7:0] <= csrbank2_dfii_pi2_address0_r;
+ litedramcore_phaseinjector2_address_storage[14:0] <= csrbank2_dfii_pi2_address0_r;
end
litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
if (csrbank2_dfii_pi2_baddress0_re) begin
litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
end
litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
- if (csrbank2_dfii_pi2_wrdata3_re) begin
- litedramcore_phaseinjector2_wrdata_storage[31:24] <= csrbank2_dfii_pi2_wrdata3_r;
- end
- if (csrbank2_dfii_pi2_wrdata2_re) begin
- litedramcore_phaseinjector2_wrdata_storage[23:16] <= csrbank2_dfii_pi2_wrdata2_r;
- end
- if (csrbank2_dfii_pi2_wrdata1_re) begin
- litedramcore_phaseinjector2_wrdata_storage[15:8] <= csrbank2_dfii_pi2_wrdata1_r;
- end
if (csrbank2_dfii_pi2_wrdata0_re) begin
- litedramcore_phaseinjector2_wrdata_storage[7:0] <= csrbank2_dfii_pi2_wrdata0_r;
+ litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
end
litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
if (csrbank2_dfii_pi3_command0_re) begin
litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
end
litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
- if (csrbank2_dfii_pi3_address1_re) begin
- litedramcore_phaseinjector3_address_storage[14:8] <= csrbank2_dfii_pi3_address1_r;
- end
if (csrbank2_dfii_pi3_address0_re) begin
- litedramcore_phaseinjector3_address_storage[7:0] <= csrbank2_dfii_pi3_address0_r;
+ litedramcore_phaseinjector3_address_storage[14:0] <= csrbank2_dfii_pi3_address0_r;
end
litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
if (csrbank2_dfii_pi3_baddress0_re) begin
litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
end
litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
- if (csrbank2_dfii_pi3_wrdata3_re) begin
- litedramcore_phaseinjector3_wrdata_storage[31:24] <= csrbank2_dfii_pi3_wrdata3_r;
- end
- if (csrbank2_dfii_pi3_wrdata2_re) begin
- litedramcore_phaseinjector3_wrdata_storage[23:16] <= csrbank2_dfii_pi3_wrdata2_r;
- end
- if (csrbank2_dfii_pi3_wrdata1_re) begin
- litedramcore_phaseinjector3_wrdata_storage[15:8] <= csrbank2_dfii_pi3_wrdata1_r;
- end
if (csrbank2_dfii_pi3_wrdata0_re) begin
- litedramcore_phaseinjector3_wrdata_storage[7:0] <= csrbank2_dfii_pi3_wrdata0_r;
+ litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
end
litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
if (sys_rst) begin
projects / microwatt.git / commitdiff