add OP_RFID SRR0/SRR1 in PowerDecode2

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index f166bec26ec35521bd568f5b08ad3b9bf4503b1a..9dcf9e3f293d18e4e72d30aa45b04cd40a971104 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -241,6 +241,12 @@ class DecodeOut(Elaboratable):
             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
                 comb += self.fast_out.ok.eq(1)
+
+        # RFID 1st spr (fast)
+        with m.If(op.internal_op == InternalOp.OP_RFID):
+                comb += self.fast_out.data.eq(FastRegs.SRR0) # constant: SRR0
+                comb += self.fast_out.ok.eq(1)
+
         return m
 
 
@@ -275,6 +281,11 @@ class DecodeOut2(Elaboratable):
                 comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR
                 comb += self.fast_out.ok.eq(1)
 
+        # RFID 2nd spr (fast)
+        with m.If(op.internal_op == InternalOp.OP_RFID):
+                comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1
+                comb += self.fast_out.ok.eq(1)
+
         return m