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add bus.err to list of default Wishbone signals in Tercel
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 29 Mar 2022 19:43:10 +0000 (20:43 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 29 Mar 2022 19:43:10 +0000 (20:43 +0100)

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