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diff --git a/openpower/sv/predication.mdwn b/openpower/sv/predication.mdwn
index d3c72279835f9f9002e261a4b2bf164916feb99d..c4bc0897fa551622fd819b1d34dcb18688e8a459 100644 (file)
--- a/openpower/sv/predication.mdwn
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@@ -25,7 +25,7 @@
 * two modes, "zeroing" and "non-zeroing". zeroing mode places a zero in the masked-out element results, where non-zeroing leaves the destination (result) element unmodified.
 * predicate must be invertable via an opcode bit (to avoid the need for an instruction which inverts all bits of the predicate mask)
 
-Implementation note: even in in-order microarchitectures it is strongly adviseable to use byte-level write-enable lines on the register file.  This in combination with 8-bit SIMD element overrides allows, in "non-zeroing" mode, the predicate mask to be directly ANDed with the regfile write-enable lines to achieve the required functionality.  The alternative is to perform a READ-MODIFY-MASK-WRITE cycle which is costly and compromises performance.  Avoided very simply with byte-level write-enable.
+Implementation note: even in in-order microarchitectures it is strongly adviseable to use byte-level write-enable lines on the register file.  This in combination with 8-bit SIMD element overrides allows, in "non-zeroing" mode, the predicate mask can very simply be directly ANDed with the regfile write-enable lines to achieve the required functionality of leaving masked-out elements unmodified.  The alternative is to perform a READ-MODIFY-MASK-WRITE cycle which is costly and compromises performance.  Avoided very simply with byte-level write-enable.
 
 ## General implications and considerations