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authorlkcl <lkcl@web>
Sun, 3 May 2020 13:20:43 +0000 (14:20 +0100)
committerIkiWiki <ikiwiki.info>
Sun, 3 May 2020 13:20:43 +0000 (14:20 +0100)
3d_gpu/architecture/regfile.mdwn [new file with mode: 0644]

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+# Register Files
+
+A minimum of 3 register files are required for POWER:
+
+* Floating-point
+* Integer
+* Control and Condition Code Registers (CR0-7, CTR, LR)
+* SPRs (Special Purpose Registers)
+
+The FP and Integer registers need to be a massive 128 x 64-bit.
+
+# Connectivity between regfiles and Function Units
+
+[[!img regfile_hilo_32_odd_even.reg]]