add FP load test lfsx

diff --git a/src/openpower/decoder/helpers.py b/src/openpower/decoder/helpers.py
index e73c8371bf9eb148657bcb74fcd25ae9318a0cca..b93d51bee3068bcca6715c48a696d1af4b60c889 100644 (file)
--- a/src/openpower/decoder/helpers.py
+++ b/src/openpower/decoder/helpers.py
@@ -154,11 +154,18 @@ def DOUBLE(WORD):
     """convert incoming WORD to double.  v3.0B p140 section 4.6.2
     """
     # result, FRT, start off all zeros
+    print ("WORD", WORD)
     FRT = SelectableInt(0, 64)
     z1 = SelectableInt(0, 1)
     z29 = SelectableInt(0, 29)
+    e = WORD[1:9]
+    m = WORD[9:32]
+    s = WORD[0]
+    print ("word s e m", s, e, m)
+
     # Normalized Operand
-    if WORD[1:9] > 0 and WORD[1:9] < 255:
+    if e.value > 0 and e.value  < 255:
+        print ("normalised")
         FRT[0:2] = WORD[0:2]
         FRT[2] = ~WORD[1]
         FRT[3] = ~WORD[1]
@@ -166,12 +173,13 @@ def DOUBLE(WORD):
         FRT[5:64] = selectconcat(WORD[2:32], z29)
 
     # Denormalized Operand
-    if WORD[1:9] == 0 and WORD[9:32] != 0:
+    if e.value  == 0 and m.value  != 0:
+        print ("denormalised")
         sign = WORD[0]
         exp = -126
         frac = selectconcat(z1, WORD[9:32], z29)
         # normalize the operand
-        while frac[0] == 0:
+        while frac[0].value  == 0:
             frac[0:53] = selectconcat(frac[1:53], z1)
             exp = exp - 1
         FRT[0] = sign
@@ -179,13 +187,17 @@ def DOUBLE(WORD):
         FRT[12:64] = frac[1:53]
 
     # Zero / Infinity / NaN
-    if WORD[1:9] == 255 or WORD[1:32] == 0:
+    if e.value  == 255 or m.value  == 0:
+        print ("z/inf/nan")
         FRT[0:2] = WORD[0:2]
         FRT[2] = WORD[1]
         FRT[3] = WORD[1]
         FRT[4] = WORD[1]
         FRT[5:64] = selectconcat(WORD[2:32], z29)
 
+    print ("Double s e m", FRT[0].value, FRT[1:12].value-1023,
+                           FRT[12:64].value)
+
     return FRT
 
 
@@ -196,17 +208,17 @@ def SINGLE(FRS):
     WORD = SelectableInt(0, 32)
 
     #No Denormalization Required (includes Zero / Infinity / NaN)
-    if FRS[1:12] > 896 or FRS[1:64] == 0:
+    if FRS[1:12].value > 896 or FRS[1:64].value  == 0:
           WORD[0:2] = FRS[0:2]
           WORD[2:32] = FRS[5:35]
 
     #Denormalization Required
-    if FRS[1:12] >= 874 and FRS[1:12] <= 896:
+    if FRS[1:12].value  >= 874 and FRS[1:12].value  <= 896:
           sign = FRS[0]
           exp = FRS[1:12] - 1023
           frac = selectconcat(SelectableInt(1, 1), FRS[12:64])
           # denormalize operand
-          while exp < -126:
+          while exp.value  < -126:
               frac[0:53] = selectconcat(SelectableInt(0, 1), frac[0:52])
               exp = exp + 1
           WORD[0] = sign

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 26e88d03e9dd5853a37549c7719c3fb5a53b4423..b8e4f1d368b1b7a2cda5479e8aba82e9ffc0f2ef 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1193,7 +1193,11 @@ class ISACaller:
                                                      is_vec)
                         output = SelectableInt(0, 256)
                     else:
-                        print('writing reg %d %s' % (regnum, str(output)),
+                        if name in fregs:
+                            ftype = 'fpr'
+                        else:
+                            ftype = 'gpr'
+                        print('writing %s %s %s' % (regnum, ftype, str(output)),
                                                      is_vec)
                     if output.bits > 64:
                         output = SelectableInt(output.value, 64)

diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py
index a28e1eef208b1a33f90916887508ceaf0f07732d..05b7ebd256d12d2aacf7dc0b74a1d2afcb473a78 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_fp.py
+++ b/src/openpower/decoder/isa/test_caller_fp.py
@@ -23,20 +23,20 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.fpr(i), SelectableInt(expected_fpr[i], 64))
 
     def test_fpload(self):
-        """>>> lst = ["lfsx 1, 0, 0x0008",
+        """>>> lst = ["lfsx 1, 0, 0",
                      ]
         """
-        lst = ["lfsx 1, 0, 0x0008",
+        lst = ["lfsx 1, 0, 0",
                      ]
-        initial_mem = {0x0000: (0x4040266666666666, 8),
-                       0x0008: (0xabcdef0187654321, 8),
+        initial_mem = {0x0000: (0x42013333, 8),
+                       0x0008: (0x42026666, 8),
                        0x0020: (0x1828384822324252, 8),
                         }
 
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, initial_mem=initial_mem)
             print("FPR 1", sim.fpr(1))
-            self.assertEqual(sim.fpr(1), SelectableInt(0x4040266666666666, 64))
+            self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64))
 
     def run_tst_program(self, prog, initial_regs=None,
                               initial_mem=None):

diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index 5b82bd447d1efb1a1f29d77566ebad11780edfad..f54bd107150a5cd949a3cd9f6e758d35e48e29e6 100644 (file)
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -138,6 +138,20 @@ class DecodeA(Elaboratable):
             comb += reg.data.eq(rs)
             comb += reg.ok.eq(1)
 
+        # select Register FRA field,
+        fra = Signal(5, reset_less=True)
+        comb += fra.eq(self.dec.FRA)
+        with m.If(self.sel_in == In1Sel.FRA):
+            comb += reg.data.eq(fra)
+            comb += reg.ok.eq(1)
+
+        # select Register FRS field,
+        frs = Signal(5, reset_less=True)
+        comb += frs.eq(self.dec.FRS)
+        with m.If(self.sel_in == In1Sel.FRS):
+            comb += reg.data.eq(frs)
+            comb += reg.ok.eq(1)
+
         # decode Fast-SPR based on instruction type
         with m.Switch(op.internal_op):
 
@@ -219,6 +233,9 @@ class DecodeB(Elaboratable):
 
         # select Register B field
         with m.Switch(self.sel_in):
+            with m.Case(In2Sel.FRB):
+                comb += reg.data.eq(self.dec.FRB)
+                comb += reg.ok.eq(1)
             with m.Case(In2Sel.RB):
                 comb += reg.data.eq(self.dec.RB)
                 comb += reg.ok.eq(1)
@@ -327,6 +344,12 @@ class DecodeC(Elaboratable):
                 # for M-Form shiftrot
                 comb += reg.data.eq(self.dec.RB)
                 comb += reg.ok.eq(1)
+            with m.Case(In3Sel.FRS):
+                comb += reg.data.eq(self.dec.FRS)
+                comb += reg.ok.eq(1)
+            with m.Case(In3Sel.FRC):
+                comb += reg.data.eq(self.dec.FRC)
+                comb += reg.ok.eq(1)
             with m.Case(In3Sel.RS):
                 comb += reg.data.eq(self.dec.RS)
                 comb += reg.ok.eq(1)
@@ -362,6 +385,9 @@ class DecodeOut(Elaboratable):
 
         # select Register out field
         with m.Switch(self.sel_in):
+            with m.Case(OutSel.FRT):
+                comb += reg.data.eq(self.dec.FRT)
+                comb += reg.ok.eq(1)
             with m.Case(OutSel.RT):
                 comb += reg.data.eq(self.dec.RT)
                 comb += reg.ok.eq(1)

diff --git a/src/openpower/decoder/power_fields.py b/src/openpower/decoder/power_fields.py
index 9cc7d43699d35ecb10393382b38faec3c807056e..16e7fdff6d5fcc5f503d061595639b9b6072e92a 100644 (file)
--- a/src/openpower/decoder/power_fields.py
+++ b/src/openpower/decoder/power_fields.py
@@ -137,6 +137,11 @@ class DecodeFields:
         # note: these are from microwatt insn_helpers.vhdl
         self.common_fields = {
             "PO": self.Formall.PO,
+            "FRS": self.FormX.FRS,
+            "FRT": self.FormX.FRT,
+            "FRA": self.FormX.FRA,
+            "FRB": self.FormX.FRB,
+            "FRC": self.FormX.FRB,
             "RS": self.FormX.RS,
             "RT": self.FormX.RT,
             "RA": self.FormX.RA,