(no commit message)

diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index 7c72f557197d26d04a1a30ed944e2808efc11577..890f2c6953dcc177819d795fc607da8d915bf048 100644 (file)
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -225,7 +225,7 @@ acts as if SV had not been applied at all to the instruction  (an
 The fact that `VL` is dynamic and can be set to any value at runtime based
 on program conditions and behaviour means very specifically that
 `scalar identity behaviour` is **not** a redundant encoding. If the
-only means by which VL cold be set was by way of static-compiled
+only means by which VL could be set was by way of static-compiled
 immediates then this assertion would be false.  VL should not
 be confused with MAXVL when understanding this key aspect of SimpleV.
 
@@ -259,6 +259,11 @@ future versions of SV may involve 256 or greater registers. Backwards
 binary compatibility may be achieved with a PCR bit (Program Compatibility
 Register).  Further discussion is out of scope for this version of SVP64.
 
+Additionally, a future variant of SVP64 will be applied to the Scalar
+(Quad-precision and 128-bit) VSX instructions. Element-width overrides
+are an opportunity to expand the Power ISA to 256-bit, 512-bit and
+1024-bit operations.
+
 --------
 
 \newpage{}