set address ok and fix unit test to check it properly

diff --git a/src/soc/experiment/pi2ls.py b/src/soc/experiment/pi2ls.py
index 11cd1ab53c7f66b211fcf0ea9b00da0e4dd7cad1..3fe43b73d4896e5b6f27585743c7dee32abb9d4d 100644 (file)
--- a/src/soc/experiment/pi2ls.py
+++ b/src/soc/experiment/pi2ls.py
@@ -63,6 +63,8 @@ class Pi2LSUI(Elaboratable):
             # pass through the address, indicate "valid"
             m.d.comb += lsui.x_addr_i.eq(pi.addr.data) # full address
             m.d.comb += lsui.x_valid_i.eq(1)
+            # indicate "OK" - XXX should be checking address valid
+            m.d.comb += pi.addr_ok_o.eq(1)
 
         with m.If(pi.is_ld_i):
             m.d.comb += pi.ld.data.eq(lsui.m_ld_data_o)

diff --git a/src/soc/experiment/test/test_pi2ls.py b/src/soc/experiment/test/test_pi2ls.py
index 705d691cd3dc2ed307eb2f070b0677c5425dfc6b..eda2f51514cbbc21610e847e36293d7cbcb4bccc 100644 (file)
--- a/src/soc/experiment/test/test_pi2ls.py
+++ b/src/soc/experiment/test/test_pi2ls.py
@@ -21,7 +21,7 @@ def wait_addr(port):
     while True:
         addr_ok = yield port.pi.addr_ok_o
         print("addrok", addr_ok)
-        if not addr_ok:
+        if addr_ok:
             break
         yield
 
@@ -50,6 +50,7 @@ def l0_cache_st(dut, addr, data, datalen):
 
     yield port1.pi.addr.data.eq(addr)  # set address
     yield port1.pi.addr.ok.eq(1)  # set ok
+    yield Settle()
     yield from wait_addr(port1)             # wait until addr ok
     # yield # not needed, just for checking
     # yield # not needed, just for checking
@@ -81,6 +82,7 @@ def l0_cache_ld(dut, addr, datalen, expected):
 
     yield port1.pi.addr.data.eq(addr)  # set address
     yield port1.pi.addr.ok.eq(1)  # set ok
+    yield Settle()
     yield from wait_addr(port1)             # wait until addr ok
 
     yield from wait_ldok(port1)             # wait until ld ok
@@ -101,10 +103,17 @@ def l0_cache_ldst(arg, dut):
     data2 = 0xf00f
     #data = 0x4
     yield from l0_cache_st(dut, 0x2, data, 2)
+    yield
+    yield
     yield from l0_cache_st(dut, 0x4, data2, 2)
+    yield
+    yield
     result = yield from l0_cache_ld(dut, 0x2, 2, data)
+    yield
+    yield
     result2 = yield from l0_cache_ld(dut, 0x4, 2, data2)
     yield
+    yield
     arg.assertEqual(data, result, "data %x != %x" % (result, data))
     arg.assertEqual(data2, result2, "data2 %x != %x" % (result2, data2))