move para

diff --git a/openpower/sv/executive_summary.mdwn b/openpower/sv/executive_summary.mdwn
index f0e2ca470ac8e40e8ea971e4d79a8039b625d082..e12817b9c520eef792fd315be7b13210548708bf 100644 (file)
--- a/openpower/sv/executive_summary.mdwn
+++ b/openpower/sv/executive_summary.mdwn
@@ -7,12 +7,6 @@ allocation of opcodes (five) to implement, whereas any other Vector
 implementation would require an intrusive fundamental overhaul of the
 Power ISA.
 
-*If not done as carefully as SVP64, the addition of any other Scalable
-Vector Extension would require a significant number of opcodes, putting
-further pressure on Major Opcode space which was never designed with
-Scalable Vectors in mind in the first place.  Contrast with RISC-V which was
-designed over a 7 year period with Cray-style Vectors right from the start.*
-
 It is extremely important to think of Simple-V as a 2-Dimensional ISA:
 instructions vertical and registers horizontal otherwise it will be
 difficult to grasp and appreciate its RISC simplicity.
@@ -32,6 +26,12 @@ All implementations regardless of back-end capability may execute the exact
 same binaries *(this is known to be extremely important to the Power ISA
 ecosystem)*.
 
+*If not done as carefully as SVP64, the addition of any other Scalable
+Vector Extension would require a significant number of opcodes, putting
+further pressure on Major Opcode space which was never designed with
+Scalable Vectors in mind in the first place.  Contrast with RISC-V which was
+designed over a 7 year period with Cray-style Vectors right from the start.*
+
 Simple-V is **not RISC-V and is not RISC-V Vectors**.
 [NEC SX Aurora](https://sxauroratsubasa.sakura.ne.jp/documents/guide/pdfs/Aurora_ISA_guide.pdf),
 [RVV](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc), [Simple-V](https://ftp.libre-soc.org/simple_v_spec.pdf) and