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diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
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 # Condition Register SVP64 Operations
 
+Links:
+
+* <https://bugs.libre-soc.org/show_bug.cgi?id=687>
+
 Condition Register Fields are only 4 bits wide: this presents some
 interesting conceptual challenges for SVP64, particularly with respect to element
 width (which is clearly meaningless for a 4-bit