create single-stage ALU pipeline, shorten latency on in-order core

diff --git a/src/soc/fu/alu/pipeline.py b/src/soc/fu/alu/pipeline.py
index 87ca1356a6e4de3e70b1562a5616ea0ba073e5a0..a9c4f337be5c5c247efa016032d03efd0d8e959c 100644 (file)
--- a/src/soc/fu/alu/pipeline.py
+++ b/src/soc/fu/alu/pipeline.py
@@ -4,11 +4,12 @@ from soc.fu.alu.input_stage import ALUInputStage
 from soc.fu.alu.main_stage import ALUMainStage
 from soc.fu.alu.output_stage import ALUOutputStage
 
-class ALUStages(PipeModBaseChain):
+
+class ALUStagesOld(PipeModBaseChain):
     def get_chain(self):
         inp = ALUInputStage(self.pspec)
         main = ALUMainStage(self.pspec)
-        return [inp, main]
+        return [inp, main, out]
 
 
 class ALUStageEnd(PipeModBaseChain):
@@ -17,7 +18,7 @@ class ALUStageEnd(PipeModBaseChain):
         return [out]
 
 
-class ALUBasePipe(ControlBase):
+class ALUBasePipeOld(ControlBase):
     def __init__(self, pspec):
         ControlBase.__init__(self)
         self.pspec = pspec
@@ -31,3 +32,25 @@ class ALUBasePipe(ControlBase):
         m.submodules.pipe2 = self.pipe2
         m.d.comb += self._eqs
         return m
+
+
+class ALUStages(PipeModBaseChain):
+    def get_chain(self):
+        inp = ALUInputStage(self.pspec)
+        main = ALUMainStage(self.pspec)
+        out = ALUOutputStage(self.pspec)
+        return [inp, main, out]
+
+
+class ALUBasePipe(ControlBase):
+    def __init__(self, pspec):
+        ControlBase.__init__(self)
+        self.pspec = pspec
+        self.pipe1 = ALUStages(pspec)
+        self._eqs = self.connect([self.pipe1])
+
+    def elaborate(self, platform):
+        m = ControlBase.elaborate(self, platform)
+        m.submodules.pipe1 = self.pipe1
+        m.d.comb += self._eqs
+        return m