Fix bug in test_decoder_gas

diff --git a/src/soc/decoder/test/test_decoder_gas.py b/src/soc/decoder/test/test_decoder_gas.py
index be3f42b7ba407c1efc4d5da347308e5f963b11b8..39d087b77e5206a5f644e760632ce00778b94c31 100644 (file)
--- a/src/soc/decoder/test/test_decoder_gas.py
+++ b/src/soc/decoder/test/test_decoder_gas.py
@@ -429,7 +429,7 @@ class DecoderTestCase(FHDLTestCase):
 
         sim.add_process(process)
         with sim.write_vcd("%s.vcd" % name, "%s.gtkw" % name,
-                           traces=[pdecode2.ports()]):
+                           traces=pdecode2.ports()):
             sim.run()
 
     def test_reg_reg(self):