nmigen Case supports "-" as dont care, so can make use of that

diff --git a/openpower/isatables.mdwn b/openpower/isatables.mdwn
index 226e612f6727ded48707ea3e2e87fd166d017224..7affedc5fa3a310e0bcabfa2b783dee9f4188c03 100644 (file)
--- a/openpower/isatables.mdwn
+++ b/openpower/isatables.mdwn
@@ -6,29 +6,46 @@ Based on Anton Blanchard's microwatt decode1.vhdl
 
 # Major opcodes
 
+decodes using f_in.insn(31 downto 26)
+
 [[!table format=csv file="openpower/isatables/major.csv"]]
 
 # Minor opcode 19
 
+valid from table using f_in.insn(10 downto 1)
+
+decodes using f_in.insn(5) & f_in.insn(3) & f_in.insn(2)
+
 [[!table format=csv file="openpower/isatables/minor_19.csv"]]
 
 # Minor opcode 30
 
+decodes using f_in.insn(4 downto 1)
+
 [[!table format=csv file="openpower/isatables/minor_30.csv"]]
 
 # Minor opcode 31
 
+decodes using f_in.insn(10 downto 1)
+
 [[!table format=csv file="openpower/isatables/minor_31.csv"]]
 
 # Minor opcode 58
 
+decodes using f_in.insn(1 downto 0)
+
 [[!table format=csv file="openpower/isatables/minor_58.csv"]]
 
 # Minor opcode 62
 
+decodes using f_in.insn(1 downto 0)
+
 [[!table format=csv file="openpower/isatables/minor_62.csv"]]
 
 # Extra opcodes
 
+These can match against the (full) row[0] spec: nmigen Case supports "-" as
+"don't care"
+
 [[!table format=csv file="openpower/isatables/extra.csv"]]
 

diff --git a/openpower/isatables/extra.csv b/openpower/isatables/extra.csv
index a1f10f25931945d1eef60fe6f212a16f7793be15..b645c002193ed86cfc596a538b85861fff7022ee 100644 (file)
--- a/openpower/isatables/extra.csv
+++ b/openpower/isatables/extra.csv
@@ -1,4 +1,4 @@
 opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe, comment
-attn,ALU,OP_ILLEGAL,NONE,NONE,NONE,NONE,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,1,attn
-nop,ALU,OP_NOP,NONE,NONE,NONE,NONE,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,nop
-sim_cfg,ALU,OP_SIM_CONFIG,NONE,NONE,NONE,RT,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,sim_cfg
+000000---------------0100000000-,ALU,OP_ILLEGAL,NONE,NONE,NONE,NONE,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,1,attn
+01100000000000000000000000000000,ALU,OP_NOP,NONE,NONE,NONE,NONE,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,nop
+000001---------------0000000011-,ALU,OP_SIM_CONFIG,NONE,NONE,NONE,RT,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,sim_cfg