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diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index 254796f56dff2b46dbc7a9a452030194d6dbcd4a..18aa562fb34df188ce237f610fc2806d60fa2165 100644 (file)
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -163,6 +163,9 @@ When used with SVP64 Prefixing this is a [[sv/normal]]
 SVP64 type operation and as such can use RC1 Data-dependent
 Mode capability
 
+Hardware Architectural Note: when M=1 this instruction is a Read-Modify-Write
+on the `BF` CR Field. When M=0 it is a more normal Write.
+
 **mtcrweird**
 
     mtcrweird: BF,RA,M,fmsk,fmap
@@ -231,16 +234,20 @@ individual bits in BF may be set to 1 by ensuring that the required bit of
     n1 = fmsk[1] & (fmap[1] == creg[1])
     n2 = fmsk[2] & (fmap[2] == creg[2])
     n3 = fmsk[3] & (fmap[3] == creg[3])
-    bf = BT[2:4] # select CR field
-    bit = BT[0:1] # select bit of CR field
+
     n = (n0||n1||n2||n3) & fmsk
     result = (n != 0) if M else (n == fmsk)
-    CR{bf}[bit] = result
+    bf = BT[2:4] # select CR field
+    bit = BT[0:1] # select bit of CR field
+    CR{bf}[bit] = result # aka the usual "CR[32+BT] = result"
 
 When used with SVP64 Prefixing this is a [[sv/cr_ops]] SVP64
 type operation that has 5-bit Data-dependent and 5-bit Predicate-result
 capability (BT is 5 bits)
 
+Hardware Architectural Note: when M=1 this instruction is a Read-Modify-Write
+on the `BT` CR bit. When M=0 it is a more normal Write.
+
 **Example Pseudo-ops:**
 
     mtcri BF, fmap    mtcrweird BF, r0, 0, 0b1111,~fmap