uart: Make 16550 the default

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl
index 15e082b5cd35f632fc00916613aaeb8b7f7945f8..9dc476f7eb3558462fcbc0a192cf02b6d927906e 100644 (file)
--- a/fpga/top-arty.vhdl
+++ b/fpga/top-arty.vhdl
@@ -24,7 +24,7 @@ entity toplevel is
         LOG_LENGTH         : natural := 512;
         USE_LITEETH        : boolean  := false;
         UART_IS_16550      : boolean  := false;
-        HAS_UART1          : boolean  := false
+        HAS_UART1          : boolean  := true
         );
     port(
         ext_clk   : in  std_ulogic;

diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl
index 3f27af72c20532000785b438fecdea2f3cf12c2a..2300456b47e91e3567195a026d0816cd33c73360 100644 (file)
--- a/fpga/top-generic.vhdl
+++ b/fpga/top-generic.vhdl
@@ -12,7 +12,7 @@ entity toplevel is
        CLK_INPUT     : positive := 100000000;
        CLK_FREQUENCY : positive := 100000000;
        DISABLE_FLATTEN_CORE : boolean := false;
-        UART_IS_16550 : boolean  := false
+        UART_IS_16550 : boolean  := true
        );
     port(
        ext_clk   : in  std_ulogic;

diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl
index 5fc3bab448ad3a9fa91bd29bd423b1814f0f6215..ac760a1b13b71d2b07890149cff3cb7b7d340db6 100644 (file)
--- a/fpga/top-nexys-video.vhdl
+++ b/fpga/top-nexys-video.vhdl
@@ -20,7 +20,7 @@ entity toplevel is
         SPI_FLASH_OFFSET   : integer := 10485760;
         SPI_FLASH_DEF_CKDV : natural := 1;
         SPI_FLASH_DEF_QUAD : boolean := true;
-        UART_IS_16550      : boolean  := false;
+        UART_IS_16550      : boolean := true;
        );
     port(
        ext_clk   : in  std_ulogic;

diff --git a/microwatt.core b/microwatt.core
index 5fb81f5a06fc7ab824aacd93f3f5727385940711..046020d4c70e9bfc34e88b841b82ec82bbdea963 100644 (file)
--- a/microwatt.core
+++ b/microwatt.core
@@ -315,7 +315,7 @@ parameters:
     datatype    : bool
     description : Use 16550-compatible UART from OpenCores
     paramtype   : generic
-    default     : false
+    default     : true
 
   has_uart1:
     datatype    : bool

diff --git a/soc.vhdl b/soc.vhdl
index 6ff52d6d96ba4af11a36682498e7f954e3d49c7a..0a700260ad7f049b9468a0a6dab8bd093df514d7 100644 (file)
--- a/soc.vhdl
+++ b/soc.vhdl
@@ -63,7 +63,7 @@ entity soc is
         SPI_FLASH_DEF_QUAD : boolean := false;
         LOG_LENGTH         : natural := 512;
         HAS_LITEETH        : boolean := false;
-       UART0_IS_16550     : boolean := false;
+       UART0_IS_16550     : boolean := true;
        HAS_UART1          : boolean := false
        );
     port(