(no commit message)

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 780ab1b020c80dde9fca65a0c3e493391aadc00f..2df9910a72865b546d75bef8232d2d0ab3a514d6 100644 (file)
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -38,7 +38,7 @@ add such modes without changing the behaviour of the underlying Base
 Vectorisation of Load and Store requires creation, from scalar operations,
 a number of different modes:
 
-* fixed stride (contiguous sequence with no gaps) aka "unit" stride
+* fixed aka "unit" stride (contiguous sequence with no gaps)
 * element strided (sequential but regularly offset, with gaps)
 * vector indexed (vector of base addresses and vector of offsets)
 * Speculative fail-first (where it makes sense to do so)
@@ -47,6 +47,9 @@ a number of different modes:
 Also included in SVP64 LD/ST is both signed and unsigned Saturation,
 as well as Element-width overrides and Twin-Predication.
 
+*Despite being constructed from Scalar LD/ST none of these Modes
+exist or make sense in any Scalar ISA. They **only** exist in Vector ISAs*
+
 # Vectorisation of Scalar Power ISA v3.0B
 
 OpenPOWER Load/Store operations may be seen from [[isa/fixedload]] and