add more fields to svp64

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index f3fc150f21fb5a4e8ed30b982853552693ee2a85..229a7ffcf2ef022545b8c571db9e1950739fb4b6 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -34,14 +34,20 @@ There are two different encodings: single-predication (typically arithmetic oper
 
 ## Remapped Encoding Fields
 
-| Remapped Encoding Field Name | Field bits | Description                                                            |
-|------------------------------|------------|------------------------------------------------------------------------|
-| MASK_KIND                    | `0`        | Execution Mask Kind                                                    |
-| MASK                         | `1:3`      | Execution Mask                                                         |
-| ELWIDTH                      | `4:5`      | Element Width                                                          |
-| SUBVL                        | `6:7`      | Sub-vector length                                                      |
-| TBD                          | `8:23`     | TBD                                                                    |
-| MASK_SRC                     | TBD        | Execution Mask for Source (only on instructions with twin-predication) |
+| Remapped Encoding Field Name | Field bits | Description                                                               |
+|------------------------------|------------|---------------------------------------------------------------------------|
+| MASK_KIND                    | `0`        | Execution Mask Kind                                                       |
+| MASK                         | `1:3`      | Execution Mask                                                            |
+| ELWIDTH                      | `4:5`      | Element Width                                                             |
+| SUBVL                        | `6:7`      | Sub-vector length                                                         |
+| Rdest_EXTRA                  | `8:10`     | extra bits for Rdest                                                      |
+| Rsrc1_EXTRA                  | `11:13`    | extra bits for Rsrc1                                                      |
+| Rsrc2_EXTRA                  | `14:16`    | extra bits for Rsrc2                                                      |
+| Rsrc3_EXTRA                  | `17:19`    | extra bits for Rsrc3                                                      |
+| MASK_SRC                     | `14:16`    | Execution Mask for Source (only on instructions with twin-predication)    |
+| ELWIDTH_SRC                  | `17:18`    | Element Width for Source (only on instructions with twin-predication)     |
+| SUBVL_SRC                    | `19:20`    | Sub-vector length for Source (only on instructions with twin-predication) |
+| TBD                          | `21:23`    | TBD                                                                       |
 
 ## ELWIDTH Encoding