Revert ""

This reverts commit 68931b2ab1fe8f5053d0abad297705fa9411424f.

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 4187eff1dcf87940746717693e6d484f768e81da..82de8682dd79928477147e43f56618d67872caf6 100644 (file)
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -149,6 +149,20 @@ Available options to combine:
 * `ALL` or `ANY` behaviour corresponding to `AND` of all tests and
   `OR` of all tests, respectively.
 
+Pseudocode for Rc in sv.bc
+
+```
+# Use bit 30, disable AA
+Rc = AA
+AA = 0
+```
+
+Pseudocode for Rc in sv.bclr
+
+```
+Rc = instr[16]
+```
+
 Pseudocode for Horizontal-First Mode:
 
 ```
@@ -159,7 +173,8 @@ Pseudocode for Horizontal-First Mode:
         if predicate[srcstep]:
             # get SVP64 extended CR field 0..127
             SVCRf = SVP64EXTRA(BI>>2)
-            CR{SVCRf+srcstep} = CRbits
+            if Rc = 1 then # CR0 Vectorised
+                CR{0+srcstep} = CRbits
             testbit = CRbits[BI & 0b11]
             # testbit = CR[BI+32+srcstep*4]
         else if not SVRMmode.sz:
@@ -197,7 +212,8 @@ Pseudocode for Vertical-First Mode:
     if predicate[srcstep]:
         # get SVP64 extended CR field 0..127
         SVCRf = SVP64EXTRA(BI>>2)
-        CR{SVCRf+srcstep} = CRbits
+        if Rc = 1 then # CR0 vectorised
+            CR{0+srcstep} = CRbits
         testbit = CRbits[BI & 0b11]
     else if not SVRMmode.sz:
         SVSTATE.srcstep = new_srcstep