destarify debug

diff --git a/src/soc/minerva/units/debug/controller.py b/src/soc/minerva/units/debug/controller.py
index 31641baf10d84b7131067bbec231ee9655428fc4..7304303e577b14eebba15144642eb7bee829e107 100644 (file)
--- a/src/soc/minerva/units/debug/controller.py
+++ b/src/soc/minerva/units/debug/controller.py
@@ -1,8 +1,8 @@
-from nmigen import *
+from nmigen import Elaboratable, Module, Signal, Array, Record
 from nmigen.lib.coding import PriorityEncoder
 
-from ...csr import *
-from ...isa import *
+from ...csr import AutoCSR, CSR
+from ...isa import dcsr_layout, flat_layout
 from ...wishbone import wishbone_layout
 from .dmi import DebugReg, Command, Error, Version, cmd_access_reg_layout
 

diff --git a/src/soc/minerva/units/debug/jtag.py b/src/soc/minerva/units/debug/jtag.py
index e979789dcc04c50fc0be5d7de594222f320c70f3..331dd512ccd83aca22307801deee7e4d902af478 100644 (file)
--- a/src/soc/minerva/units/debug/jtag.py
+++ b/src/soc/minerva/units/debug/jtag.py
@@ -1,4 +1,4 @@
-from nmigen.hdl.rec import *
+from nmigen.hdl.rec import DIR_FANIN, DIR_FANOUT
 
 
 __all__ = ["jtag_layout", "JTAGReg", "dtmcs_layout", "dmi_layout"]

diff --git a/src/soc/minerva/units/debug/regfile.py b/src/soc/minerva/units/debug/regfile.py
index a27e3bd1b5b62e5a2466030cad09d7c95f32a61d..a7d3fd4f8dd5294c97a5ea170171daa128398f2c 100644 (file)
--- a/src/soc/minerva/units/debug/regfile.py
+++ b/src/soc/minerva/units/debug/regfile.py
@@ -1,7 +1,8 @@
-from nmigen import *
-from nmigen.hdl.rec import *
+from nmigen import Elaboratable, Module, Record, Const
 
-from .dmi import *
+from .dmi import (DebugReg, DmiOp, RegMode,
+                  abstractcs_layout, cmd_access_reg_layout, command_layout,
+                  dmcontrol_layout, dmstatus_layout, flat_layout, sbcs_layout)
 
 
 __all__ = ["DebugRegisterFile"]

diff --git a/src/soc/minerva/units/debug/top.py b/src/soc/minerva/units/debug/top.py
index e5cf40415f313c7c3e6863e7c9564a6489b28baf..53b92ebe0f1069ff56062908d56c7df66c7e3ffa 100644 (file)
--- a/src/soc/minerva/units/debug/top.py
+++ b/src/soc/minerva/units/debug/top.py
@@ -1,16 +1,14 @@
-from nmigen import *
-from nmigen.hdl.rec import *
+from nmigen import Elaboratable, Module, Signal, Record
 
 
-from ...csr import *
-from ...isa import *
+from ...csr import AutoCSR, CSR
 from ...wishbone import wishbone_layout
-from .controller import *
-from .dmi import *
-from .jtag import *
-from .regfile import *
-from .wbmaster import *
+from .controller import DebugController
+from .jtag import JTAGReg, dtmcs_layout, dmi_layout, jtag_layout
+from .regfile import DebugRegisterFile
+from .wbmaster import wishbone_layout, DebugWishboneMaster
 
+from jtagtap import JTAGTap
 
 __all__ = ["DebugUnit"]
 
@@ -69,7 +67,6 @@ class DebugUnit(Elaboratable, AutoCSR):
     def elaborate(self, platform):
         m = Module()
 
-        from jtagtap import JTAGTap
         tap        = m.submodules.tap        = JTAGTap(jtag_regs)
         regfile    = m.submodules.regfile    = DebugRegisterFile(tap.regs[JTAGReg.DMI])
         controller = m.submodules.controller = DebugController(regfile)

diff --git a/src/soc/minerva/units/debug/wbmaster.py b/src/soc/minerva/units/debug/wbmaster.py
index a47115686e1ecbf6b604ec04421ed6e02e780841..db02af95b4eb3ef8ac25b348f3abaa2bcbe7d96f 100644 (file)
--- a/src/soc/minerva/units/debug/wbmaster.py
+++ b/src/soc/minerva/units/debug/wbmaster.py
@@ -1,11 +1,10 @@
 from functools import reduce
 from operator import or_
 
-from nmigen import *
-from nmigen.hdl.rec import *
+from nmigen import Elaboratable, Module, Signal, Record
 
 from ...wishbone import wishbone_layout
-from .dmi import *
+from .dmi import DebugReg
 
 
 __all__ = ["BusError", "AccessSize", "DebugWishboneMaster"]